JPH11260954A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

(57) Abstract: In a semiconductor device having a solder bump formed by mounting a semiconductor chip on a wiring board and sealing the semiconductor chip with resin, PBGA and FCBGA absorb moisture without lowering the heat dissipation of the semiconductor chip. Even when heated in a state where the semiconductor chip is heated, the interface between the wiring board and the die bonding agent
Another object of the present invention is to provide a highly reliable semiconductor device which does not peel off at the interface between a semiconductor chip and a wiring substrate and a sealing resin and does not cause a popcorn phenomenon, and a method for manufacturing the same. A resist for protecting wiring formed on a wiring board and a resin film for protecting circuit elements on a semiconductor chip are exposed and developed with an opening diameter smaller than the minimum opening diameter that can be opened by exposure and development. By doing so, it is possible to form irregularities on the surface, improve the adhesive force with transfer mold, die bonding agent, sealing resin, and prevent defects such as peeling of the sealing resin and popcorn phenomenon that occurred conventionally. Can be.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a semiconductor chip mounted on a wiring board and sealing the semiconductor chip with a resin, and more particularly to a semiconductor device with solder bumps and a method of manufacturing the same. .

[0002]

2. Description of the Related Art In recent years, semiconductor devices having a large number of electrode terminals have been developed as electronic circuits become more sophisticated. A typical example is a plastic ball grid array (Pla) which is a surface mount type multi-terminal package.
stick Ball GridArray) (hereinafter P
Described as BGA. ) And flip chip ball grid array (Flip Chip Ball Grid)
Array) (hereinafter referred to as FCBGA).

[0003] A conventional technique will be described below with reference to the drawings. FIG. 35 is a sectional view showing a conventional PBGA. As shown in FIG. 35, a connection electrode 3 for wire bonding with the semiconductor chip 1 is provided on the upper surface side, a pad electrode 4 for providing solder bumps 6 is provided on the lower surface side, and a wiring in the center portion of the resin substrate 2 is provided. Thermal via holes 16 for connecting the pads 15 to the pad electrodes 4 to dissipate heat generated by the semiconductor chip 1, through holes 14 for connecting the connection electrodes 3 and the pad electrodes 4, and resists 5 for protecting the wiring 15 A semiconductor chip 1 fixed to a central portion of the wiring board 18 by a die bonding agent 7, a resin film 12 for protecting circuit elements on the semiconductor chip 1, and electrodes of the semiconductor chip 1. Wiring board 18
Bonding wires 8 for connecting the connection electrodes 3
And a transfer mold 9 for sealing the semiconductor chip 1 and the bonding wires 8, and a solder bump 6 on the pad electrode 4 of the wiring board 18.

Next, a method of manufacturing a PBGA will be described. 36 to 39 are cross-sectional views showing a manufacturing process of a conventional PBGA.

As shown in FIG. 36, the resin substrate 2 is made of a glass epoxy resin having a rectangular shape and a thickness of about 0.2 mm, and a copper foil 17 having a thickness of about 18 μm is provided on both upper and lower surfaces thereof. The resin substrate 2 is provided with thermal via holes 16 for heat radiation between the plurality of through holes 14 and the semiconductor chip 1 by cutting drilling. After cleaning the substrate surface including the wall surfaces of the through hole 14 and the thermal via hole 16, an electroless copper plating layer is provided on the entire surface of the resin substrate 2. The copper plating layer is formed up to the inside of the through hole 14 and the thermal via hole 16.

Next, a photosensitive dry film is adhered to the upper and lower surfaces of the resin substrate 2 and exposed and developed to form an etching resist film. Thereafter, an etching solution is sprayed on the upper and lower surfaces of the resin substrate 2 to remove exposed copper without an etching resist film. After this etching, the remaining etching resist film is removed. As shown in FIG. 37, the connection electrode 3 for wire bonding is formed on the upper surface of the resin substrate 2, the pad electrode 4 for forming the solder bump 6 is formed on the lower surface, and the wiring 15 is formed on both surfaces. Provided. The wiring 15 and the pad electrode 4 at the center of the resin substrate 2 are connected via a thermal via hole 16, and the connection electrode 3 and the pad electrode 4 corresponding to the opening of the resist are connected via a through hole 14.

[0007] Further, as shown in FIG.
A resist 5 is provided by laminating a resist on both sides of the resist 5 and performing exposure and development, and an opening is provided in the resist 5 at a portion corresponding to the connection electrode 3 and the pad electrode 4.

Next, a nickel plating layer having a thickness of about 2 to 5 μm is provided on the surfaces of the copper plating layers of the exposed electrodes on the upper and lower surfaces of the resin substrate 2. Further, on the surface of the nickel plating layer, there is provided a flash gold plating layer having a thickness of about 0.05 μm, which contains impurities such as cobalt and is apt to bite the nickel plating layer. Although not shown, the steps up to the copper plating layer, the nickel plating layer, and the flash gold plating layer are the base plating steps for providing the base plating layer.

Next, a thickness of 0.3 μm to 0.7 μm, which is excellent in conductivity with the bonding wire 8, is formed on the base plating layer.
A gold plating layer of about μm is provided. Although not shown, this step is a gold plating step for forming a gold plating layer. Thus, the wiring board 18 is completed.

[0010] Next, as shown in FIG.
The semiconductor chip 1 is fixed on the wiring board 18 by applying a die bonding agent 7 on the central portion on the upper surface side of the upper surface 8 and placing the semiconductor chip 1 thereon and drying it until the die bonding agent 7 is cured. The electrodes of the semiconductor chip 1 and the connection electrodes 3 on the wiring board 18 are electrically connected by bonding wires 8. Next, the semiconductor chip 1 and the bonding wires 8 are sealed with a transfer mold 9.

At this time, a resin film 12 for protecting circuit elements is formed on the semiconductor chip 1, and an electrode portion connected by wire bonding is opened by exposing and developing the resin film 12.

Next, solder balls having a diameter of 0.6 mm to 0.8 mm are supplied to the pad electrode 4 on the lower surface side of the wiring board 18 and heated by using a heating furnace, so that the solder bumps 6 are provided. This completes the PBGA.

FIG. 40 is a sectional view showing a conventional FCBGA. As shown in FIG. 40, a connection electrode 3 for flip-chip mounting the semiconductor chip 1 is provided on the upper surface side, a pad electrode 4 for providing solder bumps 6 on the lower surface side, and the connection electrode 3 and the pad electrode are further provided. 4, a wiring board 18 having a through hole 14 for connecting the wiring 4 and a resist 5 for protecting the wiring 15, a resin film 12 for protecting circuit elements on the semiconductor chip 1, and The formed protruding electrode 10, a connection material 13 such as a conductive adhesive or solder for connecting the connection electrode 3 and the protruding electrode 10, and a sealing resin 11 between the semiconductor chip 1 and the wiring board 18 are provided. In addition, the structure has a solder bump 6 on the pad electrode 4 of the wiring board 18.

Next, a method of manufacturing FCBGA will be described.
FIG. 41 to FIG. 44 are cross-sectional views showing the steps of manufacturing the FCBGA.

As shown in FIG. 41, the resin substrate 2 is made of a glass epoxy resin having a rectangular shape and a thickness of about 0.2 mm, and a copper foil 17 having a thickness of about 18 μm is provided on both upper and lower surfaces thereof. The resin substrate 2 is provided with a plurality of through holes 14 by cutting drilling. Through hole 1
After cleaning the substrate surface including the wall surface of No. 4, an electroless copper plating layer is provided on the entire surface of the resin substrate 2. The copper plating layer is formed even inside the through hole 14.

Next, a photosensitive dry film is adhered to the upper and lower surfaces of the resin substrate 2 and exposed and developed to form an etching resist film. Thereafter, an etching solution is sprayed on the upper and lower surfaces of the resin substrate 2 to remove exposed copper without an etching resist film. After this etching, the remaining etching resist film is removed. As shown in FIG. 42, a connection electrode 3 for flip-chip mounting the semiconductor chip 1 is formed on the upper surface of the resin substrate 2 and a pad electrode 4 for forming a solder bump is formed on the lower surface.
Then, the wiring 15 is provided on both surfaces. The connection electrode 3 corresponding to the opening and the pad electrode 4 are connected via a through hole 14.

Further, as shown in FIG.
The resist 5 is provided by laminating a resist on both sides of the substrate and performing exposure and development, and an opening of the resist 5 is provided in a portion corresponding to the connection electrode 3 and the pad electrode 4.

Next, a nickel plating layer having a thickness of about 2 to 5 μm is provided on the surfaces of the copper plating layers of the exposed electrodes on the upper and lower surfaces of the resin substrate 2. Further, on the surface of the nickel plating layer, there is provided a flash gold plating layer having a thickness of about 0.05 μm, which contains impurities such as cobalt and is apt to bite the nickel plating layer. Although not shown, the above steps up to the copper plating layer, the nickel plating layer, and the flash gold plating layer are the base plating steps of providing the base plating layer.

Next, a thickness of 0.3 μm
A gold plating layer of about m to 0.7 μm is provided. Although not shown, this step is a gold plating step for forming a gold plating layer. Thus, the wiring board 18 is completed.

Next, as shown in FIG. 44, the connection electrodes 3 on the upper surface side of the wiring board 18 formed by the method described above and the bump electrodes 10 formed on the semiconductor chip 1 are soldered or conductive adhesive. The connection is made with a connection material 13 such as
Thereafter, the semiconductor chip 1 is protected by flowing the sealing resin 11 from the end of the semiconductor chip 1 and thermosetting.

At this time, a resin film 12 for protecting circuit elements is formed on the semiconductor chip 1, and an electrode portion for forming the protruding electrode 10 is opened by exposing and developing the resin film 12.
The protruding electrode 10 is formed of a metal such as solder, copper, or gold by a plating method, a stud bump method, or the like.

Next, a solder ball having a diameter of 0.6 mm to 0.8 mm is supplied to the pad electrode 4 on the lower surface side of the wiring board 18 and heated by using a heating furnace, whereby the solder bump 6 is provided. This completes the FCBGA.

[0023]

The above-described semiconductor device has the following problems. Generally PBGA
And the FCBGA during the storage to some extent, the wiring board 1
8. Moisture is absorbed by the transfer mold 9 and the sealing resin 11. In this state, when the PBGA or FCBGA is mounted on the motherboard substrate by heating in a heating furnace, the absorbed moisture evaporates and expands, generating stress. At this time, peeling occurs at the interface between the resist 5 and the die bonding agent 7 on the central portion of the wiring board 18, which is the weakest in PBGA, and FCBG
In the case A, the resin film 12 for protecting the circuit elements on the semiconductor chip 1 and the resist 5 for protecting the wiring 15 on the wiring board 18 and the sealing resin 11 are separated at the interface. In addition, blistering occurs, which is commonly referred to as the popcorn phenomenon of the package.

Adjacent solder bumps 6 come into contact with each other due to the popcorn phenomenon, causing an electrical short circuit, moving the semiconductor chip 1 and breaking the bonding wires 8, thereby impairing the reliability of the semiconductor device.

In the wiring board 18, the thermal via holes 16 under the semiconductor chip 1 are provided to allow heat generated during the operation of the semiconductor chip 1 to pass through the solder bumps 6 and to radiate to the outside of the PBGA.

However, the thermal via hole 16 is a PBGA
Is a water inflow path when absorbing moisture. Although the lower surface of the thermal via hole 16 is covered with the resist 5, the moisture absorption penetrates the resist 5, passes through the thermal via hole 16 in the cavity, and is near the lower surface of the die bonding agent 7 fixing the semiconductor chip 1. Accumulate. Therefore, as the number of thermal via holes 16 increases, the amount of moisture absorbed in the PBGA increases, and the tendency for the popcorn phenomenon to occur increases.

Heretofore, the number of thermal via holes 16 has been reduced to prevent the popcorn phenomenon. However, reducing the number of thermal via holes 16 reduces the heat radiation effect of the semiconductor chip 1.

An object of the present invention is to solve the above-mentioned problems and to reduce the heat dissipation of PBGA and FCBGA without lowering the heat dissipation of the semiconductor chip, so that the semiconductor chip can be bonded to the center portion and the die bonding agent. An object of the present invention is to provide a highly reliable semiconductor device which does not peel off at an interface and does not cause a popcorn phenomenon, and a method for manufacturing the same.

[0029]

In order to achieve the above object, a semiconductor device and a method of manufacturing the same according to the present invention employ the following configurations and manufacturing methods.

The semiconductor device of the present invention has a connection electrode for wire bonding with a semiconductor chip on the upper surface side,
A pad electrode for providing solder bumps on the lower surface side, a thermal via hole for connecting the central portion of the resin substrate and the pad electrode to dissipate heat of the semiconductor chip, and for connecting the connection electrode and the pad electrode. To protect a wiring substrate having through holes and a resist having an uneven surface on the surface for protecting the wiring, a semiconductor chip fixed on a central portion of the wiring substrate with a die bonding agent, and a circuit element on the semiconductor chip. Resin film, a bonding wire for connecting the electrode of the semiconductor chip to the connection electrode of the wiring board, a transfer mold for sealing the semiconductor chip and the bonding wire, and a solder bump on the pad electrode of the wiring board. It is characterized by:

According to a second aspect of the present invention, there is provided a semiconductor device having a connection electrode for wire bonding with a semiconductor chip on an upper surface side, a pad electrode for providing solder bumps on a lower surface side, and a resin substrate. A wiring board including a thermal via hole for connecting the central portion of the pad electrode to the pad electrode to dissipate heat generated by the semiconductor chip, a through hole for connecting the connection electrode and the pad electrode, and a resist for protecting the wiring; A semiconductor chip fixed with a die bonding agent on a central portion of a wiring board, a resin film having an uneven surface for protecting circuit elements on the semiconductor chip, and connecting an electrode of the semiconductor chip to a connection electrode of the wiring board. Wire, a transfer mold for sealing the semiconductor chip and the bonding wire, and a It is characterized by having a solder bump on Tsu gate electrode.

According to a third aspect of the present invention, a semiconductor device according to the present invention includes a connection electrode for wire bonding with a semiconductor chip on an upper surface side, a pad electrode for providing a solder bump on a lower surface side, and a resin substrate. A thermal via hole for connecting the central portion of the pad and the pad electrode to dissipate heat generated by the semiconductor chip, a through hole for connecting the connection electrode and the pad electrode, and a resist having an uneven surface to protect the wiring. , A semiconductor chip fixed on a central portion of the wiring board with a die bonding agent, a resin film having an uneven surface for protecting circuit elements on the semiconductor chip, electrodes of the semiconductor chip, and a wiring board A bonding wire for connecting the connection electrodes of
It is characterized by having a transfer mold for sealing a semiconductor chip and a bonding wire and a solder bump on a pad electrode of a wiring board.

According to a fourth aspect of the present invention, a semiconductor device according to the present invention includes a connection electrode for flip-chip mounting a semiconductor chip on an upper surface side, and a pad electrode for providing a solder bump on a lower surface side. Wiring board with through-holes for connecting electrodes and pad electrodes, resist with uneven surface to protect wiring, connection electrodes formed on wiring board, and protection of circuit elements on semiconductor chip Resin film, a protruding electrode formed on the semiconductor chip, a connection material such as a conductive adhesive or solder for connecting the connection electrode and the protruding electrode, and a sealing resin between the semiconductor chip and the wiring board. And a solder bump on the pad electrode of the wiring board.

According to a fifth aspect of the present invention, there is provided a semiconductor device comprising a connection electrode for flip-chip mounting a semiconductor chip on an upper surface side, and a pad electrode for providing a solder bump on a lower surface side. A wiring board having a through hole for connecting the electrode and the pad electrode, a resist for protecting the wiring, a connection electrode formed on the wiring board, and a surface for protecting circuit elements on the semiconductor chip; A bumpy resin film, a bump electrode formed on the semiconductor chip, a connection material such as a conductive adhesive or solder for connecting the connection electrode and the bump electrode, and a sealing resin between the semiconductor chip and the wiring board. And a solder bump on the pad electrode of the wiring board.

According to a sixth aspect of the present invention, a semiconductor device according to the present invention includes a connection electrode for flip-chip mounting a semiconductor chip on an upper surface side, and a pad electrode for providing a solder bump on a lower surface side. Wiring board with through-holes for connecting electrodes and pad electrodes, resist with uneven surface to protect wiring, connection electrodes formed on wiring board, and protection of circuit elements on semiconductor chip Between the semiconductor chip and the wiring substrate, a resin film having an uneven surface, a protruding electrode formed on the semiconductor chip, a connecting material such as a conductive adhesive or solder for connecting the connecting electrode and the protruding electrode. Having a sealing resin,
It is characterized by having solder bumps on the pad electrodes of the wiring board.

Further, the method of manufacturing a semiconductor device according to the present invention
Drilling process to form thermal via holes for heat dissipation through holes of semiconductor chips and through holes for connecting upper and lower surfaces of resin substrate to resin substrate covered with copper foil on upper and lower surfaces, A copper plating step of providing a copper plating layer in a hole provided in the drilling step; a connection electrode connected to a semiconductor chip electrode and a bonding wire on an upper surface side of the resin substrate; and a solder bump on a lower surface side of the resin substrate. A patterning process for forming a pad electrode for forming a resist, a resist forming process for arranging a resist on a resin substrate, and forming a resist opening on the connection electrode and the pad electrode, and a surface on other portions. Process for forming a resist to protect the wiring with irregularities on the surface, and underlay plating for gold plating on the patterned copper plating layer A ground plating step, a gold plating step of forming a gold plating layer on the base plating layer, a resin film forming step of arranging a resin film on the semiconductor chip and opening an electrode portion, and a semiconductor chip on a central portion of the wiring board Die bonding step of fixing the semiconductor chip with a die bonding agent, a wire bonding step of connecting the fixed semiconductor chip electrode and the connection electrode of the wiring board with bonding wires, a semiconductor chip fixed on the wiring board, and the semiconductor chip and wiring A transfer molding process in which the bonding wires connecting the connection electrodes on the substrate are sealed with resin, and solder balls are supplied to the pad electrodes on the lower surface side of the wiring board and heated in a heating furnace so that the solder balls are placed on the pad electrodes. And a step of forming a solder bump.

In the method of manufacturing a semiconductor device according to the present invention, the thermal via hole of the heat dissipation through hole of the semiconductor chip and the upper and lower surfaces of the resin substrate are connected to the resin substrate having copper foils on the upper and lower surfaces. Drilling process to form through holes for making, a copper plating process of providing a copper plating layer in the entire surface of the resin substrate and holes provided in the drilling process, and a semiconductor chip on the upper surface side of the resin substrate. A connection electrode connected to the electrode by a bonding wire, a patterning step for forming a pad electrode for forming a solder bump on the lower surface side of the resin substrate, a resist disposed on the resin substrate, and a connection electrode and a pad; A resist forming step of forming a resist opening in the electrode, a base plating step of forming a base plating for gold plating on the patterned copper plating layer, and a base plating step; A gold plating step of forming a gold plating layer on a metal layer, a resin film forming step of arranging a resin film on a semiconductor chip and opening an electrode portion, and an unevenness forming step of forming unevenness on the surface of other portions And a die bonding step of fixing a semiconductor chip on a central portion of the wiring board with a die bonding agent, a wire bonding step of connecting electrodes of the fixed semiconductor chip and connection electrodes of the wiring board with bonding wires, and fixing on the wiring board. Transfer molding process to seal the semiconductor chip and the bonding wire connecting this semiconductor chip and the connection electrode on the wiring board with resin, and supply solder balls to the pad electrode on the lower side of the wiring board and heat it in a heating furnace. A soldering step, whereby the solder balls are fixed on the pad electrodes, and a solder bump is formed. To have.

According to a ninth aspect of the present invention, in a method of manufacturing a semiconductor device according to the present invention, a thermal via hole of a heat dissipation through hole of a semiconductor chip and upper and lower surfaces of a resin substrate are connected to a resin substrate having copper foils on upper and lower surfaces. Drilling process to form through holes for making, a copper plating process of providing a copper plating layer in the entire surface of the resin substrate and holes provided in the drilling process, and a semiconductor chip on the upper surface side of the resin substrate. A connection electrode connected to the electrode by a bonding wire, a patterning step for forming a pad electrode for forming a solder bump on the lower surface side of the resin substrate, a resist disposed on the resin substrate, and a connection electrode and a pad; A resist forming step for forming a resist opening in an electrode, and a concavo-convex forming step for forming a resist for protecting a wiring having a concavo-convex surface on other portions An underlying plating step of performing primary plating for gold plating on the copper plating layer was patterned,
A gold plating step of forming a gold plating layer on the base plating layer, a resin film forming step of arranging a resin film on a semiconductor chip and opening an electrode portion, and irregularities forming irregularities on the surface of other portions A forming step, a die bonding step of fixing a semiconductor chip on a central portion of the wiring board with a die bonding agent, a wire bonding step of connecting electrodes of the fixed semiconductor chip and connection electrodes of the wiring board with bonding wires, A semiconductor chip fixed to the semiconductor chip, a transfer molding step of sealing a bonding wire connecting the semiconductor chip and a connection electrode on the wiring board with a resin, and supplying solder balls to a pad electrode on the lower surface side of the wiring board to supply heat to a heating furnace. The solder ball is fixed on the pad electrode, and a solder bump is formed. It is characterized in.

According to a tenth aspect of the present invention, there is provided a method of manufacturing a semiconductor device according to the present invention, wherein a hole is formed in a resin substrate having copper foils on upper and lower surfaces to form through holes for connecting upper and lower surfaces of the resin substrate. A copper plating step of providing a copper plating layer in the entire surface of the resin substrate and the holes provided in the drilling step; and a connection electrode on the upper surface side of the resin substrate for connecting to a protruding electrode formed on a semiconductor chip. And a patterning step for forming pad electrodes for forming solder bumps on the lower surface side of the resin substrate, and a connection corresponding to a connection portion where a resist is disposed on the resin substrate and the projection electrode formed on the semiconductor chip is connected. In addition to the resist forming step to open the electrode and pad electrode part, the uneven part forming step to form unevenness on the surface of the other part, and gold plating on the patterned copper plating layer A primary plating step of performing primary plating, and gold plating step of forming a gold plating layer on the primer plating layer, and the opening of the electrode portion on the semiconductor chip, and,
A process of forming a resin film for protecting circuit elements in other portions, a bonding process of fixing a connection electrode of a wiring board and a projection electrode formed on a semiconductor chip with a conductive adhesive or solder, and A sealing step in which a sealing resin is poured between the chip and the wiring board and heat-cured in a heating furnace, and a solder ball is supplied to a pad electrode on the lower surface side of the wiring board and heated in a heating furnace to form a solder ball. And a bump process in which solder bumps are formed on the electrodes.

In the method of manufacturing a semiconductor device according to the present invention, a punching process for forming through holes for connecting the upper and lower surfaces of the resin substrate to the resin substrate having copper foils on the upper and lower surfaces. A copper plating step of providing a copper plating layer in the entire surface of the resin substrate and the holes provided in the drilling step; and a connection electrode on the upper surface side of the resin substrate for connecting to a protruding electrode formed on a semiconductor chip. And a patterning step for forming a pad electrode for forming a solder bump on the lower surface side of the resin substrate, and opening a connection electrode and a pad electrode portion corresponding to a connection portion with a protruding electrode formed on a semiconductor chip. A step of forming a resist for protecting the wiring, and a base plating step of performing a base plating for gold plating on the patterned copper plating layer,
A gold plating step of forming a gold plating layer on the base plating layer, a resin film forming step of arranging a resin film on a semiconductor chip and opening an electrode portion, and forming irregularities on the surface of other parts Process, a bonding step of fixing the connection electrodes of the wiring board and the protruding electrodes formed on the semiconductor chip with a conductive adhesive or solder, and pouring a sealing resin between the semiconductor chip and the wiring board, and curing by heating in a heating furnace. By supplying a solder ball to the pad electrode on the lower surface side of the wiring board and heating it in a heating furnace,
And a bump step in which solder balls are fixed on the pad electrodes and solder bumps are formed.

According to a twelfth aspect of the present invention, in a method of manufacturing a semiconductor device according to the present invention, a boring process for forming through holes for connecting upper and lower surfaces of a resin substrate to a resin substrate covered with copper foil on upper and lower surfaces. A copper plating step of providing a copper plating layer in the entire surface of the resin substrate and the holes provided in the drilling step; and a connection electrode on the upper surface side of the resin substrate for connecting to a protruding electrode formed on a semiconductor chip. And a patterning step for forming pad electrodes for forming solder bumps on the lower surface side of the resin substrate, and a connection corresponding to a connection portion where a resist is disposed on the resin substrate and the projection electrode formed on the semiconductor chip is connected. In addition to the resist forming step to open the electrode and pad electrode part, the uneven part forming step to form unevenness on the surface of the other part, and gold plating on the patterned copper plating layer A base plating step of performing base plating, a gold plating step of forming a gold plating layer on the base plating layer, a resin film forming step of arranging a resin film on a semiconductor chip and opening an electrode portion, and other portions A step of forming irregularities on the surface of the semiconductor chip, a bonding step of fixing the connection electrodes of the wiring board and the projecting electrodes formed on the semiconductor chip with a conductive adhesive or solder, and sealing between the semiconductor chip and the wiring board A sealing step of pouring resin and heating and curing in a heating furnace, and supplying solder balls to the pad electrodes on the lower surface side of the wiring board and heating in a heating furnace to fix the solder balls on the pad electrodes and form solder bumps And a bump process to be performed.

[Operation] In the present invention, the resist for protecting the wiring formed on the resin substrate and the resin film for protecting the circuit element on the semiconductor chip are smaller than the minimum opening diameter that can be opened by exposure and development. Irregularities are formed on the surface by exposure and development with the opening diameter.

Therefore, in the PBGA, the bonding area with the die bonding agent for fixing the semiconductor chip is increased, so that the adhesive strength is improved, and the die bonding agent for fixing the semiconductor chip and the wiring formed on the resin substrate are protected. Since the path of moisture entering from the interface with the resist becomes longer, defects such as peeling of a die bonding agent for fixing a semiconductor chip and popcorn phenomenon, which have conventionally occurred, can be prevented.

Also in the FCBGA, a sealing resin flowing between the semiconductor chip and the wiring board, a resin film for protecting circuit elements on the semiconductor chip and a resist for protecting wiring on the wiring board are used. Since the bonding area is increased, the bonding strength is improved, and the path of moisture entering from the interface between the sealing resin and the resin film for protecting the circuit elements on the semiconductor chip and the resist for protecting the wiring on the wiring board. Therefore, it is possible to prevent defects such as peeling of the sealing resin and popcorn phenomenon, which occur conventionally.

[0045]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings with reference to the accompanying drawings.

[0046]

FIG. 1 is a sectional view showing a PBGA according to a first embodiment of the present invention. As described in FIG.
A connection electrode 3 for wire bonding with the semiconductor chip 1 is provided on an upper surface side, a pad electrode 4 for providing a solder bump 6 is provided on a lower surface side, and a wiring 15 in a central portion of the resin substrate 2 is connected to the pad electrode 4. Thermal via holes 16 for dissipating heat generated by the semiconductor chip 1
A wiring board 18 having a through hole 14 for connecting the connection electrode 3 and the pad electrode 4, a resist 5 having an uneven surface on the surface for protecting the wiring 15, and a wiring board 1.
8, a semiconductor chip 1 fixed by a die bonding agent 7 on a central portion, a resin film 12 for protecting circuit elements on the semiconductor chip 1, electrodes of the semiconductor chip 1 and a wiring board 18.
Bonding wires 8 for connecting the connection electrodes 3
And a transfer mold 9 for sealing the semiconductor chip 1 and the bonding wires 8, and a solder bump 6 on the pad electrode 4 of the wiring board 18.

Next, a method of manufacturing the semiconductor device according to the first embodiment will be described. 2 to 5 are cross-sectional views illustrating the steps of manufacturing the semiconductor device according to the first embodiment.

As shown in FIG. 2, the resin substrate 2 is made of a glass epoxy resin having a rectangular shape and a thickness of about 0.2 mm, and a copper foil 17 having a thickness of about 18 μm is provided on both upper and lower surfaces thereof. The resin substrate 2 is provided with thermal via holes 16 for heat radiation between the plurality of through holes 14 and the semiconductor chip 1 by cutting drilling. After cleaning the substrate surface including the wall surfaces of the through hole 14 and the thermal via hole 16, an electroless copper plating layer is provided on the entire surface of the resin substrate 2. The copper plating layer is formed up to the inside of the through hole 14 and the thermal via hole 16.

Next, a photosensitive dry film is adhered to the upper and lower surfaces of the resin substrate 2 and exposed and developed to form an etching resist film. Thereafter, an etching solution is sprayed on the upper and lower surfaces of the resin substrate 2 to remove exposed copper without an etching resist film. After this etching, the remaining etching resist film is removed. As shown in FIG. 3, the connection electrodes 3 for wire bonding are formed on the upper surface of the resin substrate 2 and the solder bumps 6 are formed on the lower surface.
And a wiring 15 on both surfaces. The wiring 15 at the center of the resin substrate 2 and the pad electrode 4 are connected via a thermal via hole 14, and the connection electrode 3 corresponding to the opening of the resist and the pad electrode 4 are connected via a through hole 14.

Further, a resist is laminated on both surfaces of the resin substrate 2 and exposed and developed to provide a resist 5, and an opening of the resist 5 is provided in a portion corresponding to the connection electrode 3 and the pad electrode 4.

At this time, the connection electrodes 3 on the upper surface side of the resin substrate 2
By performing the exposure and development with the opening diameter smaller than the minimum opening diameter that can be opened by the exposure and development of the resist 5 in a portion other than the above, the portion with the opening diameter smaller than the minimum opening diameter that can be opened by the exposure and development is completely opened Instead, it is possible to form irregularities on the resist surface as shown in FIG.

Next, a nickel plating layer having a thickness of about 2 to 5 μm is provided on the surfaces of the copper plating layers of the exposed electrodes on the upper and lower surfaces of the resin substrate 2. Further, on the surface of the nickel plating layer, there is provided a flash gold plating layer having a thickness of about 0.05 μm, which contains impurities such as cobalt and is apt to bite the nickel plating layer. Although not shown, the above steps up to the copper plating layer, the nickel plating layer, and the flash gold plating layer are the base plating steps of providing the base plating layer.

Next, a thickness of 0.3 μm to 0.7 μm having excellent conductivity with the bonding wire is formed on the base plating layer.
An about m gold plating layer is provided. Although not shown, this step is a gold plating step for forming a gold plating layer. Thus, the wiring board 18 is completed.

Next, as shown in FIG. 5, a die bonding agent 7 is applied on the center portion on the upper surface side of the wiring board 18 formed by the method described above, and the semiconductor chip 1
, And dried until the die bonding agent 7 is cured, and the semiconductor chip 1 is fixed on the wiring board 18.
And the connection electrode 3 on the wiring board 18 are electrically connected by bonding wires 8. Then, the semiconductor chip 1
And the bonding wire 8 are sealed with a transfer mold 9.

At this time, the resin film 12 for protecting the circuit element is formed on the semiconductor chip 1 to be mounted as shown in FIG. 5, and the resin film 12 at the terminal portion connected by wire bonding is opened by exposure and development. Let me.

Next, a solder ball having a diameter of 0.6 mm to 0.8 mm is supplied to the pad electrode 4 on the lower surface side of the wiring board 18 and the solder bump 6 is provided by heating using a heating furnace. Thus, the semiconductor device of the present invention is completed.

(Embodiment 2) FIG. 6 is a sectional view showing a PBGA according to a second embodiment of the present invention. As shown in FIG. 6, a connection electrode 3 for wire bonding with the semiconductor chip 1 is provided on the upper surface side, a pad electrode 4 for providing solder bumps 6 on the lower surface side, and a central portion of the resin substrate 2 is further provided. Thermal via hole 1 for connecting wiring 15 and pad electrode 4 to dissipate heat of semiconductor chip 1
6, a through hole 14 for connecting the connection electrode 3 and the pad electrode 4, and a resist 5 for protecting the wiring 15
A semiconductor chip 1 fixed on a central portion of the wiring board 18 with a die bonding agent 7, a resin film 12 having an uneven surface for protecting circuit elements on the semiconductor chip 1, Electrodes of semiconductor chip 1 and wiring board 1
Bonding wires 8 for connecting the connection electrodes 3
And a transfer mold 9 for sealing the semiconductor chip 1 and the bonding wires 8, and a solder bump 6 on the pad electrode 4 of the wiring board 18.

Next, a method of manufacturing a semiconductor device according to the second embodiment will be described. 7 to 10 are cross-sectional views illustrating the steps of manufacturing the semiconductor device of the second embodiment.

As shown in FIG. 7, the resin substrate 2 is made of a glass epoxy resin having a rectangular shape and a thickness of about 0.2 mm, and a copper foil 17 having a thickness of about 18 μm is provided on both upper and lower surfaces thereof. The resin substrate 2 is provided with thermal via holes 16 for heat radiation between the plurality of through holes 14 and the semiconductor chip 1 by cutting drilling. After cleaning the substrate surface including the wall surfaces of the through hole 14 and the thermal via hole 16, an electroless copper plating layer is provided on the entire surface of the resin substrate 2. The copper plating layer is formed up to the inside of the through hole 14 and the thermal via hole 16.

Next, a photosensitive dry film is adhered to the upper and lower surfaces of the resin substrate 2 and exposed and developed to form an etching resist film. Thereafter, an etching solution is sprayed on the upper and lower surfaces of the resin substrate 2 to remove exposed copper without an etching resist film. After this etching, the remaining etching resist film is removed. As shown in FIG. 8, the connection electrodes 3 for wire bonding are formed on the upper surface of the resin substrate 2 and the solder bumps 6 are formed on the lower surface.
And a wiring 15 on both surfaces. The wiring 15 at the center of the resin substrate 2 and the pad electrode 4 are connected via a thermal via hole 14, and the connection electrode 3 corresponding to the opening of the resist and the pad electrode 4 are connected via a through hole 14.

Further, as shown in FIG.
The resist 5 is provided by laminating a resist on both sides of the substrate and performing exposure and development, and an opening of the resist 5 is provided in a portion corresponding to the connection electrode 3 and the pad electrode 4.

Next, a nickel plating layer having a thickness of about 2 to 5 μm is provided on the surfaces of the copper plating layers of the exposed electrodes on the upper and lower surfaces of the resin substrate 2. Further, on the surface of the nickel plating layer, there is provided a flash gold plating layer having a thickness of about 0.05 μm, which contains impurities such as cobalt and is apt to bite the nickel plating layer. Although not shown, the above steps up to the copper plating layer, the nickel plating layer, and the flash gold plating layer are the base plating steps of providing the base plating layer.

Next, a thickness of 0.3 μm to 0.7 μm having excellent conductivity with the bonding wire is formed on the base plating layer.
An about m gold plating layer is provided. Although not shown, this step is a gold plating step for forming a gold plating layer. Thus, the wiring board 18 is completed.

Next, as shown in FIG. 10, a die bonding agent 7 is applied on the central portion on the upper surface side of the wiring board 18 formed by the method described above, and the semiconductor chip 1 is placed thereon, The semiconductor chip 1 is fixed on the wiring board 18, and the electrodes of the semiconductor chip 1 are electrically connected to the connection electrodes 3 on the wiring board 18 by bonding wires 8. Thereafter, the semiconductor chip 1 and the bonding wires 8 are transferred to the transfer mold 9.
Seal with.

At this time, the semiconductor chip 1 to be mounted is
Resin film 12 for protecting circuit elements as described in
When the resin film 12 at the terminal portion connected by wire bonding is opened by exposure and development, portions other than the terminal where the projecting electrode 10 is formed with an opening diameter smaller than the minimum opening diameter that can be opened by exposure and development. The resin film 12 that protects the circuit elements of the semiconductor chip 1 is also formed by exposure and development.

Next, a solder ball having a diameter of 0.6 mm to 0.8 mm is supplied to the pad electrode 4 on the lower surface side of the wiring board 18, and the solder bump 6 is provided by heating using a heating furnace. Thus, the semiconductor device of the present invention is completed.

(Embodiment 3) FIG. 11 is a sectional view showing a PBGA according to a third embodiment of the present invention. As shown in FIG. 11, a connection electrode 3 for wire bonding to the semiconductor chip 1 is provided on the upper surface side, a pad electrode 4 for providing a solder bump 6 on the lower surface side, and a resin substrate 2 is further provided.
The thermal via hole 16 for connecting the wiring 15 in the central part of the semiconductor chip 1 and the pad electrode 4 to dissipate the heat of the semiconductor chip 1, the through hole 14 for connecting the connecting electrode 3 and the pad electrode 4, and protecting the wiring 15 Wiring board 18 provided with a resist 5 having an uneven surface on which the semiconductor chip 1 is mounted, a semiconductor chip 1 fixed on a central portion of the wiring board 18 with a die bonding agent 7, and a circuit element on the semiconductor chip 1 for protecting circuit elements. A resin film 12 having an uneven surface and a semiconductor chip 1
A bonding wire 8 for connecting the connection electrode 3 to the connection electrode 3 of the wiring board 18, a transfer mold 9 for sealing the semiconductor chip 1 and the bonding wire 8,
The structure has a solder bump 6 on the pad electrode 4 of the wiring board 18.

Next, a method of manufacturing a semiconductor device according to the third embodiment will be described. 12 to 15 are cross-sectional views illustrating the steps of manufacturing the semiconductor device of the third embodiment.

As shown in FIG. 12, the resin substrate 2 is made of a glass epoxy resin having a rectangular shape and a thickness of about 0.2 mm, and a copper foil 17 having a thickness of about 18 μm is provided on both upper and lower surfaces thereof. The resin substrate 2 is provided with thermal via holes 16 for heat radiation between the plurality of through holes 14 and the semiconductor chip 1 by cutting drilling. After cleaning the substrate surface including the wall surfaces of the through hole 14 and the thermal via hole 16, an electroless copper plating layer is provided on the entire surface of the resin substrate 2. The copper plating layer is formed up to the inside of the through hole 14 and the thermal via hole 16.

Next, a photosensitive dry film is stuck on both the upper and lower surfaces of the resin substrate 2 and exposed and developed to form an etching resist film. Thereafter, an etching solution is sprayed on the upper and lower surfaces of the resin substrate 2 to remove exposed copper without an etching resist film. After this etching, the remaining etching resist film is removed. As shown in FIG. 13, the connection electrodes 3 for wire bonding are provided on the upper surface of the resin substrate 2, the pad electrodes 4 for forming the solder bumps 6 on the lower surface, and the wirings 15 are provided on both surfaces. Can be The wiring 15 and the pad electrode 4 at the center of the resin substrate 2 are connected via the thermal via hole 14 and
The connection electrode 3 corresponding to the opening of the resist and the pad electrode 4 are connected via a through hole 14.

Further, a resist is laminated on both sides of the resin substrate 2 and exposed and developed to provide a resist 5, and an opening of the resist 5 is provided in a portion corresponding to the connection electrode 3 and the pad electrode 4.

At this time, the connection electrodes 3 on the upper surface side of the resin substrate 2
By performing the exposure and development with the opening diameter smaller than the minimum opening diameter that can be opened by the exposure and development of the resist 5 in a portion other than the above, the portion with the opening diameter smaller than the minimum opening diameter that can be opened by the exposure and development is completely opened. Instead, irregularities can be formed on the resist surface as shown in FIG.

Next, a nickel plating layer having a thickness of about 2 to 5 μm is provided on the surfaces of the copper plating layers of the exposed electrodes on the upper and lower surfaces of the resin substrate 2. Further, on the surface of the nickel plating layer, there is provided a flash gold plating layer having a thickness of about 0.05 μm, which contains impurities such as cobalt and is apt to bite the nickel plating layer. Although not shown, the above steps up to the copper plating layer, the nickel plating layer, and the flash gold plating layer are the base plating steps of providing the base plating layer.

Next, a thickness of 0.3 μm to 0.7 μm having excellent conductivity with the bonding wire is formed on the base plating layer.
An about m gold plating layer is provided. Although not shown, this step is a gold plating step for forming a gold plating layer. Thus, the wiring board 18 is completed.

Next, as shown in FIG. 15, a die bonding agent 7 is applied on the central portion on the upper surface side of the wiring board 18 formed by the method described above, and the semiconductor chip 1 is placed thereon, and the die bonding is performed. The semiconductor chip 1 is fixed on the wiring board 18, and the electrodes of the semiconductor chip 1 are electrically connected to the connection electrodes 3 on the wiring board 18 by bonding wires 8. Thereafter, the semiconductor chip 1 and the bonding wires 8 are transferred to the transfer mold 9.
Seal with.

At this time, the semiconductor chip 1 to be mounted is
Resin film 12 for protecting circuit elements as described in
When the resin film 12 at the terminal portion connected by wire bonding is opened by exposure and development, portions other than the terminal where the projecting electrode 10 is formed with an opening diameter smaller than the minimum opening diameter that can be opened by exposure and development. The resin film 12 that protects the circuit elements of the semiconductor chip 1 is also formed by exposure and development.

Next, a solder ball having a diameter of 0.6 mm to 0.8 mm is supplied to the pad electrode 4 on the lower surface side of the wiring board 18, and the solder bump 6 is provided by heating using a heating furnace. Thus, the semiconductor device of the present invention is completed.

(Embodiment 4) FIG. 16 is a sectional view showing an FCBGA according to a fourth embodiment of the present invention. As shown in FIG. 16, connection electrodes 3 for flip-chip mounting the semiconductor chip 1 are provided on the upper surface, and solder bumps 6 are provided on the lower surface.
And a through-hole 14 for connecting the connection electrode 3 and the pad electrode 4.
A wiring board 18 provided with a resist 5 having an uneven surface for protecting the wiring 15, a resin film 12 for protecting circuit elements on the semiconductor chip 1, and a semiconductor chip 1.
It has a protruding electrode 10 formed thereon, a connection material 13 such as a conductive adhesive or solder for connecting the connection electrode 13 and the protruding electrode 10, and a sealing resin 11 between the semiconductor chip 1 and the wiring board 18. In addition, the structure has a solder bump 6 on the pad electrode 4 of the wiring board 18.

Next, a method of manufacturing a semiconductor device according to the fourth embodiment will be described. 17 to 20 are cross-sectional views illustrating the steps of manufacturing the semiconductor device according to the fourth embodiment.

As shown in FIG. 17, the resin substrate 2 is made of a glass epoxy resin having a rectangular shape and a thickness of about 0.2 mm, and a copper foil 17 having a thickness of about 18 μm is provided on both upper and lower surfaces thereof. The resin substrate 2 is provided with a plurality of through holes 14 by cutting drilling. Through hole 1
After cleaning the substrate surface including the wall surface of No. 4, an electroless copper plating layer is provided on the entire surface of the resin substrate 2. The copper plating layer is formed even inside the through hole 14.

Next, a photosensitive dry film is stuck on both upper and lower surfaces of the resin substrate 2 and exposed and developed to form an etching resist film. Thereafter, an etching solution is sprayed on the upper and lower surfaces of the resin substrate 2 to remove exposed copper without an etching resist film. After this etching, the remaining etching resist film is removed. As shown in FIG. 18, the connection electrode 3 for flip-chip mounting the semiconductor chip 1 on the upper surface of the resin substrate 2 and the pad electrode 4 for forming the solder bump 6 on the lower surface as shown in FIG.
Then, the wiring 15 is provided on both surfaces. The connection electrode 3 corresponding to the opening of the resist and the pad electrode 4 are connected through a through hole 14.

Further, a resist is provided by laminating a resist on both surfaces of the resin substrate 2 and performing exposure and development.
A resist 5 is applied to a portion corresponding to the connection electrode 3 and the pad electrode 4.
Is provided.

At this time, the connection electrodes 3 on the upper surface side of the resin substrate 2
By performing the exposure and development with the opening diameter smaller than the minimum opening diameter that can open the resist 5 by the exposure and development in a place other than the above, the portion with the opening diameter smaller than the minimum opening diameter that can be opened by the exposure and development is completely opened. Instead, irregularities can be formed on the surface of the resist 5 as shown in FIG.

Next, a nickel plating layer having a thickness of about 2 to 5 μm is provided on the surfaces of the copper plating layers of the exposed electrodes on the upper and lower surfaces of the resin substrate 2. Further, on the surface of the nickel plating layer, there is provided a flash gold plating layer having a thickness of about 0.05 μm, which contains impurities such as cobalt and is apt to bite the nickel plating layer. Although not shown, the above steps up to the copper plating layer, the nickel plating layer, and the flash gold plating layer are the base plating steps of providing the base plating layer.

Next, a 0.3 μm thick
A gold plating layer of about m to 0.7 μm is provided. Although not shown, this step is a gold plating step for forming a gold plating layer. Thus, the wiring board 18 is completed.

Next, as shown in FIG. 20, the connection electrode 3 on the upper surface side of the wiring board 18 formed by the method described above and the protruding electrode 10 formed on the semiconductor chip 1 are soldered or conductive adhesive. Flip-chip mounting is performed using a connection material 13 such as the above. Thereafter, the sealing resin 11 is poured from the end of the semiconductor chip 1 and thermally cured, so that the semiconductor chip 1
To protect.

The semiconductor chip 1 to be flip-chip mounted is formed with a resin film 12 for protecting circuit elements, and an electrode portion for forming the bump electrode 10 is opened by exposure and development.
The protruding electrode 10 is formed of a metal such as solder, copper, or gold by a plating method, a stud bump method, or the like.

Next, solder balls having a diameter of 0.6 mm to 0.8 mm are supplied to the pad electrode 4 on the lower surface side of the wiring board 18 and heated by using a heating furnace, so that the solder bumps 6 are provided. Thus, the semiconductor device of the present invention is completed.

(Embodiment 5) FIG. 21 is a sectional view showing an FCBGA according to a fifth embodiment of the present invention. As shown in FIG. 21, connection electrodes 3 for flip-chip mounting the semiconductor chip 1 are provided on the upper surface side, and solder bumps 6 are provided on the lower surface side.
And a through-hole 14 for connecting the connection electrode 3 and the pad electrode 4.
A wiring board 18 having a resist 5 for protecting the wiring 15, a resin film 12 having an uneven surface for protecting circuit elements on the semiconductor chip 1, and a semiconductor chip 1.
The protruding electrode 10, the connection electrode 3, and the protruding electrode 1 formed thereon
A connection material 13 such as a conductive adhesive or solder for connecting the semiconductor chip 1 and a sealing resin 11 between the semiconductor chip 1 and the wiring board 18, and a solder bump 6 on the pad electrode 4 of the wiring board 18. It has a structure.

Next, a method of manufacturing a semiconductor device according to the fifth embodiment will be described. FIG. 22 to FIG. 27 are cross-sectional views showing the steps of manufacturing the semiconductor device in the fifth embodiment.

As shown in FIG. 22, the resin substrate 2 is made of a glass epoxy resin having a rectangular shape and a thickness of about 0.2 mm, and a copper foil 17 having a thickness of about 18 μm is provided on both upper and lower surfaces thereof. The resin substrate 2 is provided with a plurality of through holes 14 by cutting drilling. Through hole 1
After cleaning the substrate surface including the wall surface of No. 4, an electroless copper plating layer is provided on the entire surface of the resin substrate 2. The copper plating layer is formed even inside the through hole 14.

Next, a photosensitive dry film is adhered to the upper and lower surfaces of the resin substrate 2 and exposed and developed to form an etching resist film. Thereafter, an etching solution is sprayed on the upper and lower surfaces of the resin substrate 2 to remove exposed copper without an etching resist film. After this etching, the remaining etching resist film is removed. As shown in FIG. 23, the connection electrodes 3 for flip-chip mounting the semiconductor chip 1 on the upper surface of the resin substrate 2 and the pad electrodes 4 for forming the solder bumps 6 on the lower surface, as shown in FIG.
Then, the wiring 15 is provided on both surfaces. The connection electrode 3 corresponding to the opening of the resist and the pad electrode 4 are connected through a through hole 14.

Further, as shown in FIG.
The resist 5 is provided by laminating a resist 5 on both sides of the substrate and performing exposure and development.
The opening corresponding to the resist 5 is provided in the portion corresponding to.

Next, a nickel plating layer having a thickness of about 2 to 5 μm is provided on the surfaces of the copper plating layers of the exposed electrodes on the upper and lower surfaces of the resin substrate 2. Further, on the surface of the nickel plating layer, there is provided a flash gold plating layer having a thickness of about 0.05 μm, which contains impurities such as cobalt and is apt to bite the nickel plating layer. The above steps up to the copper plating layer, the nickel plating layer and the flash gold plating layer are the base plating steps for providing the base plating layer.

Next, a thickness of 0.3 μm to 0.7 μm having excellent conductivity with the bonding wire 8 is formed on the base plating layer.
A gold plating layer of about μm is provided. This step is a gold plating step for forming a gold plating layer. Thus, the wiring board 18 is completed.

Next, as shown in FIG. 27, the connection electrode 3 on the upper surface side of the wiring board 18 formed by the method described above and the protruding electrode 10 formed on the semiconductor chip 1 are soldered or conductive adhesive. Flip-chip mounting is performed using a connection material 13 such as the above. Thereafter, the sealing resin 11 is poured from the end of the semiconductor chip 1 and thermally cured, so that the semiconductor chip 1
To protect.

The semiconductor chip 1 to be flip-chip mounted has a resin film 12 for protecting circuit elements as shown in FIG. 25, and the resin film 12 at the terminal portion where the protruding electrode 10 is formed is exposed and developed. At the time of opening, portions other than the terminals for forming the protruding electrodes 10 with an opening diameter smaller than the smallest opening diameter that can be opened by exposure and development are exposed and developed to the resin film 12 which protects the circuit elements of the semiconductor chip 1. Irregularities are formed.

Thereafter, as shown in FIG. 26, the bump electrodes 10 formed on the semiconductor chip 1 are formed by plating a metal such as solder or copper or gold by a plating method, a stud bump method, or the like.

Next, a solder ball having a diameter of 0.6 mm to 0.8 mm is supplied to the pad electrode 4 on the lower surface side of the wiring board 18 and heated by using a heating furnace, whereby the solder bump 6 is provided. Thus, the semiconductor device of the present invention is completed.

(Embodiment 6) FIG. 28 is a sectional view showing an FCBGA according to a sixth embodiment of the present invention. As shown in FIG. 28, connection electrodes 3 for flip-chip mounting the semiconductor chip 1 are provided on the upper surface, and solder bumps 6 are provided on the lower surface.
And a through-hole 14 for connecting the connection electrode 3 and the pad electrode 4.
And a wiring board 18 provided with a resist 5 having an uneven surface on the surface for protecting the wiring 15, the connection electrodes 3 formed on the wiring board 18, and a surface for protecting circuit elements on the semiconductor chip 1. A bumpy resin film 12, a bump electrode 10 formed on the semiconductor chip 1, a connection material 13 such as a conductive adhesive or solder for connecting the connection electrode 3 and the bump electrode 10, a semiconductor chip 1 and a wiring board 18 and a sealing resin 11, and has a structure in which solder bumps 6 are formed on the pad electrodes 4 of the wiring board 18.

Next, a method of manufacturing a semiconductor device according to the sixth embodiment will be described. FIGS. 29 to 34 are cross-sectional views showing the steps of manufacturing the semiconductor device according to the sixth embodiment.

As shown in FIG. 29, the resin substrate 2 is made of a glass epoxy resin having a rectangular shape and a thickness of about 0.2 mm, and a copper foil 17 having a thickness of about 18 μm is provided on both upper and lower surfaces thereof. The resin substrate 2 is provided with a plurality of through holes 14 by cutting drilling. Through hole 1
After cleaning the substrate surface including the wall surface of No. 4, an electroless copper plating layer is provided on the entire surface of the resin substrate 2. The copper plating layer is formed even inside the through hole 14.

Next, a photosensitive dry film is adhered to the upper and lower surfaces of the resin substrate 2 and exposed and developed to form an etching resist film. After that, the etching liquid is applied to the resin substrate 2
To remove the exposed copper without the etching resist film. After this etching, the remaining etching resist film is removed. As shown in FIG. 30, the connection electrodes 3 for flip-chip mounting the semiconductor chip 1 on the upper surface of the resin substrate 2 and the pad electrodes 4 for forming the solder bumps 6 on the lower surface, as shown in FIG.
Then, the wiring 15 is provided on both surfaces. The connection electrode 3 corresponding to the opening of the resist and the pad electrode 4 are connected through a through hole 14.

Further, a resist 5 is laminated on both surfaces of the resin substrate 2 and exposed and developed to provide the resist 5, and an opening of the resist 5 is provided in a portion corresponding to the connection electrode 3 and the pad electrode 4.

At this time, the connection electrodes 3 on the upper surface side of the resin substrate 2
By performing the exposure and development with the opening diameter smaller than the minimum opening diameter that can be opened by the exposure and development of the resist 5 in a portion other than the above, the portion with the opening diameter smaller than the minimum opening diameter that can be opened by the exposure and development is completely opened. Instead, irregularities can be formed on the surface of the resist 5 as shown in FIG.

Next, a nickel plating layer having a thickness of about 2 to 5 μm is provided on the exposed surfaces of the copper plating layers on the upper and lower surfaces of the resin substrate 2. Further, on the surface of the nickel plating layer, there is provided a flash gold plating layer having a thickness of about 0.05 μm, which contains impurities such as cobalt and is apt to bite the nickel plating layer. The above steps up to the copper plating layer, the nickel plating layer and the flash gold plating layer are the base plating steps for providing the base plating layer.

Next, a thickness of 0.3 μm to 0.7 μm having excellent conductivity with the bonding wire 8 is formed on the base plating layer.
A gold plating layer of about μm is provided. This step is a gold plating step for forming a gold plating layer. Thus, the wiring board 18 is completed.

Next, as shown in FIG. 34, the connection electrodes 3 on the upper surface side of the wiring board 18 formed by the method described above and the protruding electrodes 10 formed on the semiconductor chip 1 are soldered or conductive adhesive. Flip-chip mounting is performed using a connection material 13 such as the above. Thereafter, the sealing resin 11 is poured from the end of the semiconductor chip 1 and thermally cured, so that the semiconductor chip 1
To protect.

As shown in FIG. 32, the semiconductor chip 1 to be flip-chip mounted has a resin film 12 for protecting circuit elements formed thereon. The resin film 12 protecting the circuit elements of the semiconductor chip 1 by exposing and developing portions other than the terminals forming the protruding electrodes 10 with an opening diameter smaller than the minimum opening diameter that can be opened by exposure and development. The surface has irregularities.

At this time, as shown in FIG. 33, the bump electrodes 10 formed on the semiconductor chip 1 are formed of a metal such as solder, copper or gold by a plating method or a stud bump method.

Next, solder balls having a diameter of 0.6 mm to 0.8 mm are supplied to the pad electrode 4 on the lower surface side of the wiring board 18 and heated by using a heating furnace, so that the solder bumps 6 are provided. Thus, the semiconductor device of the present invention is completed.

[0112]

As is apparent from the above description, in the semiconductor device and the manufacturing method according to the present invention, a resist for protecting wiring formed on a wiring board or a resin for protecting circuit elements on a semiconductor chip is provided. Irregularities are formed on the surface by exposing and developing the film with an opening diameter smaller than the minimum opening diameter that can be opened by exposure and development.

Accordingly, in the PBGA, the bonding area with the die bonding agent for fixing the semiconductor chip is increased, so that the adhesive force is improved, and the die bonding agent for fixing the semiconductor chip and the wiring formed on the wiring board are protected. Therefore, the path of the moisture entering from the interface with the resist becomes longer, so that defects such as peeling of the die bonding agent for fixing the transfer mold or the semiconductor chip and popcorn phenomenon, which occur conventionally, can be prevented.

Also in the FCBGA, the sealing resin flowing between the semiconductor chip and the wiring board, the resin film for protecting the circuit elements on the semiconductor chip, and the resist for protecting the wiring on the wiring board are different. Since the bonding area is increased, the bonding strength is improved, and the path of moisture entering from the interface between the sealing resin and the resin film for protecting the circuit elements on the semiconductor chip and the resist for protecting the wiring on the wiring board. Therefore, it is possible to prevent defects such as peeling of the sealing resin and popcorn phenomenon, which occur conventionally.

That is, the peeling of the die bonding agent fixing the semiconductor chip or the sealing resin protecting the semiconductor chip due to the intrusion of moisture, which has occurred conventionally, can be performed without changing the manufacturing process of the conventional PBGA or FCBGA. And a defect such as a popcorn phenomenon can be prevented, and a highly reliable semiconductor package can be obtained.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a sectional view illustrating a manufacturing method for forming a semiconductor device according to the first embodiment of the present invention.

FIG. 3 is a sectional view illustrating a manufacturing method for forming a semiconductor device according to the first embodiment of the present invention.

FIG. 4 is a cross-sectional view illustrating a manufacturing method for forming a semiconductor device according to the first embodiment of the present invention.

FIG. 5 is a sectional view showing a manufacturing method for forming a semiconductor device according to the first embodiment of the present invention.

FIG. 6 is a sectional view showing a semiconductor device according to a second embodiment of the present invention.

FIG. 7 is a cross-sectional view illustrating a manufacturing method for forming a semiconductor device according to a second embodiment of the present invention.

FIG. 8 is a cross-sectional view illustrating a manufacturing method for forming a semiconductor device according to a second embodiment of the present invention.

FIG. 9 is a sectional view illustrating a manufacturing method for forming a semiconductor device according to a second embodiment of the present invention.

FIG. 10 is a cross-sectional view illustrating a manufacturing method for forming a semiconductor device according to a second embodiment of the present invention.

FIG. 11 is a sectional view showing a semiconductor device according to a third embodiment of the present invention.

FIG. 12 is a cross-sectional view illustrating a manufacturing method for forming a semiconductor device according to a third embodiment of the present invention.

FIG. 13 is a sectional view illustrating a manufacturing method for forming a semiconductor device according to a third embodiment of the present invention.

FIG. 14 is a sectional view illustrating a manufacturing method for forming a semiconductor device according to a third embodiment of the present invention.

FIG. 15 is a sectional view showing a manufacturing method for forming a semiconductor device according to a third embodiment of the present invention.

FIG. 16 is a sectional view showing a semiconductor device according to a fourth embodiment of the present invention.

FIG. 17 is a sectional view illustrating a manufacturing method for forming a semiconductor device according to a fourth embodiment of the present invention.

FIG. 18 is a sectional view illustrating a manufacturing method for forming a semiconductor device according to a fourth embodiment of the present invention.

FIG. 19 is a sectional view showing a manufacturing method for forming a semiconductor device according to a fourth embodiment of the present invention.

FIG. 20 is a sectional view illustrating a manufacturing method for forming a semiconductor device according to a fourth embodiment of the present invention.

FIG. 21 is a sectional view showing a semiconductor device according to a fifth embodiment of the present invention.

FIG. 22 is a sectional view showing a manufacturing method for forming a semiconductor device according to a fifth embodiment of the present invention.

FIG. 23 is a sectional view showing a manufacturing method for forming a semiconductor device according to a fifth embodiment of the present invention.

FIG. 24 is a sectional view illustrating a manufacturing method for forming a semiconductor device according to a fifth embodiment of the present invention.

FIG. 25 is a sectional view illustrating a manufacturing method for forming a semiconductor device according to a fifth embodiment of the present invention.

FIG. 26 is a sectional view illustrating a manufacturing method for forming a semiconductor device according to a fifth embodiment of the present invention.

FIG. 27 is a sectional view illustrating a manufacturing method for forming a semiconductor device according to a fifth embodiment of the present invention.

FIG. 28 is a sectional view showing a semiconductor device according to a sixth embodiment of the present invention.

FIG. 29 is a cross-sectional view illustrating a manufacturing method for forming a semiconductor device according to a sixth embodiment of the present invention.

FIG. 30 is a sectional view illustrating a manufacturing method for forming a semiconductor device according to a sixth embodiment of the present invention.

FIG. 31 is a sectional view illustrating a manufacturing method for forming a semiconductor device according to a sixth embodiment of the present invention.

FIG. 32 is a sectional view illustrating a manufacturing method for forming a semiconductor device according to a sixth embodiment of the present invention.

FIG. 33 is a sectional view illustrating a manufacturing method for forming a semiconductor device according to a sixth embodiment of the present invention.

FIG. 34 is a cross-sectional view illustrating a manufacturing method for forming a semiconductor device according to a sixth embodiment of the present invention.

FIG. 35 is a cross-sectional view showing a conventional semiconductor device.

FIG. 36 is a cross-sectional view showing a manufacturing method for forming a conventional semiconductor device.

FIG. 37 is a cross-sectional view showing a manufacturing method for forming a conventional semiconductor device.

FIG. 38 is a cross-sectional view showing a manufacturing method for forming a conventional semiconductor device.

FIG. 39 is a cross-sectional view showing a manufacturing method for forming a conventional semiconductor device.

FIG. 40 is a sectional view showing a conventional semiconductor device.

FIG. 41 is a cross-sectional view showing a manufacturing method for forming a conventional semiconductor device.

FIG. 42 is a cross-sectional view showing a manufacturing method for forming a conventional semiconductor device.

FIG. 43 is a cross-sectional view showing a manufacturing method for forming a conventional semiconductor device.

FIG. 44 is a cross-sectional view showing a manufacturing method for forming a conventional semiconductor device.

[Explanation of symbols]

 Reference Signs List 1 semiconductor chip 2 resin substrate 3 connection electrode 4 pad electrode 5 resist 6 solder bump 7 die bonding agent 8 bonding wire 9 transfer mold 10 protruding electrode 11 sealing resin 12 resin film 13 connection material 14 through hole 15 wiring 16 thermal via hole 17 copper foil 18 Wiring board

Claims (12)

[Claims] 1. A connection electrode for wire bonding with a semiconductor chip is provided on an upper surface side, a pad electrode for providing a solder bump is provided on a lower surface side, and a wiring in a central portion of a resin substrate is connected to the pad electrode. A thermal via hole for dissipating heat generated by the semiconductor chip, a through hole for connecting the connection electrode and the pad electrode,
A wiring board provided with a resist having irregularities on the surface for protecting the wiring, a semiconductor chip fixed by a die bonding agent on a central portion of the wiring board, and a resin film for protecting circuit elements on the semiconductor chip; A bonding wire for connecting the electrode of the semiconductor chip to the connection electrode of the wiring board, a transfer mold for sealing the semiconductor chip and the bonding wire, and a solder bump on the pad electrode of the wiring board. Characteristic semiconductor device. 2. A connection electrode for wire bonding with a semiconductor chip is provided on an upper surface side, a pad electrode for providing a solder bump is provided on a lower surface side, and a wiring at a central portion of a resin substrate is connected to the pad electrode. A thermal via hole for dissipating heat generated by the semiconductor chip, a through hole for connecting the connection electrode and the pad electrode,
A wiring board including a resist for protecting the wiring,
A semiconductor chip fixed with a die bonding agent on the central part of a wiring board, a resin film with an uneven surface to protect circuit elements on the semiconductor chip, and an electrode of the semiconductor chip connected to a connection electrode of the wiring board And a transfer mold for sealing the semiconductor chip and the bonding wire, and a solder bump on a pad electrode of the wiring board. 3. A connection electrode for wire bonding with a semiconductor chip is provided on an upper surface side, a pad electrode for providing a solder bump is provided on a lower surface side, and a wiring at a central portion of the resin substrate is connected to the pad electrode. A thermal via hole for dissipating heat generated by the semiconductor chip, a through hole for connecting the connection electrode and the pad electrode,
A wiring board provided with a resist having unevenness on the surface for protecting the wiring, a semiconductor chip fixed on a central portion of the wiring board with a die bonding agent, and an unevenness on the surface for protecting circuit elements on the semiconductor chip; Resin film, a bonding wire for connecting the electrode of the semiconductor chip to the connection electrode of the wiring board, a transfer mold for sealing the semiconductor chip and the bonding wire, and a solder bump on the pad electrode of the wiring board. And a semiconductor device comprising: 4. A connection electrode for flip-chip mounting a semiconductor chip on an upper surface side, a pad electrode for providing a solder bump on a lower surface side, and a through hole for connecting the connection electrode to the pad electrode. A wiring board provided with a resist having unevenness on the surface for protecting the wiring, a connection electrode formed on the wiring board, a resin film for protecting circuit elements on the semiconductor chip, and a wiring board formed on the semiconductor chip And a connection material such as a conductive adhesive or solder for connecting the connection electrode and the projection electrode, and a sealing resin between the semiconductor chip and the wiring board. A semiconductor device having solder bumps. 5. A connection electrode for flip-chip mounting a semiconductor chip on an upper surface side, a pad electrode for providing solder bumps on a lower surface side, and a through hole for connecting the connection electrode to the pad electrode. A wiring board provided with a resist for protecting the wiring, a connection electrode formed on the wiring board, a resin film having an uneven surface for protecting circuit elements on the semiconductor chip, and formed on the semiconductor chip And a connection material such as a conductive adhesive or solder for connecting the connection electrode and the projection electrode,
A semiconductor device having a sealing resin between a semiconductor chip and a wiring board, and having a solder bump on a pad electrode of the wiring board. 6. A connection electrode for flip-chip mounting a semiconductor chip on an upper surface side, a pad electrode for providing a solder bump on a lower surface side, and a through hole for connecting the connection electrode to the pad electrode. And a wiring board comprising a resist having unevenness on the surface for protecting the wiring, a connection electrode formed on the wiring board, and a resin film having unevenness on the surface for protecting circuit elements on the semiconductor chip. Having a projection electrode formed on the semiconductor chip, a connection material such as a conductive adhesive or solder for connecting the connection electrode and the projection electrode, and a sealing resin between the semiconductor chip and the wiring board; A semiconductor device having a solder bump on a pad electrode of a wiring board. 7. A drilling process for forming a thermal via hole for a heat dissipation through hole of a semiconductor chip and a through hole for connecting the upper and lower surfaces of the resin substrate to a resin substrate having copper foils on upper and lower surfaces, A copper plating step of providing a copper plating layer in the entire surface of the resin substrate and in the holes provided in the drilling process; a connection electrode connected to a semiconductor chip electrode and a bonding wire on an upper surface side of the resin substrate; A patterning process for forming pad electrodes for forming solder bumps on the lower surface of the substrate, and a resist forming process for arranging a resist on the resin substrate and forming resist openings on the connection electrodes and the pad electrodes , An irregularity forming step of forming irregularities on the surface of the other part, and a base plating step of performing a base plating for gold plating on the patterned copper plating layer And a gold plating step of forming a gold plating layer on the base plating layer, a resin film forming step of arranging a resin film on the semiconductor chip and opening an electrode portion, and a die bonding agent on the semiconductor chip at the center of the wiring board. A die bonding step of fixing, a wire bonding step of connecting a fixed electrode of the semiconductor chip and a connection electrode of the wiring board with a bonding wire, a semiconductor chip fixed on the wiring board, and a connection between the semiconductor chip and the wiring board. The transfer molding step of sealing the bonding wires connecting the electrodes with resin, and supplying the solder balls to the pad electrodes on the lower surface side of the wiring board and heating them in a heating furnace, so that the solder balls are fixed on the pad electrodes, and the solder bumps are formed. And a bump process for forming a semiconductor device. 8. A drilling process for forming a thermal via hole for a heat dissipation through hole of a semiconductor chip and a through hole for connecting the upper and lower surfaces of the resin substrate to a resin substrate having copper foils on upper and lower surfaces, A copper plating step of providing a copper plating layer in the entire surface of the resin substrate and in the holes provided in the drilling process; a connection electrode connected to a semiconductor chip electrode and a bonding wire on an upper surface side of the resin substrate; A patterning step for forming a pad electrode for forming solder bumps on the lower surface side of the substrate, a resist forming step of arranging a resist on a resin substrate and forming a resist opening on the connection electrode and the pad electrode; A base plating step of performing a base plating for gold plating on the patterned copper plating layer, and a gold plating step of forming a gold plating layer on the base plating layer. A resin film forming step of arranging a resin film on a semiconductor chip and opening an electrode portion, and an unevenness forming step of forming unevenness on the surface of the other portion, and die bonding the semiconductor chip to a central portion of the wiring board A die bonding step of fixing with an agent, a wire bonding step of connecting the fixed electrode of the semiconductor chip and the connection electrode of the wiring board with a bonding wire, a semiconductor chip fixed on the wiring board, and the semiconductor chip and the wiring board. The transfer molding step of sealing the bonding wires connecting the connection electrodes with resin, and supplying the solder balls to the pad electrodes on the lower surface side of the wiring board and heating them in a heating furnace, whereby the solder balls are fixed on the pad electrodes. And a bump process for forming solder bumps. 9. A drilling process for forming a thermal via hole for a heat dissipation through hole of a semiconductor chip and a through hole for connecting the upper and lower surfaces of the resin substrate to a resin substrate having copper foils on upper and lower surfaces, A copper plating step of providing a copper plating layer in the entire surface of the resin substrate and in the holes provided in the drilling process; a connection electrode connected to a semiconductor chip electrode and a bonding wire on an upper surface side of the resin substrate; A patterning process for forming pad electrodes for forming solder bumps on the lower surface of the substrate, and a resist forming process for arranging a resist on the resin substrate and forming resist openings on the connection electrodes and the pad electrodes , An irregularity forming step of forming irregularities on the surface of the other part, and a base plating step of performing a base plating for gold plating on the patterned copper plating layer And a gold plating step of forming a gold plating layer on the base plating layer, a resin film forming step of arranging a resin film on a semiconductor chip and opening an electrode part, and forming irregularities on the surface of other parts Forming a concavo-convex pattern, a die bonding step of fixing a semiconductor chip to a central portion of a wiring board with a die bonding agent, a wire bonding step of connecting electrodes of the fixed semiconductor chip and connection electrodes of the wiring board with bonding wires, A transfer molding step of sealing the semiconductor chip fixed thereon and a bonding wire connecting the semiconductor chip and the connection electrode on the wiring board with a resin, and supplying solder balls to the pad electrode on the lower surface side of the wiring board and heating. By heating in a furnace, the solder ball is fixed on the pad electrode, and a solder bump is formed. The method of manufacturing a semiconductor device according to claim and. 10. A process for forming a through hole for connecting the upper and lower surfaces of a resin substrate to a resin substrate having copper foils on upper and lower surfaces, and a process for forming a hole in the entire surface of the resin substrate. A copper plating step of providing a copper plating layer in the hole, a connection electrode for connecting to a protruding electrode formed on the semiconductor chip on the upper surface side of the resin substrate, and a solder bump on the lower surface side of the resin substrate. A patterning step for forming a pad electrode for, and a resist forming step of arranging a resist on a resin substrate and opening a connection electrode and a pad electrode part corresponding to a connection part with a protruding electrode formed on a semiconductor chip, A step of forming irregularities on the surface of the other part, a step of plating an underlayer for gold plating on the patterned copper plating layer, and a step of forming the underlayer A gold plating step of forming a gold plating layer on the plating layer, and opening an electrode portion on the semiconductor chip,
A step of forming a resin film for protecting circuit elements in other portions, and a bonding step of fixing a connection electrode of a wiring board and a projection electrode formed on a semiconductor chip with a conductive adhesive or solder. By pouring the sealing resin between the semiconductor chip and the wiring board and heating and curing in a heating furnace, and supplying solder balls to the pad electrodes on the lower surface side of the wiring board, and heating in a heating furnace, A method of manufacturing a semiconductor device, comprising: a step of fixing a solder ball on a pad electrode to form a solder bump. 11. A process for forming a through hole for connecting the upper and lower surfaces of a resin substrate to a resin substrate having copper foils on upper and lower surfaces, and a process for forming a hole in the entire surface of the resin substrate. A copper plating step of providing a copper plating layer in the hole, a connection electrode for connecting to a protruding electrode formed on the semiconductor chip on the upper surface side of the resin substrate, and a solder bump on the lower surface side of the resin substrate. Patterning process for forming a pad electrode for forming a resist for opening a connection electrode and a pad electrode portion corresponding to a connection portion with a protruding electrode formed on a semiconductor chip and forming a resist for protecting a wiring Process, an underplating process for performing an undercoat for gold plating on a patterned copper plating layer, and gold plating for forming a gold plating layer on the underplating layer A resin film forming step of arranging a resin film on the semiconductor chip and opening an electrode portion, and
A step of forming irregularities on the surface of the other part, a bonding step of fixing the connection electrodes of the wiring board and the protruding electrodes formed on the semiconductor chip with a conductive adhesive or solder, etc .; A sealing step of pouring the sealing resin between and heating and curing in a heating furnace;
Supply solder balls to the pad electrodes on the lower side of the wiring board,
A method of manufacturing a semiconductor device, comprising: a step of forming a solder bump by heating a heating furnace to fix a solder ball on a pad electrode. 12. A process for forming a through hole for connecting the upper and lower surfaces of a resin substrate to a resin substrate having copper foils on the upper and lower surfaces, and a process for forming a hole in the entire surface of the resin substrate. A copper plating step of providing a copper plating layer in the hole, a connection electrode for connecting to a protruding electrode formed on the semiconductor chip on the upper surface side of the resin substrate, and a solder bump on the lower surface side of the resin substrate. A patterning step for forming a pad electrode for, and a resist forming step of arranging a resist on a resin substrate and opening a connection electrode and a pad electrode part corresponding to a connection part with a protruding electrode formed on a semiconductor chip, A step of forming irregularities on the surface of the other part, a step of plating an underlayer for gold plating on the patterned copper plating layer, and a step of forming the underlayer A gold plating step of forming a gold plating layer on a plating layer, a resin film forming step of setting a resin film on a semiconductor chip and opening an electrode part, and a concavo-convex forming step of forming concavities and convexities on the surface of other parts And a bonding step of fixing the connection electrodes of the wiring board and the protruding electrodes formed on the semiconductor chip with a conductive adhesive or solder, and pouring a sealing resin between the semiconductor chip and the wiring board, and heating in a heating furnace. A sealing step of curing and a bump step of supplying solder balls to the pad electrodes on the lower surface side of the wiring board and heating the same in a heating furnace so that the solder balls are fixed on the pad electrodes and solder bumps are formed. A method for manufacturing a semiconductor device, comprising: