JPH11261395A - Output buffer - Google Patents

Abstract

(57) Abstract: An output buffer capable of continuously changing an output current by an input voltage of a control terminal is provided. A transistor of an output buffer is connected in series, a signal to be output is input to one gate, and an analog signal for controlling an output current is input to the other gate. By changing the voltage level of the analog signal, the output current can be changed continuously. [Effect] The value of the output current can be continuously changed by the voltage level applied to the control input terminal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CMOS semiconductor integrated circuit, and more particularly to an output buffer capable of changing an output current.

[0002]

2. Description of the Related Art Conventionally, an output buffer of a CMOS semiconductor integrated circuit generally has a fixed output current value.
A circuit as disclosed in, for example, Patent Publication No. S62828817 is known so that the output current of the output buffer can be changed for a special use.

FIG. 4 shows a conventional circuit example. In FIG. 4, 1 is a power supply terminal, 2 is a ground (hereinafter abbreviated as GND), 11 is a data input terminal, 14 is an output terminal, 15
Is a control input terminal for changing the output current, and 61 is a CMO
S, an inverter circuit 48 to 50 is an enhancement P-channel MOS transistor (hereinafter referred to as P
ch-Tr), 28 to 30 are enhancement N-channel MOS transistors (hereinafter referred to as Nch-Tr).
Abbreviated).

The input of the inverter 61 is connected to the input terminal 15, and the Pch-Trs 48 and 49 are connected in series.
The source of 9 is connected to the power supply, and the drain of 48 is connected to the output terminal 14. Nch-Trs 28 and 29 are also connected in series, the source of 28 is connected to GND, and 29
Are connected to the output terminal 14. Pch-
Tr 50 has a source connected to the power supply and a drain connected to the output terminal 14, a drain of the Nch-Tr 30 connected to the output terminal 14, and a source connected to GND.

The gates of the Pch-Trs 48 and 50 and the Nch
The gates of -Tr 29 and 30 are connected to the input terminal 11;
The gate of the Phc-Tr 49 is connected to the output of the inverter 61, and the gate of the Nch-Tr 28 is directly connected to the input terminal 15.

When a low level is applied to the input terminal 15, the Pch-Tr 49 and the Nch-Tr 28 are turned off.
Therefore, even when a high level and a low level are applied to the input terminal 11, the transistor Pch-T that actually switches
r is only 50 and Nch-Tr is 30 and the output current is small. On the other hand, when a high level is applied to the input terminal 15, the Pch-Tr 49 and the Nch-Tr 28 are turned on, and the Pch-Trs 48 and 49 are turned on by the input signal of the input terminal 11.
And the series transistors of Nch-Trs 28 and 29 are added as output currents, and the output current increases.

[0007]

In the example shown in FIG. 4, only one transistor and one input terminal are used to control the output current. However, the output current can be more finely controlled by providing a plurality of transistors and input terminals. However, since the output current is controlled by turning on / off the transistor, there is a disadvantage that the number of transistors to be used becomes extremely large if the output current is to be finely controlled. Also, no matter how many transistors are added, it is impossible to continuously change the output current.

The problem to be solved by the present invention is to reduce the number of transistors used and to make it possible to continuously change the output current.

[0009]

According to the present invention, an output buffer transistor is connected in series, a signal to be output is input to one gate, and an analog signal for controlling an output current to the other gate. Input the signal. By changing the voltage level of the analog signal, the output current can be changed continuously.

[0010]

FIG. 1 shows an embodiment of the present invention. In FIG. 1, 1 is a power supply, 2 is GND, 11 is an input terminal, 1
2 and 13 are control input terminals for controlling output current, 1
4 is an output terminal. 21 to 23 are Nch-Trs,
41 to 43 are Pch-Tr. Nch-Tr21
And 22 are connected in series and inserted between GND and the output terminal 14. The Pch-Trs 41 and 42 are connected in series and inserted between the power supply and the output terminal 14. The drains of the Nch-Tr 23 and the Pch-Tr 43 are commonly connected to the output terminal 14, the source of 23 is connected to GND, and the source of 43 is connected to the power supply. The input terminal 11 is connected to the gates of the transistors 22, 23, 42, 43, the input terminal 12 is connected to the gate of the transistor 41, and the input terminal 13 is connected to the gate of the transistor 21.

When the same potential as the power supply is applied to the input terminal 12 and the same potential as GND is applied to the input terminal 13,
The ch-Tr 41 and the Nch-Tr 21 are completely turned off. Therefore, even if a signal is input to the input terminal 11, only the transistors 23 and 43 contribute to the output, that is, become effective as an output current. This state is where the output current is the smallest.

Next, when the same potential as GND is applied to the input terminal 12 and the same potential as the power supply is applied to the input terminal 13, Pc
h-Tr41 and Nch-Tr21 are completely turned on.

At this time, when a low level is applied to the input terminal 11, the output becomes "H" and the high level output current I
OH is the sum of the output current of the transistor 43 and the output current of the transistors 41 and 42 connected in series, and the output current is maximized.

When a high level is applied to the input terminal 11, the output becomes "L" and the low level output current IO
L is the sum of the output current of the transistor 23 and the output current of the transistors 21 and 22 connected in series, and the output current also becomes the maximum.

Next, the case where an intermediate potential is applied to the control input terminals 12 and 13 will be considered. When the power supply voltage is 3 V and 1.5 V is applied to the input terminal 12, the Pch-Tr 41 is turned on but is not completely ON. The equivalent resistance value is obtained when the same potential as GND is applied to the input terminal 12. Be larger. Therefore, the high-level output current is smaller than the above-described maximum current.

Similarly, when 1.5 V is applied to the input terminal 13, the Nch-Tr 21 does not turn on completely, so that the low-level output current becomes smaller than the above-mentioned maximum current.

As described above, in the present invention, the output current can be changed steplessly by applying an arbitrary voltage to the input terminal of the output current control.

FIG. 2 shows another embodiment of the present invention. In FIG. 2, 1 is a power supply, 2 is GND, 11 is an input terminal, 12 and 13 are control input terminals for controlling output current, and 14 is an output terminal. 24 and 25 are Nch-Tr, 44,
45 is a Pch-Tr. The Nch-Trs 24 and 25 are connected in series and inserted between GND and the output terminal 14. The Pch-Trs 44 and 45 are connected in series and inserted between the power supply and the output terminal 14. Input terminal 11
Is connected to the gates of the transistors 24 and 44, the input terminal 12 is connected to the gate of the transistor 45, and the input terminal 13 is connected to the gate of the transistor 25.

The difference between the example of FIG. 2 is that a transistor for controlling the output current is provided on the output terminal side and that the transistors (23 and 43 in FIG. 1) that determine the minimum output current are not provided. In the circuit of FIG. 2, when the same voltage as the power supply voltage is applied to the input terminal 12 which controls the high-level output current, the Pch-Tr 45 is completely turned off, so that the high-level output current also becomes completely zero. G to input terminal 12
When the same potential as ND is applied, the Pch-Tr 45 is completely turned on and the high level output current is maximized.

Similarly, when the same potential as GND is applied to the input terminal 13, the Nc-Tr is completely turned off, and the low level output current becomes completely zero. When the same potential as the power supply voltage is applied to the input terminal 13, the Nch-Tr 25 is completely turned on and the low-level output current is maximized.

The example of FIG. 2 has an advantage that the output current can be changed from 0 to the maximum output as compared with the circuit example of FIG.
In addition, since the transistor controlling the output current is provided on the output terminal side, there is an advantage that the parasitic capacitance of the output terminal when the main current is 0 is small.

FIG. 3 shows another embodiment of the present invention. In FIG. 3, 1 is a power supply, 2 is GND, 11 is an input terminal, 12
And 13 are control input terminals for controlling the output current, 14
Is an output terminal. 26 and 27 are Nch-Tr, and 46
And 47 are Pch-Tr. The Nch-Tr 26 has a source connected to GND, a drain connected to the drain of the Pch-Tr 46, a source of the Nch-Tr 27 and a source of the Pch-Tr 47, and a source of the Pch-Tr 46 connected to a power supply. Pch-Tr47 drain and Nc
The drain of the h-Tr 27 is connected in common and the output terminal 14
Is connected to The input terminal 11 is connected to the gates of the transistors 26 and 46, and the input terminal 12 is a Pch-Tr
The input terminal 13 is connected to the gate of the Nch-Tr 27.

In the circuit of FIG. 3, Nch-Tr 27 and Pch
The point that the value of the output current is controlled by the transmission gate constituted by -Tr47 is significantly different from the circuits of FIGS. Since a transmission gate is used, Pch-Tr46 and Nc
The output current of the inverter output constituted by the h-Tr 26 is controlled by controlling the resistance value of the transmission gate. Since the transmission gate is composed of the Pch-Tr 47 and the Nch-Tr 27, the combined resistance of these two transistors becomes the equivalent resistance of the transmission gate. Therefore, the equivalent resistance can be reduced even with a small transistor size. In the example of FIG. 2, when the same potential as the power supply is applied to the output current control input terminal 12, the high-level output current (IOH) becomes completely 0 and the output is fixed at the L level. Even if the same potential as the power supply is applied to the input terminal 12, the high-level output current flows even if the other Nch-Tr 27 is not completely turned off, and the output changes to H / L. There is an advantage that can be.

In the above description, the output buffer is described as a normal output buffer. However, the same can be applied to a three-state output buffer by changing the pre-driver preceding the output transistor.

In general, it is difficult to handle an analog signal in a CMOS digital circuit, and there is a problem as to where to supply a potential applied to an output current control terminal of an output buffer of the present invention. Of course, built-in circuits that generate analog voltages on semiconductor integrated circuits,
The voltage generated by this circuit can be applied to the control input terminal.

As a simpler method, there is a method of supplying a voltage from an external terminal of the IC to an output current control terminal via an input buffer or the like for preventing static electricity. In general, a plurality of the same output buffers are often used at an output terminal of a bus or the like, and it is sometimes desired to control these plurality of output buffers to the same output current. In this case, since the output current control terminals can be simultaneously controlled by connecting them in common, the number of external terminals of the IC does not need to be increased unnecessarily, and the present invention can be used efficiently.

[0027]

As described above, the use of the present invention has an effect that the value of the output current can be continuously changed by the voltage level applied to the control input terminal. As a result, if the load capacitance connected to the output terminal of the semiconductor integrated circuit changes in the past, the delay time also changes. However, according to the present invention, the output current can be adjusted to make the delay time the same. You can also.

[Brief description of the drawings]

FIG. 1 is a diagram showing a circuit diagram of an output buffer according to the present invention.

FIG. 2 is a diagram showing a circuit diagram of a second embodiment of the present invention.

FIG. 3 is a diagram showing a circuit diagram of another embodiment of the present invention.

FIG. 4 is a diagram showing a conventional circuit example.

[Explanation of symbols]

 1 is power supply 2 is GND 11 is input terminal of output buffer 12 and 13 is input terminal for output current control 14 is output terminal of output buffer 21 to 30 are N-channel MOS transistors 41 to 50 are P-channel MOS transistors 61 is an inverter

Claims (3)

[Claims] 1. A CMOS semiconductor integrated circuit comprising:
The source of the P-channel MOS transistor is connected to the power supply, the drain of the first P-channel MOS transistor is connected to the source of the second P-channel MOS transistor, and the drain of the second P-channel MOS transistor is connected. The drain is connected to the output terminal, the source of the third N-channel MOS transistor is connected to the ground, and the drain of the third N-channel MOS transistor is connected to the source of the fourth N-channel MOS transistor. The drain of the fourth N-channel MOS transistor is connected to an output terminal, an arbitrary voltage level is applied to the gate of one of the first and second P-channel MOS transistors, and the other P-channel MOS transistor is applied. A signal to be output is given to the gate of the transistor. Alternatively, another arbitrary voltage level is applied to the gate of one of the fourth N-channel MOS transistors, a signal to be output is applied to the gate of the other N-channel MOS transistor, and the output current is controlled. Output buffer to feature. 2. A CMOS semiconductor integrated circuit comprising:
The source of the P-channel MOS transistor is connected to the power supply, the source of the second N-channel MOS transistor is connected to the ground, and the first P-channel MOS transistor is connected to the ground.
The drain of the OS transistor, the drain of the second N-channel MOS transistor, the source of the third P-channel MOS transistor, and the source of the fourth N-channel MOS transistor are commonly connected, and the third P-channel MOS transistor is connected. Connecting the drain of the MOS transistor and the drain of the fourth N-channel MOS transistor to an output terminal;
An output buffer wherein an arbitrary voltage level is applied to the gate of the transistor and another arbitrary voltage level is applied to the gate of the fourth N-channel MOS transistor to control the output current. 3. An output buffer, wherein a normal output buffer and the output buffer according to claim 1 are connected in parallel.