JPH11265938A - 半導体装置及びその製造方法 - Google Patents

半導体装置及びその製造方法

Info

Publication number
JPH11265938A
JPH11265938A JP10068309A JP6830998A JPH11265938A JP H11265938 A JPH11265938 A JP H11265938A JP 10068309 A JP10068309 A JP 10068309A JP 6830998 A JP6830998 A JP 6830998A JP H11265938 A JPH11265938 A JP H11265938A
Authority
JP
Japan
Prior art keywords
film
semiconductor device
barrier metal
forming
metal film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10068309A
Other languages
English (en)
Japanese (ja)
Other versions
JPH11265938A5 (2
Inventor
Junichiro Iba
淳一郎 井場
Masaki Narita
雅貴 成田
Tomio Katada
富夫 堅田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP10068309A priority Critical patent/JPH11265938A/ja
Priority to US09/268,678 priority patent/US6313535B1/en
Publication of JPH11265938A publication Critical patent/JPH11265938A/ja
Publication of JPH11265938A5 publication Critical patent/JPH11265938A5/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/038—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers covering conductive structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/033—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/083—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts the openings being via holes penetrating underlying conductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/425—Barrier, adhesion or liner layers

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
JP10068309A 1998-03-18 1998-03-18 半導体装置及びその製造方法 Pending JPH11265938A (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP10068309A JPH11265938A (ja) 1998-03-18 1998-03-18 半導体装置及びその製造方法
US09/268,678 US6313535B1 (en) 1998-03-18 1999-03-16 Wiring layer of a semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10068309A JPH11265938A (ja) 1998-03-18 1998-03-18 半導体装置及びその製造方法

Publications (2)

Publication Number Publication Date
JPH11265938A true JPH11265938A (ja) 1999-09-28
JPH11265938A5 JPH11265938A5 (2) 2005-07-14

Family

ID=13370089

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10068309A Pending JPH11265938A (ja) 1998-03-18 1998-03-18 半導体装置及びその製造方法

Country Status (2)

Country Link
US (1) US6313535B1 (2)
JP (1) JPH11265938A (2)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040191697A1 (en) * 2003-03-24 2004-09-30 Communications Research Laboratory Method for processing a niobium type thin film and method for manufacturing a superconducting integrated circuit
JP4447419B2 (ja) * 2004-09-29 2010-04-07 Ｎｅｃエレクトロニクス株式会社 半導体装置の製造方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4158613A (en) * 1978-12-04 1979-06-19 Burroughs Corporation Method of forming a metal interconnect structure for integrated circuits
US4786962A (en) * 1986-06-06 1988-11-22 Hewlett-Packard Company Process for fabricating multilevel metal integrated circuits and structures produced thereby
JP2655213B2 (ja) * 1991-10-14 1997-09-17 三菱電機株式会社 半導体装置の配線接続構造およびその製造方法
US5635763A (en) * 1993-03-22 1997-06-03 Sanyo Electric Co., Ltd. Semiconductor device having cap-metal layer
US5518805A (en) * 1994-04-28 1996-05-21 Xerox Corporation Hillock-free multilayer metal lines for high performance thin film structures
US5818110A (en) * 1996-11-22 1998-10-06 International Business Machines Corporation Integrated circuit chip wiring structure with crossover capability and method of manufacturing the same

Also Published As

Publication number Publication date
US6313535B1 (en) 2001-11-06

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