JPH1126773A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

(57) [Problem] To provide a semiconductor device and a method of manufacturing the same, which can reduce the cost and improve the reliability of the device. SOLUTION: An insulating film 6 is provided on a supporting substrate 7, and an active region 1a of a semiconductor device and a lower wiring layer 5 are provided in the insulating film 6.
And a connection region 1b for connecting this to the upper wiring is buried. The active region 1a and the connection region 1b are formed at substantially the same thickness with the insulating film 6 interposed therebetween. One side of a lower wiring layer (also serving as a lower gate electrode) 5 is formed below the active region 1a via a lower gate insulating layer 4, and the other side of the lower wiring layer 5 is formed below the connection region 1b. An upper gate insulating layer 4a is formed on the active region 1a, an upper gate electrode 8 having an upper wiring portion is formed on the upper gate insulating layer 4a, and an upper wiring portion is formed on the connection region 1b. The thermal oxide film 2 is formed on the insulating film 6. Therefore, it is possible to reduce the price of the device and improve the reliability.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a semiconductor device and a method for manufacturing the same which can realize a reduction in the price of the device and an improvement in reliability.

[0002]

2. Description of the Related Art As a conventional semiconductor device, there is a device having a double gate structure in which a semiconductor device is embedded in an insulating layer and further has an upper electrode and a lower electrode. In this semiconductor device, it is necessary to take out the wiring of the lower electrode to the upper part.

[0003] As a manufacturing process of such a semiconductor device, a V for removing a wiring of a lower electrode to an upper part in an insulating layer is used.
A step of forming ia Hole and a step of embedding polysilicon, metal, or the like in the via hole are required.

[0004]

As described above, the conventional method for manufacturing a semiconductor device requires a step of forming a via hole and a step of embedding a metal or the like in addition to the step of forming a semiconductor element portion. Therefore, the number of steps increases accordingly, which is one of the factors that hinder the cost reduction of the semiconductor device.

In addition, with the miniaturization of elements, the embedding may be insufficient in the step of embedding metal or the like, which causes a reduction in yield and a reduction in wiring reliability.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor device and a method of manufacturing the same, which can realize a reduction in the price of the device and an improvement in reliability. .

[0007]

In order to solve the above-mentioned problems, a semiconductor device according to the present invention connects an active region, a lower wiring and an upper wiring of a semiconductor device having substantially the same thickness and insulated from each other. A connection region, a lower wiring formed on one surface of the connection region, an insulating film for embedding the lower wiring, the connection region and the active region of the semiconductor device, and formed on the other surface of the connection region; Upper wiring,
Is provided. It is preferable that the semiconductor device further includes a support substrate attached to a surface of the insulating film.

In a method of manufacturing a semiconductor device according to the present invention, a step of forming an active region of a semiconductor device and a connection region for connecting a lower wiring and an upper wiring to the semiconductor substrate by etching the surface of the semiconductor substrate. Forming a lower wiring on one surface of the connection region; forming an insulating film on the lower wiring and the semiconductor substrate;
Polishing the back surface of the semiconductor substrate so that the active region and the connection region of the semiconductor device remain; and forming an upper wiring on the other surface of the connection region.

In the method of manufacturing a semiconductor device, the active region of the semiconductor device and the connection region for connecting the lower wiring and the upper wiring are formed in the semiconductor substrate by etching the surface of the semiconductor substrate. Of the active region and the connection region can be formed with substantially the same thickness. Further, an insulating film is formed on the lower wiring and the semiconductor substrate. Therefore, there is no need to form a via hole for connecting the lower wiring and the upper wiring.
There is no need for a step of embedding metal or the like in the hole. Therefore, it is advantageous in manufacturing the device, and therefore, a higher yield can be achieved, and higher reliability of the wiring can be realized.

[0010]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1A is a cross-sectional view illustrating a semiconductor device according to a first embodiment of the present invention.
FIG. 2B is a cross-sectional view taken along line 1b-1b shown in FIG. This semiconductor device has a double gate structure.

As shown in FIG. 1, an insulating film 6 is provided on a supporting substrate 7, for example, a silicon substrate, and the active regions 1a, 1c, 1
d, a lower wiring layer 5 and a connection region 1b connecting the lower wiring layer 5 and the upper wiring are buried. That is, the active region of the semiconductor device (the channel region 1a shown in FIG.
The source / drain regions 1c and 1d shown in FIG. 2B and the connection region 1b connecting the lower wiring and the upper wiring are formed of silicon with substantially the same thickness with the insulating film 6 interposed therebetween. A thermal oxide film 2 is formed between the side surface of each of the active region 1a and the connection region 1b and the insulating film 6. One side of a lower wiring layer (also serving as a lower gate electrode) 5 is formed below the active region 1a of the semiconductor device with a lower gate insulating layer 4 interposed therebetween. The other side of the lower wiring layer 5 is formed below the connection region 1b. Thereby, the lower wiring layer 5 is electrically connected to the connection region 1b.

An upper gate insulating layer 4a is formed on the active region 1a of the semiconductor device, and an upper gate electrode 8 having an upper wiring portion is formed on the upper gate insulating layer 4a. An upper wiring portion is formed on the connection region 1b. Thereby, the upper gate electrode 8
Are electrically connected to the connection region 1b. The thermal oxide film 2 is formed on the insulating film 6.

The connection region 1b may be formed in the channel region 1a of the active region of the semiconductor device via the insulating film 6, or may be formed in the source or drain region 1c of the active region of the semiconductor device. 1d may be formed via the insulating film 6.

According to the first embodiment, the active regions 1a, 1c and 1d of the semiconductor device made of silicon and the connection region 1b connecting the lower wiring and the upper wiring are formed in the insulating film 6 with substantially the same thickness. Embedded in For this reason, the Via connecting the lower wiring and the upper wiring as in the prior art is used.
No special steps are required to form the holes. Therefore, it is advantageous in manufacturing a device, and therefore, a high yield can be achieved and a device can be manufactured at low cost. Further, since it is not necessary to embed metal or the like in the Via Hole, it is advantageous for improving the reliability of the wiring.

Further, the active regions 1a, 1
c, 1d and the connection region 1b are formed with substantially the same thickness. Therefore, when the upper gate electrode 8 is formed, the surface thereof is almost flat, which is very advantageous in defocusing in the subsequent steps.

FIG. 2A is a sectional view showing a semiconductor device according to a second embodiment of the present invention. The same parts as those in FIG. 1 are denoted by the same reference numerals, and only different parts will be described.

An upper gate electrode 8 is formed on the upper gate insulating layer 4a. The upper wiring 8a is formed on the connection region 1b. Thus, the upper wiring 8a is electrically connected to the connection region 1b.

The same effects as those of the first embodiment can be obtained in the second embodiment.

FIG. 2B is a sectional view showing a modified example of the semiconductor device shown in FIG. 2A. The same parts as those in FIG. 2A are denoted by the same reference numerals, and only different parts will be described. I do.

The semiconductor device shown in FIG. 2A has a double gate structure, while the semiconductor device shown in FIG. 2B has a single gate structure. Therefore, the semiconductor device of FIG. 2B does not have a lower gate insulating layer. The channel forming region 1a is electrically connected to the lower electrode 5, and the lower electrode 5 is electrically connected to the channel forming region 1a.
Are formed for bias control.

In the above modification, the same effect as in the second embodiment can be obtained.

FIG. 3A is a sectional view showing a semiconductor device according to a third embodiment of the present invention. The same parts as those in FIG. 1 are denoted by the same reference numerals, and only different parts will be described. This semiconductor device has a double gate structure.

An upper gate insulating layer 4a is formed on the active region 1a of the semiconductor device. In the active region 1a of the semiconductor device, diffusion layers 1c and 1d of a channel forming region and source / drain regions (n ⁺ or p ⁺ ) are formed. An upper gate electrode 8 is formed on the upper gate insulating layer 4a. The upper wiring 8a is formed on the connection region 1b. Thus, the upper wiring 8a is electrically connected to the connection region 1b.

The same effects as in the first embodiment can be obtained in the third embodiment.

FIG. 3B is a cross-sectional view showing a modification of the semiconductor device shown in FIG. 3A. In FIG. 3A, the same parts as those in FIG. I do.

The semiconductor device shown in FIG. 3A has a double gate structure, while the semiconductor device shown in FIG. 3B has a single gate structure. Therefore, the semiconductor device of FIG. 3B does not have a lower gate oxide film. The active region (channel forming region) 1a of the semiconductor device is electrically connected to the lower electrode 5, and the lower electrode 5 is formed for controlling the bias of the channel forming region 1a.

In the above-described modified example, the same effect as in the third embodiment can be obtained.

FIGS. 4 to 11 are sectional views showing a method for manufacturing a semiconductor device according to the fourth embodiment of the present invention.

First, as shown in FIG.
On top of this, a Si ₃ N ₄ film 21 is provided. Next, this S
A resist film (not shown) is formed on the i ₃ N ₄ film 21, and the Si ₃ N ₄ film 21 is patterned using the resist film as a mask. After this, the patterned Si
₃ N ₄ film 21 as a mask RIE (Reactive Ion Etch
ing), the first and second convex silicon projections 1 are formed on the surface of the silicon substrate 1.
a and 1b are formed. The first silicon protrusion 1a is a region that forms a semiconductor device (active region of the semiconductor device), and the second protrusion 1b is a region that serves to connect a lower wiring 5 and an upper wiring 8b described later. . Next, the resist film is removed.

The second protrusion 1b is doped with a high concentration of impurity by ion implantation or the like. This step may be performed before the formation of the protrusion, or may be performed in an appropriate step after the formation of the protrusion. It is also possible to do. FIG. 4 is a cross-sectional view of the channel formation region immediately below the gate, in which the first protrusion 1a is a portion showing the channel formation region. Therefore,
The source / drain regions are formed at positions as shown in FIG. 1B and are not shown in FIG. 4 because they are located on the near side and the back side in the figure.

Thereafter, as shown in FIG. 5, a thermal oxide film 2 having a thickness of, for example, about 20 nm is formed on the surface of the silicon substrate 1 by a thermal oxidation method. Next, an interlayer insulating layer 3 made of SiO ₂ is formed on the thermal oxide film 2 by TEOSCVD or the like. Thereafter, a resist film (not shown) is formed on a region other than the first protrusion 1a, and the Si ₃ N ₄ film 21 on the first protrusion 1a is removed by etching using the resist film as a mask. Next, the resist film is removed. As a result, the upper surface of the interlayer insulating layer 3 is
The height is almost the same as the upper surface of a.

Next, as shown in FIG.
On the upper surface of a, a thermal oxide film 4 having a thickness of, for example, about 10 nm is formed by a thermal oxidation method. This thermal oxide film 4 constitutes a gate insulating film of a device (MOS transistor).

Thereafter, as shown in FIG. 7, the Si ₃ N ₄ film 21 on the second protrusion 1b is removed by etching. Next, for example, a polysilicon film is deposited on the thermal oxide film (lower gate oxide film) 4, the interlayer insulating layer 3, and the second protrusion 1b. Next, a resist film (not shown) is formed on the polysilicon film, and the polysilicon film is etched using the resist film as a mask, thereby forming the upper portion of the lower gate oxide film 4 and the second protrusion 1b. Is left so that the polysilicon film 5 is bridged. This polysilicon film 5
The portion on the lower gate oxide film 4 is the lower gate electrode 5
The portion on the second protrusion 1b forms a connection wiring portion (lower wiring) 5. Thereafter, the resist film is removed.

Next, as shown in FIG. 8, on the polysilicon film (lower gate electrode, connection wiring portion) 5 and the interlayer insulating layer 3, SiO 2 is used as a dielectric film for planarizing the entire surface of the substrate.
x-based insulating film 6, for example, BPSG (borophosphosilicate)
A glass) film 6 is formed (shown upside down). This BPSG film 6 is made of an O ₃ -TEOS (tetraethoxysilane) -based material and further TMB (trimethyl boric acid).
And a normal pressure CVD using a gas system to which TMP (trimethyl phosphate) is added. Note that the method of forming the SiOx-based insulating film 6 is not limited to this method.
(Spin-on-glass) coating, normal pressure CVD using an O ₃ -TEOS system, H ₂ O-TEOS plasma CVD, etc., as long as the method can achieve excellent step coverage and high flatness, other forming methods can be used. Can also be used.

Thereafter, the substrate is turned upside down, and the surface of the BPSG film 6 is brought into contact with the surface of another silicon substrate 7 as shown in FIG.

Next, as shown in FIG.
The silicon substrate 1 is polished from the back surface side until the KK plane (shown in FIG. 8) is exposed. That is, the silicon substrate 1 is polished using the thermal oxide film 2 as a stopper. At this time, this polishing is performed by, for example, a known CMP (chemical mechanical polishing) method. As a result, the first projection 1a (a portion forming a semiconductor device) and the second projection 1b (a portion that plays a role of connecting a lower wiring and an upper wiring) of the silicon substrate 1 remain, and the first and the second projections 1b are left. The two projections 1a and 1b are Si layers having an island shape in plan view. The process up to this point is
The typical procedure of the bonded SOI is followed.

Thereafter, as shown in FIG. 10, a Si ₃ N ₄ layer (not shown) is formed on the second protrusion 1b.
By performing thermal oxidation using the i ₃ N ₄ layer as a mask, an upper gate insulating film 4a is formed on the surface of the first protrusion 1a. Next, the Si ₃ N ₄ layer is removed.

Next, as shown in FIG. 11, for example, a polysilicon film is deposited on the upper gate insulating film 4a, the second protrusion 1b, and the thermal oxide film 2. Thereafter, an unillustrated Si ₃ N ₄ as a mask film is formed on the polysilicon film.
A layer is formed. Next, by etching the polysilicon film using the Si ₃ N ₄ layer as a mask, an upper gate electrode (also serving as a wiring) 8a is formed on the upper gate insulating film 4a, and at the same time, the second protrusion is formed. Upper wiring 8b is formed on portion 1b. Thereby, the upper wiring 8
b is electrically connected to the lower wiring 5 via the second protrusion 1b. Thereafter, the Si ₃ N ₄ layer is removed.

According to the fourth embodiment, as shown in FIG. 4, a region for forming a semiconductor device is formed on the surface of the silicon substrate 1 by performing etching by RIE using the Si ₃ N ₄ film 21 as a mask. Is formed, and at the same time, a second silicon protrusion 1b, which is a region serving to connect the lower wiring 5 and the upper wiring 8b, is formed. For this reason, Via H for connecting the lower wiring and the upper wiring as in the prior art is used.
The need to form an ole is eliminated. This is because the role of Via Hole is fulfilled by the second silicon projection 1b. Therefore, a special process for forming such a via hole is not required, which is advantageous in manufacturing a device. Therefore, a high yield can be achieved and a device can be manufactured at low cost. In addition, the above Via Hol
Since there is no need to embed metal or the like in e, it is advantageous for improving the reliability of wiring.

The first and second silicon projections 1
By forming a and 1b at the same time, the first and second silicon protrusions 1a and 1b can be formed to have the same thickness. Therefore, when the upper wiring 8b is formed, as shown in FIG. 10, the surface thereof is almost flattened, which is very advantageous in defocusing in the subsequent steps.

In the fourth embodiment, in order to simplify the description of the manufacturing process, the first projection 1a, which is a region constituting a semiconductor device, and the lower wiring and the upper wiring are connected. Although the present invention is applied to a semiconductor device having one second protrusion 1b, which is a region that plays a role, the first and second protrusions 1a and 1b are formed as in a normal ULSI fabrication. The present invention can be applied to a semiconductor device having a large number of semiconductor devices.

Further, the connection region 1b is replaced with the active region 1a
The connection region 1b may be formed in the source or drain region of the active region 1a with the interlayer insulating film 3 interposed therebetween.

In the first to fourth embodiments,
Although the present invention is applied to a device having an SOI structure such as bonding or SIMOX, it is also possible to apply the present invention to a device having a TFT structure on silicon.

Although the present invention is applied to a device using a silicon semiconductor, the present invention is not limited to this, and the present invention can be applied to a device using a compound semiconductor such as GaAs.

[0045]

As described above, according to the present invention, the active region of the semiconductor device and the connection region for connecting the lower wiring and the upper wiring can be formed on the surface of the semiconductor substrate with substantially the same thickness. Therefore, cost reduction and improvement in reliability of the semiconductor device can be realized.

[Brief description of the drawings]

FIG. 1A is a cross-sectional view illustrating a semiconductor device according to a first embodiment of the present invention, and FIG.
It is sectional drawing which followed the 1b-1b line | wire shown to (a).

FIG. 2A is a cross-sectional view showing a semiconductor device according to a second embodiment of the present invention, and FIG.
FIG. 14 is a cross-sectional view illustrating a modification of the semiconductor device illustrated in FIG.

FIG. 3A is a cross-sectional view illustrating a semiconductor device according to a third embodiment of the present invention, and FIG.
FIG. 14 is a cross-sectional view illustrating a modification of the semiconductor device illustrated in FIG.

FIG. 4 is a sectional view illustrating a method for manufacturing a semiconductor device according to a fourth embodiment of the present invention.

FIG. 5 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the fourth embodiment of the present invention, which is a step subsequent to FIG. 4;

FIG. 6 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the fourth embodiment of the present invention, showing a step subsequent to FIG. 5;

FIG. 7 is a cross-sectional view illustrating the method for manufacturing the semiconductor device according to the fourth embodiment of the present invention, which is a step subsequent to FIG. 6;

FIG. 8 is a sectional view illustrating the method for manufacturing the semiconductor device according to the fourth embodiment of the present invention, which is a step subsequent to FIG. 7;

FIG. 9 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the fourth embodiment of the present invention, showing a step subsequent to FIG. 8;

FIG. 10 is a sectional view illustrating the method for manufacturing the semiconductor device according to the fourth embodiment of the present invention, which is a step subsequent to FIG. 9;

FIG. 11 illustrates a method for manufacturing a semiconductor device according to a fourth embodiment of the present invention, and is a cross-sectional view illustrating a step subsequent to that of FIG.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Silicon substrate, 1a ... First silicon projection, active region (channel region) of semiconductor device, 1b ... Second silicon projection, 1c, 1d ... Source / drain region (active region of semiconductor device), lower part Connection area for connecting wiring and upper wiring, 2 ... thermal oxide film, 3 ... interlayer insulating layer, 4
... thermal oxide film (lower gate oxide film), 4a ... upper gate insulating layer, 5 ... polysilicon film (lower gate electrode, connection wiring section, lower wiring), 6 ... insulating film (BPSG), 7 ... support substrate (silicon) Substrate), 8 ... Upper gate electrode, 8a, 8b
... Upper wiring, 21 ... Si ₃ N ₄ film.

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁶ Identification code FI H01L 29/78 626Z 627D 627A

Claims (8)

[Claims] A connection region for connecting an upper region and an active region and a lower region of a semiconductor device having substantially the same thickness and insulated from each other; a lower line formed on one surface of the connection region; A semiconductor device comprising: a lower wiring, an insulating film filling the connection region and an active region of the semiconductor device, and an upper wiring formed on the other surface of the connection region. 2. The semiconductor device according to claim 1, further comprising a support substrate attached to a surface of said insulating film. 3. The semiconductor device according to claim 1, wherein a part of said lower wiring is formed on one surface of an active region of said semiconductor device via a gate insulating film. 4. A part of the lower wiring is formed on one surface of the active region of the semiconductor device via a gate insulating film, and a part of the upper wiring is formed on the other surface of the active region of the semiconductor device. 2. The semiconductor device according to claim 1, wherein the semiconductor device is formed via a gate insulating film. 5. The semiconductor device according to claim 1, wherein said connection region is formed in a channel region in an active region of said semiconductor device via an insulating film. 6. The semiconductor device according to claim 1, wherein said connection region is formed in a source or drain region in an active region of said semiconductor device via an insulating film. 7. A step of forming an active region of a semiconductor device and a connection region for connecting a lower wiring and an upper wiring on the semiconductor substrate by etching a surface of the semiconductor substrate; and forming a lower region on one surface of the connection region. Forming a wiring; forming an insulating film on the lower wiring and the semiconductor substrate; polishing the back surface of the semiconductor substrate so that the active region and the connection region of the semiconductor device remain. And a step of forming an upper wiring on the other surface of the connection region. 8. The method of manufacturing a semiconductor device according to claim 5, further comprising, after the step of forming the insulating film, a step of bonding a surface of the insulating film to a surface of the support substrate.