JPH11272725A - Library generation method and simulation method - Google Patents

Abstract

(57) [Summary] [PROBLEMS] To enable quick logic simulation of a custom designed circuit even when layout information or process information is changed. SOLUTION: A simulation apparatus is composed of a modified net list generation means, a temporary library generation means, a logic simulation means, and a storage unit. Modified netlist 1
1 and assigns the layout information 13 and the process information 14 to the parameters of the parameterized library in the storage unit to generate a temporary library of power consumption and delay time. Since the logic simulation is performed on the logic circuit of the modified netlist using the temporary library, even if the element design parameter is changed, it can be quickly dealt with.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a parameterization library at a logic gate level and a delay time library for each logic gate based on element design parameter information for setting parameters corresponding to each logic gate of the parameterization library. The present invention relates to a method for generating a library, and a simulation method for calculating a delay time of a logic circuit by performing a logic simulation based on a delay time library set corresponding to a netlist and a logic gate level of the logic circuit.

[0002]

An LSI such as a CPU
(Large-scale integrated circuits)
In order to simulate the delay time and power consumption of a circuit, estimation is generally performed using a logic simulation. This is because, in a transistor-level circuit simulation represented by SPICE, the number of gates is large, so that a large amount of time is required for the simulation, and processing cannot be performed within a practical time.

Therefore, when performing calculations by logic simulation, it is necessary to create and set in advance a delay time library and a power consumption library. In this case, generation of these libraries is supposed to be performed by transistor-level circuit simulation. However, it generally takes a lot of time to perform arithmetic processing for generating the libraries.

In this case, in a method of setting a standard cell and designing a circuit, a library is generated by performing a circuit simulation at a transistor level in advance for a limited type of standard cells used in the design. Therefore, in circuit design, logic simulation can be performed by using a predetermined standard cell.

[0005] However, even if cells having the same function (logical operation) have different types of gates used, as in a custom design, there are many types of cells having different sizes. A library must be created for each gate. Therefore, a library must be generated by performing a transistor-level circuit simulation in advance for each circuit to be designed, but this may be necessary for circuit simulation for library generation depending on the size of the circuit and the type of gate used. It can take a lot of time.

Similarly, not only in the case of custom design but also in the case of designing using standard cells, a library is generated each time the process design is changed or the design rules are changed. Therefore, a great deal of time is required for a circuit simulation for such a process, and such a process design or a change in a design rule involves practical difficulties.

To solve such technical problems, Japanese Patent Laid-Open No.
Japanese Unexamined Patent Publication No.-226077 discloses a configuration in which a circuit simulator is automatically executed based on layout information, and a delay time library is modified without manual intervention.

In Japanese Unexamined Patent Publication No. 1-156864, a transistor-level delay time is calculated from layout data, a process parameter file, and a calculation formula, and the calculated delay time is stored in a netlist for each transistor. There is disclosed a technique that solves the problem by adding a time to enable a high-speed simulation with an accuracy close to an actual product.

However, in the case of the former, it is unnecessary to manually start the circuit simulation to generate the library, and it is not necessary to manually perform the processing. However, since the circuit simulation itself is used for generating the library, the processing time is reduced. Since it is not shortened, it has not reached an essential solution. Also, in the latter case, the purpose is to improve the accuracy of the simulation, and the amount of information required for the simulation is increased, and the simulation is performed at the transistor level. Is difficult.

Therefore, the following technical problems remain under such prior art. First, since gates and drain / source areas of custom-designed gates such as CPUs are individually different, creating a library for logic simulation for all sizes results in a large library and practical use. Cannot be performed within a typical processing time. Second, when there is a small change in process design or design rules, a new logic simulation library needs to be generated, but it takes a lot of time to generate it.

The present invention has been made in view of the above circumstances, and has as its object to enable a custom designed circuit to be simulated at a gate level. In this case, a circuit layout change is schematically performed by a gate level simulation. It is an object of the present invention to provide a simulation method and a simulation apparatus capable of providing a library that enables a result to be verified at high speed and that can immediately respond to a change in process design or design rule.

[0012]

According to the first aspect of the present invention, in the process of generating the delay time library, the parameterizing library determines the values of the load capacitance and the driving capability of the input terminal of each logic gate by using element design parameters. Since the function is set as a function based on the information, the parameter corresponding to each logic gate is substituted for the element design parameter information into the function to calculate the load capacitance and the fan-out value of the input terminal. Obtaining a delay time corresponding to the logic gate from the result, to generate a delay time library.

Thus, when performing a logic simulation, when simulating the delay time along the netlist, the delay time corresponding to each logic gate is set to the delay time set in the delay time library. Can be performed quickly. Therefore,
Even when the element design parameters are changed, it is not necessary to find the delay time through a transistor-level circuit simulation, and the logic simulation can be performed using a delay time library according to the changed parameters.

According to the second aspect of the present invention, in the above-described case, since the layout information of the logic gate is included as the element design parameter information, the change of the layout of the logic gate is performed by the parameterization library. A gate delay time library can be quickly obtained, and a logic simulation for a change in layout design can be quickly performed.

According to the third aspect of the present invention, the device design parameter information includes process information indicating a process parameter for forming a logic gate. Therefore, when the manufacturing process is changed, each logic associated with the change is changed. A gate delay time library can be quickly obtained, and a logic simulation for a change in process design can be quickly performed.

According to the fourth aspect of the present invention, in the step of obtaining the delay time, the delay time is obtained based on the slope data of the input signal of the logic gate and the delay time function defined as a function of the fan-out. Even when the element design parameters of the logic gate, such as information and process information, are changed, the corresponding logic based on the delay time function is obtained from the result of calculating the slope data and fanout value of the input signal of the logic gate corresponding to this. A delay time library can be obtained by calculating the delay time of the gate.

According to the fifth aspect of the present invention, in the step of obtaining the delay time, the delay time is determined with reference to a preset delay time table determined from the slope data of the input signal of the logic gate and the fan-out. Even if the element design parameters of the logic gate, such as layout information and process information, are changed, from the result of calculating the slope data of the input signal of the logic gate and the value of the fanout corresponding thereto, the delay corresponding to these is obtained. The time can be obtained quickly by referring to the table to obtain a delay time library.

According to the sixth aspect of the present invention, in the above case, the input signal of the logic gate calculated by calculating the slope data or the fan-out data of the input signal set in the delay time table. When there is no corresponding value in the table for the slope data and the fanout value, for example, when the value takes an intermediate value, the interpolation processing step interpolates the value set in the table to obtain the delay time. It is possible to obtain a more accurate delay time corresponding to an intermediate value without making the setting interval of the input signal gradient data and the fan-out data for creating a table unnecessarily small. .

According to the seventh aspect of the present invention, there is provided a step of obtaining power consumption, whereby the data of the slope of the input signal of the logic gate and the result of obtaining the fan-out are obtained.
Since the power consumption library can be obtained by obtaining the power consumption corresponding to the logic gate, the power consumption library can be used simultaneously with the delay time library in the logic simulation. According to the eighth to tenth aspects of the present invention, a power consumption library can be generated in the same manner as the above-described generation of the delay time library.
This can be used simultaneously with the delay time library for logic simulation.

According to the eleventh aspect of the present invention, in the modified netlist generating step, a modified netlist including layout information is generated from the netlist of the logic circuit and the layout information of each corresponding logic gate. In the provisional library generation step, a provisional library relating to the delay time of each logic gate is generated based on a parameterization library for each logic gate and element design parameter information for setting parameters corresponding to each logic gate of the parameterization library. Become like

At this time, in the process of generating the delay time library, the parameterized library sets the values of the load capacitance and the driving capability of the input terminal of each logic gate as functions based on the element design parameter information. Substituting the parameters corresponding to the individual logic gates into the element design parameter information into the function to calculate the load capacitance and fanout value of the input terminal, and obtaining the delay time corresponding to the logic gate from the result Through the steps, a delay time library can be generated.

Thus, in the subsequent logic simulation step, the logic simulation is performed by referring to the delay time data of the temporary library in accordance with the contents of the generated modified netlist, so that the element design of each logic gate of the logic circuit is performed. Even when the parameter is changed, it is not necessary to obtain the delay time through the circuit simulation at the transistor level, and the logic simulation can be performed using the delay time library according to the changed parameter.

According to the twelfth to twentieth aspects of the present invention, a temporary library of delay time or a temporary library of power consumption can be generated in the same manner as described above, and a logical simulation of a corrected netlist can be performed using the temporary library. Therefore, as described above, even when the element design parameters of each logic gate of the logic circuit are changed, it is not necessary to obtain the delay time through a transistor-level circuit simulation, and the delay time library according to the changed parameters is not required. Can be used to perform a logic simulation.

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) A first embodiment in which the present invention is applied to a logic simulation apparatus will be described below with reference to FIGS. That is, FIG. 2 schematically shows the configuration of the logic simulation apparatus 1, which comprises an arithmetic processing unit 2, an input device 3 and an output device 4. The arithmetic processing unit 2 includes a modified net list generating means 5 for executing a modified net list generating step, a temporary library generating means 6 for executing a temporary library generating step, and a logic simulation means 7 for executing a logical simulation step.
It has the function of

The arithmetic processing unit 2 has a storage unit 8
Are connected, and are configured to transmit and receive data. The storage unit 8 includes a parameterized library storage unit 9 for storing a parameterized library, a temporary library storage unit 10 for storing delay time and power consumption data as a temporary library, and a corrected netlist storage unit for storing a corrected netlist. 11 are provided.
The arithmetic processing unit 2 refers to the information in each of the storage units 9 to 11 of the storage unit 8 when performing the arithmetic processing.

The parameterized library stored in the parameterized library storage unit 9 stores data of delay time and power consumption of a logic gate assumed to be used for a circuit to be designed, as a function or table of element design parameter information. Is stored. Using this parameterized library, a temporary library is generated by calculating the delay time and power consumption corresponding to each logic gate by performing arithmetic processing from the layout information described in the modified netlist as described later. This is stored in the temporary library storage unit 10.

As will be described later, the input device 3 receives input data such as a net list 12, layout information 13, and process information 14, and the like.
The output device 4 outputs delay time data 15 and power consumption data 16 obtained as a result of the arithmetic processing.

In the above description, the net list 12 describes data indicating a connection mode of a target circuit.
It shows the input / output relationship of the unit circuit. The layout information 13 describes data corresponding to the shape and size of a transistor constituting a unit circuit. For example, data such as a gate width, a source area, and a drain area are individually specified. The process information 14 is parameter information of a process adopted in a manufacturing process of an integrated circuit including a logic circuit to be designed, and specifies, for example, a thickness dimension of a gate oxide film.

Next, the operation of the present embodiment will be described.
FIG. 1 schematically shows an execution process of a logic simulation. When the netlist 12 describing the circuit configuration and the layout information 13 of each logic gate of the circuit configuration are input via the input device 3, the logic simulation apparatus 1
In the arithmetic processing unit 2, the corrected net list generating means 5
Executes a corrected netlist generation step S1 to generate a netlist including layout information from these as a corrected netlist, and to store this in the corrected netlist storage unit 11.

Next, the temporary library generation means 6 executes a temporary library generation step S2, and parameterizes the corrected netlist obtained as described above and the process information 14 inputted via the input device 3. A target logic gate of the parameterized library stored in the library storage unit 9 is read, and the layout information 13 and the process information 14 are substituted into the logic gate to determine the load capacity and the driving capacity of the input terminal of each logic gate. From these, the delay time and the power consumption are obtained from the delay time table and the power consumption table, respectively. By obtaining these for the necessary logic gates, a temporary library of the delay time and power consumption of the target logic circuit is generated, and this is stored in the temporary library storage unit 10.

After that, the logic simulation means 7
When executing the logic simulation step S3, a logic simulation of delay time and power consumption is executed in accordance with the corrected netlist stored in the corrected netlist storage unit 11. At this time, the delay time and power consumption of each logic gate are determined. Performs a logic simulation by referring to the temporary library data of the delay time and the power consumption stored in the temporary library storage unit 10. As a result, the delay time data 15 and the power consumption data 16 of the target logic circuit can be obtained via the output device 4.

Next, the above-described logic simulation will be described with reference to the logic circuit shown in FIG. 3 as an example, and the contents of the logic simulation will be described in detail below. First, FIG.
The logic circuit 21 will be briefly described. Input terminal A,
B and C, and output terminals YO and YB. 2
The input NAND circuit 22 has an output terminal N1, and input terminals A and B are connected to each input terminal. Similarly, a two-input NAND circuit 23 includes a NAND circuit 2 at each input terminal.
2, the output terminal N1 and the input terminal C are connected, and the output terminal is connected to YO. The INV (inverter; negative logical product) circuit 24 has an input terminal connected to the output terminal N1 of the NAND circuit 22, and an output terminal connected to YB.

FIG. 4 describes the above configuration as a netlist. That is, in this netlist, cell names (G1 to G3), designation of output terminals and input terminals, and types of cells are described for each row. In this case, first cell G1 and second cell G2 are both NAND circuits 22 and 23 performing the same logical operation.
Is supported. Note that what is shown as “NAND2” is a two-input NAND circuit like the NAND circuits 22 and 23.
2 shows a circuit.

Next, FIG. 5 shows an object to be a parameter when inputting as the layout information 13 and the process information 14. Here, the configuration of the MOSFET forming the logic gate is shown. FIG. 1A shows a plan view, and FIG. 1B shows a schematic sectional view.
In the illustrated MOSFET, a gate electrode made of polysilicon or the like is formed between a source / drain diffusion region via a gate oxide film.

The layout information 13 describes data corresponding to the shape and size of the MOSFET.
Data such as the gate width W and the source and drain areas Ad are specified. The process information 14 is parameter information of a process adopted in the manufacturing process of the MOSFET, and specifies, for example, a thickness dimension of the gate oxide film Tox.

FIG. 6A shows an example in which the layout information shown in FIG. 5A is described. Each of the logic gates G1 to G described in the netlist of FIG.
3 shows the layout data of each unit corresponding to No. 3 (NAND circuits 22, 23, INV circuit 24). in this case,
Since the NAND circuit 22 uses four MOSFETs, the dimensions of the gate widths W1 to W4 (μm is indicated by u) and the sizes of the areas Ad1 to Ad4 (p
the m ² indicated by p). Similarly, the layout information of the NAND circuit 23 is described in G2, and the layout information of the INV circuit 24 is described in G3. On the other hand, FIG.
Describes the thickness Tox of the gate oxide film in FIG. 5B as process information.
It is described in units.

Now, the net list 12, layout information 13 and process information 14 as described above are input to the input device 3.
Is input through the arithmetic processing unit 2 as described above.
In, the corrected netlist generating means 5 generates a netlist including the layout information and outputs the generated netlist as a corrected netlist (corrected netlist generation step S1). This modified netlist is, for example, a description example as shown in FIG. That is, the layout information shown in FIG. 6 is combined with the above-described netlist of FIG. 4 to generate a cell type unique to the cell type (in the figure, NAND201, NAND202 or INV0).
1). The corrected netlist generated in this manner is stored and held in the corrected netlist storage unit 11.

Next, the temporary library generation means 6 executes a temporary library generation step S2 to generate a temporary library of delay time and a temporary library of power consumption. First, the parameterization library stored in the parameterization library storage unit 9 is read, and data set as parameters is input.

The parameterization library is described, for example, as shown in FIG. 8, and a function corresponding to each of the logic gates G1 to G3 in the modified net list is described for each of the two-input NAND circuit module and the INV circuit module. calculate. The function is set with, for example, the total capacitance values Cx and Cy loaded on the wiring of the input signal, the driving capability R of the preceding logic gate, the power consumption Pw, the delay time Td, and the like. The operation is performed by substituting the layout information and the process information thus obtained.

Next, the rise time Tri and the fan-out FO of the input signal are calculated for each of the NANDs 22 and 23. The rise time Tri of the input signal is determined by the product of the total capacitance value applied to the wiring of the input signal and the driving capability of the preceding gate. For the NAND circuit 22 of the logic circuit 21 shown in FIG. 3, the rise time of the input terminal X (the input terminal connected to the output terminal of the NAND circuit 22) is represented by Tr
Assuming that i (23), the load capacitance of the input terminal of the NAND circuit 23 is represented by Cx (23), the load capacitance of the input terminal of the INV circuit 24 is represented by Cx (24), and the driving capability of the NAND circuit 22 is represented by R (22). That is, Tri (23) = [Cx (23) + Cx (24)] × R
(22) can be obtained. Similarly, the rising time T of the input signal is applied to the other terminals of the NAND circuits 22 and 23.
ri can be obtained.

Next, since the calculation of the fan-out value is expressed as the total capacitance value applied to the wiring of the output signal of each logic gate, for example, the fan-out FO (22) of the NAND circuit 22 is (22) = Cx (23) + Cx (24) The same calculation can be performed for the terminals of other logic gates.

Here, the parameterized library stored in the parameterized library storage unit 9 includes the load capacitance Cx and the driving capability R of the input terminal used in the above-described calculation.
Are expressed as functions using data corresponding to each element design parameter of the layout information 13 and the process information 14 as a parameter.
It can be determined using these data.

Now, the parameterized library storage unit 9
Tables of power consumption Pw and delay time Td as shown in FIGS. 10 and 11 are stored in advance. These are configured to obtain the values of the power consumption Pw and the delay time Td from the values of the rise time Tri and the fan-out FO of the input terminal, respectively, and the rise time of the input terminal obtained by the calculation as described above. The power consumption Pw and the delay time Td are obtained by referring to the table based on the values of Tri and the fan-out FO. The power consumption Pw described in this table
The data of the delay time Td is obtained in advance by a circuit simulation or the like, and is calculated by dividing the data at necessary data intervals.

In this case, the value obtained by the calculation does not directly correspond to the value of the rising time Tri or the value of the fan-out FO described in the table, and an intermediate value between them is taken. At this time, the values of the tables on both sides of the value obtained by the calculation are linearly interpolated to interpolate the corresponding power consumption Pw and delay time Td. In the case of interpolating both the rise time Tri and the fan-out FO, so-called surface interpolation is performed to calculate even an intermediate value, thereby obtaining more accurate values of the power consumption Pw and the delay time Td. Can be obtained.

When the power consumption Pw and the delay time Td are obtained for each logic gate in this manner,
Power consumption P corresponding to each logic gate as shown in FIG.
w and the delay time Td can be obtained,
The temporary library generating means 6 causes the temporary library storage unit 10 to store the temporary library as a temporary library.

Next, the logic simulation means 7 carries out a logic simulation step S 3, and the power consumption of the corrected netlist stored in the corrected netlist storage unit 11 and the temporary library stored in the temporary library storage unit 10. The logic simulation is performed with reference to each data of the library of Pw and the delay time Td. As a result, the delay time of the entire logic circuit 21 is obtained using the delay time Td of the temporary library in the same manner as in the normal logic simulation, and after the total number of events is confirmed, the power consumption is calculated. The delay time data 15 and the power consumption data 16 can be obtained.

According to this embodiment, when the element design parameter information such as the layout information and the process information constituting each logic gate is changed in designing the logic circuit, the delay based on these changes is considered. Since the logic simulation is performed after the temporary library of time and power consumption is generated based on the parameterized library, unlike the conventional method of obtaining delay time and power consumption by performing circuit simulation etc. according to the change of element design parameters, Although the calculation accuracy is not so high, a logic simulation with relatively high accuracy can be quickly and quickly performed.

In addition, even in the case of the same logic gate, even in the case of a custom-designed logic circuit configuration having various types of layout information, it is not necessary to generate a library corresponding to each of them in advance. Since a library required for each logic simulation of a logic circuit can be generated as a temporary library, the logic simulation can be realized by a simple method of describing layout information without increasing the size of the library. become.

Note that the temporary library described in the above embodiment may be slightly reduced in accuracy due to the quick and simple operation compared to the data of delay time and power consumption obtained by general circuit simulation. is there. However, it is possible to improve this point by making the calculation method more detailed or by setting it in accordance with the actual characteristics. This has a relationship with the required accuracy of the logic simulation and the required time. However, compared with the conventional one which requires a circuit simulation uniformly, the one of the present embodiment corresponds to the desired accuracy. Thus, the degree of freedom for design changes can be increased in that the logic simulation can be selectively performed.

(Second Embodiment) FIG. 12 shows a second embodiment of the present invention. The difference from the first embodiment is that a temporary execution is performed separately from the actual execution of the logic simulation. I have just created a library. That is, the configuration of the device is the same as that in the first embodiment,
The process up to the point at which a temporary library is generated without using the above is performed.

As shown in FIG. 12, when layout information 13 and process information 14 to be used for each logic gate are input in advance as element design parameter information, the temporary library generating means 6 executes a temporary library generating step S2a. . When the temporary library is generated, calculation is performed in the same manner as in the first embodiment. At this time, each parameter is calculated by directly referring to the layout information 13 without using the modified netlist. Thereby, a temporary library as shown in FIG. 9 is generated with reference to the description of the parameterized library shown in FIG.

As a result, even when the library is changed in accordance with the change of the element design parameters such as the layout and the process, a library corresponding to the change can be generated quickly and with a certain accuracy. As a result, it is possible to quickly perform a logic simulation on a logic circuit designed by the changed layout or process.

Further, by generating a temporary library as described above corresponding to a logic circuit in advance, even when a general logic simulation apparatus is used,
By using the obtained data of the temporary library, a logic simulation can be quickly performed.

The present invention is not limited to the above embodiment, but can be modified or expanded as follows. The power consumption and the delay time are determined using a table, but may be determined by describing a function including a rise time and a fanout of an input signal and substituting parameter data into the function. Alternatively, an appropriate conditional statement may be set to obtain data of an area satisfying these conditions.

The case where the present invention is applied to the logic simulation for calculating the power consumption in addition to the delay time has been described.
If the data of the power consumption is not required, the data may be obtained only for the delay time. In the first embodiment, even if a temporary library generation step is not separately provided and the temporary library generation step is stored in the temporary library storage unit 10, the library data obtained while simultaneously generating the temporary library during the logic simulation step is obtained. May be used.

As the types of the element design parameters used as the layout information 13 and the process information 14, in addition to the above, parameters such as the gate length and the drain / source peripheral length can be incorporated as the layout information. Parameters such as the junction capacitance, the number of wiring layers, the mobility of the channel, the contact resistance, and the SPICE parameters can be incorporated, and parameters that are expected to affect the values of the delay time and the power consumption can be appropriately introduced.

[Brief description of the drawings]

FIG. 1 is a schematic flowchart of a processing procedure according to a first embodiment of the present invention;

FIG. 2 is a schematic block diagram.

FIG. 3 is a configuration diagram of a logic circuit used as a specific example of a logic simulation;

FIG. 4 is a description example of a netlist

FIG. 5 is a configuration diagram of a MOSFET for explaining parameters of layout information and process information.

FIG. 6 is a description example of layout information and process information.

FIG. 7 is a description example of a modified netlist

FIG. 8 is a description example of a parameterizing library.

FIG. 9 is a description example of a temporary library of delay time and power consumption.

FIG. 10 is a table of power consumption.

FIG. 11 is a table of delay time.

FIG. 12 is a view corresponding to FIG. 1, showing a second embodiment of the present invention;

[Explanation of symbols]

1 is a logic simulation device, 2 is an arithmetic processing device, 3
Is an input device, 4 is an output device, 5 is a corrected net list generating unit, 6 is a temporary library generating unit, 7 is a logic simulation unit, 8 is a storage unit, 9 is a parameterized library storage unit, 10 is a temporary library storage unit, 11 is a corrected net list storage unit, 12 is a net list, 13 is layout information, 14 is process information, 15 is delay time data,
16 is power consumption data, 21 is a logic circuit, 22 and 23 are NAND (negative AND) circuits, and 24 is an INV (inversion) circuit.

Claims (20)

[Claims] 1. A library generating method for generating a delay time library for each logic gate based on a parameterization library at a logic gate level and element design parameter information for setting parameters corresponding to each logic gate of the parameterization library. In the parameterization library, the values of the load capacitance and the driving capability of the input terminal of each of the logic gates are set as a function based on the element design parameter information. In the process of generating the delay time library, Calculating the slope data and the fanout of the input signal of the logic gate from the load capacitance and the driving ability of the input terminal by the parameterization library; and calculating the logic gate from the slope and the fanout of the input signal obtained by the calculation. Corresponding to Library generation method characterized by generating the delay time libraries by performing the determining a serial delay time. 2. The library generation method according to claim 1, wherein the element design parameter information includes layout information of the logic gate. 3. The library generation method according to claim 1, wherein the element design parameter information includes process information indicating a process parameter for forming the logic gate. 4. The library generation method according to claim 1, wherein in the step of obtaining the delay time, the delay time defined as a function of a slope data and a fan-out of an input signal of the logic gate. A library generation method, wherein the delay time is obtained based on a function. 5. The library generation method according to claim 1, wherein in the step of obtaining the delay time, the delay time determined from preset slope data of the input signal of the logic gate and fan-out. A library generation method, wherein the delay time is obtained by referring to the table of (1). 6. The library generation method according to claim 5, wherein, in the step of obtaining the delay time, the calculation is performed on the slope data or the fan-out data of the input signal set in the delay time table. When the data of the slope of the input signal of the logic gate and the value of the fanout obtained by the above are not directly applicable, the value set in the table is interpolated to obtain the delay time. A library generation method. 7. The library generation method according to claim 1, wherein the slope of the input signal and the fanout of the input signal obtained by the step of calculating the data of the slope of the input signal of the logic gate and the fanout are calculated. A method for generating a power consumption library, comprising the step of obtaining power consumption corresponding to a logic gate from data, and generating a power consumption library. 8. The library generation method according to claim 7, wherein, in the step of obtaining the power consumption, the power consumption function defined as a function of fan-out and data of a slope of an input signal of the logic gate. A library generation method characterized by calculating power consumption. 9. The library generation method according to claim 7, wherein in the step of obtaining the power consumption, a power consumption table determined from a preset slope data of an input signal of the logic gate and a fanout is set. A library generation method, wherein the power consumption is obtained by referring to the power consumption. 10. The library generation method according to claim 9, wherein, in the step of obtaining the power consumption, the calculation is performed on the data of the slope of the input signal or the data of the fan-out set in the table of the power consumption. When the data of the slope of the input signal of the logic gate and the value of the fanout obtained by the above are not directly applicable, the power consumption is obtained by interpolating the value set in the table. A library generation method. 11. A simulation method for calculating a delay time of a logic circuit by performing a logic simulation based on a delay time library set corresponding to a netlist and a logic gate level of the logic circuit, A modified netlist generating step of generating a modified netlist including layout information from the netlist and the layout information of each of the corresponding logic gates; and a parameterization library for each of the logic gates and a corresponding logic gate of the parameterization library. A temporary library generating step of generating a temporary library related to the delay time of each of the logic gates based on element design parameter information for setting the adjusted parameters; and the logical simulation based on the corrected netlist and the temporary library. A logic simulation step of calculating a delay time of the logic circuit by performing a simulation.The parameterization library calculates a value of a load capacitance and a driving capability of an input terminal of each of the logic gates based on the element design parameter information. In the process of generating the temporary library of the delay time,
Calculating the data and the fanout of the slope of the input signal of the logic gate from the load capacitance and the driving ability of the input terminal by the parameterization library; and calculating the logic from the slope and the fanout of the input signal obtained by the calculation. Calculating the delay time corresponding to a gate to generate a temporary library of the delay time. 12. The simulation method according to claim 11, wherein the element design parameter information includes layout information of the logic gate. 13. The simulation method according to claim 11, wherein the element design parameter information includes process information indicating a process parameter for forming the logic gate. 14. The simulation method according to claim 11, wherein in the step of obtaining the delay time, a delay time function defined as a function of a slope data and a fan-out of an input signal of the logic gate. A simulation method, wherein the delay time is obtained based on the following. 15. The simulation method according to claim 11, wherein, in the step of obtaining the delay time, the delay time determined from a preset slope data of the input signal of the logic gate and a fanout is set. A simulation method, wherein the delay time is obtained by referring to a table. 16. The simulation method according to claim 15, wherein, in the step of obtaining the delay time, the calculation is performed on the slope data or the fan-out data of the input signal set in the delay time table. An interpolation processing step of interpolating the value set in the table and obtaining the delay time when the obtained data of the slope of the input signal of the logic gate and the value of the fanout do not directly correspond to each other. A simulation method characterized in that: 17. The simulation method according to claim 11, wherein the data of the slope of the input signal of the logic gate and the data of the slope of the input signal and the fan-out data obtained in the step of calculating the fan-out. A step of obtaining a power consumption corresponding to the logic gate from the logic gate, and a step of generating a temporary library of the power consumption. In the logic simulation step, the logic is based on the corrected netlist and the temporary library of the power consumption. A simulation method comprising calculating power consumption of a circuit. 18. The simulation method according to claim 17, wherein, in the step of obtaining the power consumption, the power consumption is defined based on a slope data of an input signal of the logic gate and a power consumption function defined as a function of a fan-out. A simulation method characterized by calculating electric power. 19. The simulation method according to claim 17, wherein, in the step of obtaining the power consumption, a table of power consumption determined from a preset slope data of an input signal of the logic gate and a fan-out. And calculating the power consumption. 20. The simulation method according to claim 19, wherein, in the step of obtaining the power consumption, the calculation is performed on the slope data or the fan-out data of the input signal set in the power consumption table. An interpolation processing step of interpolating the value set in the table and obtaining the power consumption when the obtained data of the slope of the input signal of the logic gate and the value of the fan-out do not directly correspond to each other. A simulation method characterized in that: