JPH11274644A - Semiconductor light emitting device and method of manufacturing the same - Google Patents

Abstract

(57) [Problem] To reduce the operating voltage of a semiconductor light emitting element and prevent deterioration of characteristics. SOLUTION: The light guide layers 104 and 106 are formed in an active layer 1.
05, the impurity rare regions 132 and 142, the impurity intermediate concentration regions 131 and 141, and the impurity added region 13
0 and 140.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor light emitting device such as a semiconductor laser device and a light emitting diode device, and a method for manufacturing the same.

[0002]

2. Description of the Related Art As a conventional semiconductor laser device, a quantum well laser using a quantum well layer in an active layer serving as a light emitting portion is known. This quantum well laser has various advantages such as a reduction in operating current and an improvement in noise characteristics.

In a quantum well type laser, a structure capable of increasing light confinement in an active layer includes a separated confinement structure (SCH: Separate Con
finement Heterostructure)
There is.

The forbidden band width and the refractive index of a compound semiconductor layer are generally in inverse proportion to each other, and the Al mixed crystal ratio and the forbidden band width of a compound semiconductor layer containing Al are generally in a proportional relation.

Accordingly, the band diagram near the active layer in the quantum well laser having the SCH structure is, for example, shown in FIG.
The result is as shown in FIG.

[0006] This semiconductor laser device has a multiple quantum well (MQ) comprising a plurality of quantum well layers 510 and a barrier layer 511.
QW (MultiQuantumWell) active layer 50
The first light guide layer 502 and the second light guide layer 503 having a larger forbidden band width than the quantum well layer 510 across both outer sides of the first light guide layer 510.
Is provided. An n-first cladding layer 504 and a p-second cladding layer 505 having a larger forbidden band width than the first light guide layer 502 and the second light guide layer 503 are provided on both sides thereof.

In this semiconductor laser device, carriers are confined in the quantum well layer 510, and light is confined in the first light guide layer 502 and the second light guide layer 503.

A semiconductor laser device having such an SCH structure is disclosed in, for example, Japanese Patent Publication No.
No. 252508, and the like.

In the semiconductor laser device disclosed in Japanese Patent Publication No. 4-67354, impurities are added to the entire area of the light guide layer. In the semiconductor laser element disclosed in Japanese Patent Laid-Open No. 6-252508, impurities are added to the entire area of the light guide layer. Is not added.

[0010]

In the above-described SCH structure, the light confinement efficiency is improved by increasing the thickness of the light guide layer, and a low threshold current can be obtained.
Therefore, it is desirable to increase the thickness of the light guide layer in order to reduce the current.

However, when no impurity is added to the light guide layer as in the semiconductor laser device disclosed in JP-A-6-252508, the layer resistance of the light guide layer becomes large, There is a problem that an operating voltage increases because a potential barrier is generated between the layers.

On the other hand, when an impurity is added to the light guide layer as in the semiconductor laser device disclosed in Japanese Patent Publication No. 4-67354, the impurity diffuses from the light guide layer to the active layer during energization. As a result, a non-radiative recombination center is formed in the active layer, so that an internal absorption loss occurs, and there is a problem that laser characteristics deteriorate.

Further, in the prior art, the effect of adding impurities to the semiconductor layer adjacent to the active layer including the light guide layer on the laser characteristics has not been studied in detail.

The same applies to semiconductor laser devices other than the quantum well laser device, and the same can be said for a light emitting diode device having cladding layers on the upper and lower sides of the active layer.

The present invention has been made to solve such problems of the prior art, and has as its object to provide a semiconductor light emitting device capable of reducing operating voltage and preventing deterioration of characteristics, and a method of manufacturing the same. I do.

[0016]

According to a semiconductor light emitting device of the present invention, there is provided a semiconductor light emitting device having an active layer and cladding layers provided above and below the active layer. And an impurity-doped region, wherein the impurity-rare region is disposed on the side closer to the active layer, thereby achieving the above object.

According to a semiconductor light emitting device of the present invention, in a semiconductor light emitting device having an active layer and light guide layers provided above and below the active layer, at least one of the light guide layers comprises an impurity rare region and an impurity added region. And the impurity rare region is arranged on the side closer to the active layer, whereby the object is achieved.

According to a semiconductor light emitting device of the present invention, in a semiconductor light emitting device having an active layer and a light guide layer provided on one of the upper and lower sides of the active layer, the light guide layer comprises an impurity rare region and an impurity added region. And the impurity rare region is arranged on the side closer to the active layer, whereby the object is achieved.

[0019] An intermediate impurity concentration region may be provided between the impurity rare region and the impurity added region.

[0020] The active layer may comprise a quantum well layer.

When the impurity in the impurity added region of the light guide layer is p-type, the carrier concentration of the impurity is preferably 4 × 10 ¹⁷ cm ⁻³ or more and 1.2 × 10 ¹⁸ cm ⁻³ or less. .

When the impurity in the impurity-added region of the light guide layer is n-type, it is preferable that the carrier concentration of the impurity is not less than 2 × 10 ¹⁷ cm ^{−3 and not} more than 1 × 10 ¹⁸ cm ⁻³ .

[0023] The impurity concentration in the impurity rare region can be set to 1/5 or less of the impurity concentration in the impurity added region.

The thickness of the impurity rare region is 3 nm or more and 1
It is preferably 0 nm or less.

[0025] The impurity rare region may be provided at least in a p-type cladding layer or a p-type light guide layer.

In the impurity rare region, the thickness provided in the p-type clad layer or the p-type light guide layer is larger than the thickness provided in the n-type clad layer or the n-type light guide layer. preferable.

The thickness of the impurity intermediate concentration region is preferably 3 nm or more and 10 nm or less.

[0028] The active layer is constituted by a multiple quantum well layer including a plurality of quantum well layers and a barrier layer sandwiched between the plurality of quantum well layers, and the light guide includes the impurity rare region and the impurity added region. The forbidden band width of at least the impurity-added region in the layer may be smaller than the forbidden band width of the barrier layer and larger than the forbidden band width of the quantum well layer.

In the light guide layer, a forbidden band width of the impurity added region may be smaller than a forbidden band width of the impurity rare region.

The cladding layer or the light guide layer is made of Al
GaAs-based material, AlGaInP-based material or InGaN
It may be made of a system material.

The method for manufacturing a semiconductor light emitting device according to the present invention is a method for manufacturing a semiconductor light emitting device according to the present invention, in which an impurity-added layer and an impurity-free layer are grown, and the impurity-added layer is formed by a thermal history during crystal growth. The impurity is diffused into the impurity-free layer to form the impurity intermediate concentration region, thereby achieving the above object.

The thickness of the impurity-free layer provided in the p-type cladding layer or the p-type light guide layer forming portion is defined as n
It is preferable that the thickness be larger than the thickness of the one provided on the mold cladding layer or the n-type light guide layer forming part.

The operation of the present invention will be described below.

According to the present invention, at least one of the cladding layers provided above and below the active layer has an impurity rare region and an impurity added region, and the impurity rare region having an impurity concentration lower than that of the impurity added region is activated. Since it is arranged on the side close to the layer, diffusion of impurities from the impurity added region to the active layer during energization can be suppressed in the impurity rare region.

According to another aspect of the present invention, since at least one of the light guide layers provided above and below the active layer has an impurity-doped region, the resistance of the entire light guide layer can be reduced. Since the diffusion potential between the layer and the cladding layer can be reduced, the operating voltage can be reduced. Further, since the impurity rare region having an impurity concentration lower than that of the impurity added region is disposed closer to the active layer, diffusion of impurities from the impurity added region to the active layer during energization is suppressed by the impurity rare region. The reliability of the element can be improved.

According to another aspect of the present invention, since the light guide layer provided on one of the upper and lower sides of the active layer has an impurity added region, the resistance of the entire light guide layer can be reduced. Since the diffusion potential between the cladding layer and the cladding layer can be reduced, the operating voltage can be reduced. Further, since the impurity rare region having an impurity concentration lower than that of the impurity added region is disposed closer to the active layer, diffusion of impurities from the impurity added region to the active layer during energization is suppressed by the impurity rare region. The reliability of the element can be improved.

Further, an impurity intermediate concentration region having an impurity concentration lower than that of the impurity addition region and higher than that of the impurity rare region is provided between the impurity rare region and the impurity addition region. Since impurities can be prevented from diffusing into the impurity rare region,
The reliability of the device can be further improved.

In particular, when the active layer comprises a quantum well layer,
Even though slight impurity diffusion during energization causes a change in the layer structure and is likely to cause characteristic deterioration, the present invention is very effective because impurity diffusion into the active layer during energization can be suppressed.

When the impurity in the impurity-added region of the light guide layer is p-type, the carrier concentration of the impurity is 4 ×
It is preferably set to 10 ¹⁷ cm ⁻³ or more and 1.2 × 10 ¹⁸ cm ⁻³ or less. When the impurity in the impurity-added region of the light guide layer is n-type, the carrier concentration of the impurity is preferably set to 2 × 10 ¹⁷ cm ⁻³ or more and 1 × 10 ¹⁸ cm ⁻³ or less. By setting this range, the operating voltage can be effectively reduced, and the characteristic degradation due to non-radiative recombination of carriers in the impurity added region can be effectively suppressed. Note that the impurity concentration in the impurity-added region of the cladding layer may be a concentration having a function of confining carriers to the active layer as the cladding layer.

If the impurity carrier concentration in the impurity-rare region is equal to or less than 1/5 of the impurity carrier concentration in the impurity-doped region, impurity diffusion into the active layer during energization can be effectively suppressed.

The thickness of the impurity rare region is 3 nm or more and 1
It is preferably 0 nm or less. If the thickness is less than 3 nm, impurities may diffuse into the active layer during energization, causing deterioration of characteristics. If the thickness exceeds 10 nm, carrier injection from the impurity-added region to the active layer is hindered due to a potential barrier. The voltage may increase. The thickness of the impurity-added region may be a thickness necessary for confining carriers in the active layer as a cladding layer in the case of a cladding layer, and a thickness necessary for confining light in the case of a light guiding layer. Good.

The impurity rare region may be provided only on the p-type cladding layer or p-type light guide layer side. This is because the p-type impurity has a larger diffusion coefficient than the n-type impurity, and the impurity easily diffuses into the active layer to cause characteristic deterioration. In this case, p
Since it is only necessary to control the thickness of the impurity rare region of the mold,
Element design is easy.

Alternatively, of the rare-earth regions described above, the thickness provided in the p-type clad layer or the p-type light guide layer may be greater than the thickness provided in the n-type clad layer or the n-type light guide layer. . In this case, for a p-type impurity having a larger diffusion coefficient than an n-type impurity, the thickness of the impurity-rare region can be controlled in accordance with the degree of diffusion, so that controllability in element design can be improved. .

The thickness of the impurity intermediate concentration region is preferably 3 nm or more and 10 nm or less. With this range, the diffusion of impurities from the impurity-added region to the impurity-rare region during energization can be effectively prevented, and the carrier injection from the impurity-added region to the active layer is not hindered.

When the active layer is formed of a multiple quantum well layer, at least the forbidden band width of the impurity added region in the optical guide layer is smaller than the forbidden band width of the barrier layer and smaller than the forbidden band width of the quantum well layer. May be larger. In general,
The Al mixed crystal ratio of the semiconductor layer containing Al and the forbidden band width are in a proportional relationship, and the Al mixed crystal ratio can be reduced by reducing the forbidden band width of the impurity-added region. Impurity diffusion into the layer can be further reduced. Further, since impurity diffusion from the impurity-added region to the active layer is reduced, the thickness of the impurity-rare region can be set to be thin, which is effective for reducing the operating voltage.

Here, with respect to the entire optical guide layer including the impurity rare region and the impurity intermediate concentration region, the forbidden band width is smaller than the forbidden band width of the barrier layer and larger than the forbidden band width of the quantum well layer. However, if the forbidden band width of the impurity added region is made smaller than the forbidden band width of the impurity rare region, carrier confinement in the active layer can be performed in the impurity rare region. Therefore, the Al mixed crystal ratio in the impurity-added region can be further reduced, and the impurity diffusion from the impurity-added region to the active layer can be further reduced. Further, since the diffusion of impurities from the impurity-added region to the active layer can be reduced, the thickness of the impurity-rare region can be set to be thin, which is effective in reducing the operating voltage.

The cladding layer or the light guide layer is made of AlGa
It may be an As-based material, an AlGaInP-based material, an InGaN-based material, or the like. In particular, the AlGaInP-based material is effective because impurities are easily diffused as compared with the AlGaAs-based material. Further, AlGaIn is used for InGaN-based materials.
This is effective because the growth temperature is higher than that of the P-based material and diffusion of impurities easily occurs.

In the present invention, since the impurity is diffused from the impurity-added layer to the impurity-free layer by the thermal history during the crystal growth to form the impurity intermediate concentration region, the impurity added region and the impurity intermediate concentration region are formed. The impurity rare region can be formed by a simple manufacturing process with good controllability. The temperature of the heat history (crystal growth temperature) at this time is, for example, AlGa
In the case of As-based materials, the temperature is 600 ° C. to 800 ° C.
In the case of nP-based materials, the temperature is 500 ° C. to 700 ° C., and InGaN
The temperature is 900 ° C. to 1100 ° C. for the base material, but is about 50 ° C. to 200 ° C. lower than the growth temperature of the active layer in order to control diffusion.
The intermediate impurity concentration region may be formed at a low temperature.

The thickness of the impurity-free layer provided in the p-type cladding layer or the p-type light guide layer forming portion is defined as n
It may be thicker than that provided in the mold cladding layer or the n-type light guide layer forming portion. In this case, for the p-type impurity having a larger diffusion coefficient than the n-type impurity, the thickness of the impurity-rare region can be controlled by controlling the thickness of the impurity-free region in accordance with the degree of diffusion. In addition, controllability of element design can be improved.

[0050]

Embodiments of the present invention will be described below with reference to the drawings.

Embodiment 1 In Embodiment 1, an example in which the present invention is applied to a ridge type semiconductor laser device will be described.

FIG. 1 is a sectional view of the semiconductor laser device of the first embodiment.

This semiconductor laser device comprises an n-GaAs buffer layer 102, an n-Al
_0.5 Ga _0.5 As first cladding layer 103, Al _0.35 Ga
_0.65 As first light guide layer 104, non-doped multiple quantum well active layer 105, Al _0.35 Ga _0.65 As second light guide layer 106, p-Al _0.5 Ga _0.5 As second clad layer 10
7. A p-GaAs etching stop layer 108 is laminated. A ridge stripe p-Al _0.5 Ga _0.5 As third cladding layer 109 and a p-GaAs cap layer 110 are provided on the center of the etching stop layer 108. N on both sides of the center of the etching stop layer 108 so as to embed both sides of the ridge stripe.
-Al _0.7 Ga _0.3 As current light confinement layer 111, n-G
aAs current blocking layer 112, p-GaAs planarization layer 113
Is provided. The p-GaAs contact layer 1 is formed over the cap layer 110 and the planarization layer 113.
14 are provided. p-GaAs contact layer 11
4, a p-type electrode 150 is provided, and an n-type electrode 151 is provided on the surface of the substrate 101 opposite to the semiconductor layer growth surface.

This semiconductor laser device can be manufactured, for example, as follows.

First, an n-type GaAs substrate 101 is subjected to a first MOCVD (metal organic chemical vapor deposition) method to form an n-type substrate.
GaAs buffer layer 102 (layer thickness 0.5 μm, dopant Si, carrier concentration 1 × 10 ¹⁸ cm ⁻³ ), n-Al
_0.5 Ga _0.5 As first cladding layer 103 (1.5 μm thick)
m, dopant Si, carrier concentration 8 × 10 ¹⁷ c
m ⁻³ ), Al _0.35 Ga _0.65 As first light guide layer 104,
Non-doped multiple quantum well active layer 105, Al _0.35 Ga
_0.65 As second light guide layer 106, p-Al _0.5 Ga _0.5 A
s second cladding layer 107 (layer thickness 0.25 μm, dopant Zn, carrier concentration 1 × 10 ¹⁸ cm ⁻³ ), p-GaAs
s etching stop layer 108 (layer thickness 0.003 μm,
Dopant Zn, carrier concentration 1 × 10 ¹⁸ cm ⁻³ ), p
-Al _0.5 Ga _0.5 As third cladding layer 109 (layer thickness 1.
0 μm, dopant Zn, carrier concentration 2 × 10 ¹⁸ cm
^-3 ) and p-GaAs cap layer 110 (layer thickness 0.7 μm).
m, dopant Zn, carrier concentration 3 × 10 ¹⁸ cm ⁻³ )
Grow.

Here, as shown in FIG. 2, the multiple quantum well active layer 105 has three Al _0.12 Ga _0.88 As quantum well layers 120 (0.008 μm thick) and two Al _0.35 Ga layers.
_0.65 As quantum barrier layer (barrier layer) 121 (layer thickness 0.00
(5 μm) so as to sandwich the barrier layer 121 between the multiple quantum well layers 120. Then, the first light guide layer 104
Represents an impurity-added layer (layer thickness 0.03 μm, dopant Si, carrier concentration 5 × 1) from the n-first cladding layer 103 side.
0 ¹⁷ cm ⁻³ ) and an impurity-free layer (layer thickness 0.02 μm). Further, the second light guide layer 106 includes an impurity-free layer (layer thickness 0.02 μm) and an impurity-added layer (layer thickness 0.03 μm, dopant Zn, carrier concentration 8 × 10 ¹⁷ cm ⁻³ ) from the active layer 105 side. And grew.

Next, the cap layer 110 is processed into a convex stripe (upper surface width: 2 μm) using the stripe resist pattern as a mask. The p-third cladding layer 109 is processed into a ridge stripe (2.5 μm bottom width) using the cap layer 110 of the convex stripe as a mask. At this time, the etching is stopped by the etching stop layer 108 on both outer sides of the ridge stripe. After the etching, the resist is removed.

Subsequently, n-Al _0.7 Ga _0.3 A is buried in the ridge stripe by the second MOCVD method.
s current light confinement layer 111 (layer thickness 0.6 μm, dopant Si, carrier concentration 1 × 10 ¹⁸ cm ⁻³ ), n-GaAs
s current blocking layer 112 (layer thickness 0.3 μm, dopant S
i, a carrier concentration of 1 × 10 ¹⁸ cm ⁻³ ) and a p-GaAs planarization layer 113 (layer thickness 0.3 μm, dopant Zn, carrier concentration of 1 × 10 ¹⁸ cm ⁻³ ) are grown.

After that, the unnecessary layer grown directly on the cap layer 110 is removed by etching to remove the cap layer 110.
Is adjusted to a thickness of 0.3 μm, and a p-GaAs contact layer 114 (thickness: 3 μm, dopant Zn, carrier concentration: 1 × 10 ¹⁹ cm) is formed over the cap layer 110 and the planarization layer 113 by the third MOCVD method. ^-3 ) to grow.

The thermal hysteresis temperature (crystal growth temperature) during the MOCVD growth is 600 ° C. to 800 ° C., whereby the first light guide layer 104 and the second light guide layer 106 change from an impurity-added layer to an impurity-free layer. Impurity diffusion of
The band diagram and the carrier concentration distribution near the active layer are as shown in FIG.

That is, the first light guide layer 104 is formed from the n-first cladding layer 103 side to the impurity added region 130 (having a layer thickness of 0.1.
03 μm) and the impurity intermediate concentration region 131 (layer thickness 0.01
μm) and the impurity rare region 132 (having a layer thickness of 0.01 μm) whose impurity concentration is less than 1/5 of the impurity added region 130.
m). On the other hand, the second light guide layer 106 is p-
From the second cladding layer 107 side, the impurity added region 140 (layer thickness 0.03 μm), the impurity intermediate concentration region 141 (layer thickness 0.01 μm), and the impurity rare concentration whose impurity concentration is 1/5 or less of the impurity added region 140. It is divided into a region 142 (layer thickness 0.01 μm). Therefore, the impurity added region, the impurity intermediate concentration region, and the impurity rare region are formed by a simple process with good controllability by the thermal history during the crystal growth of the semiconductor layer.

Finally, a p-type electrode 150 and an n-type electrode 151 are formed on the growth layer and the outer surface of the substrate 101, respectively. Here, the cavity length of the semiconductor laser device is 375 μm,
The end face of the light emitting side is set to 10% reflectance by a single layer film coating of Al ₂ O _3, the end face opposite to 75% reflectance by the multilayer film coating of Al ₂ O ₃ and Si.

Table 1 below shows the device characteristics of the thus obtained semiconductor laser device of Embodiment 1 when operated at room temperature with an optical output of 4 mW. For comparison,
The semiconductor laser device of Comparative Example 1 manufactured in the same manner as in Embodiment 1 except that no impurity was added to the entire region of the light guide layer, and Embodiment 1 except that the impurity was added to the entire region of the light guide layer. Table 1 below shows the device characteristics of the semiconductor laser device of Comparative Example 2 manufactured in the same manner.

[0064]

[Table 1]

As can be seen from Table 1, the first embodiment
Thus, the operating voltage, the operating current, and the element resistance can be reduced. On the other hand, the semiconductor laser device of Comparative Example 1 in which no impurity is added to the entire region of the light guide layer can reduce the operating current similarly to the semiconductor laser device of Embodiment 1, but the resistance of the light guide layer is reduced. The increase increases the element resistance, and furthermore, creates a potential barrier between the cladding layer and the optical guide layer, thereby increasing the operating voltage. Further, the semiconductor laser device of Comparative Example 2 in which impurities were added to the entire region of the light guide layer,
Although the operating voltage and the device resistance can be reduced similarly to the semiconductor laser device of the first embodiment, the laser characteristics are degraded due to impurity diffusion from the optical guide layer to the active layer during energization, and the operating current increases.

FIG. 3 shows a case where the carrier concentration of the impurity-added region of the first light guide layer 104 is fixed at 5 × 10 ¹⁷ cm ⁻³ and the carrier concentration of the impurity-added region of the second light guide layer 106 is changed. 5 shows the change in the operating voltage of FIG. FIG.
Then, the carrier concentration of the impurity-added region of the second light guide layer 106 is fixed at 8 × 10 ¹⁷ cm ⁻³ ,
4 shows a change in operating voltage when the carrier concentration of the impurity-doped region No. 4 is changed.

As can be seen from FIGS. 3 and 4, the carrier voltage in the impurity-added region increases and the operating voltage decreases.

For example, it is desirable to set the carrier concentration of the first light guide layer 104 to 2 × 10 ¹⁷ cm ⁻³ or more as shown in FIG. 4 because the operating voltage can be reduced to 1.9 V or less. However, if the carrier concentration of the first light guide layer 104 is too high, a non-emission center peculiar to the n-type impurity is generated, and the light emission efficiency is reduced in the first light guide layer 104 to cause deterioration of laser characteristics. The carrier concentration of the light guide layer 104 is desirably set to 1 × 10 ¹⁸ cm ⁻³ or less.

On the other hand, when the carrier concentration of the second light guide layer 106 is set to 4 × 10 ¹⁷ cm ⁻³ or more as shown in FIG. 3, the operating voltage can be reduced to 1.9 V or less. However, if the carrier concentration of the second light guide layer 106 is too high, the current spread in the second light guide layer 106 increases, causing an increase in the threshold current due to an increase in the reactive current. Is 1.2
It is desirable to set it to × 10 ¹⁸ cm ⁻³ or less.

Here, if the thickness of the impurity-rare regions of the light guide layers 104 and 106 is too large, the carrier injection from the impurity-doped region to the multiple quantum well active layer is hindered due to the potential barrier. However, it is desirable to set the thickness to such a level that the tunneling of the potential barrier is performed so that carrier injection can be performed smoothly, for example, 10 nm or less. However, if the layer thickness of the impurity-rare region is less than 3 nm, the impurity diffuses into the active layer during energization, causing deterioration in characteristics. Therefore, it is desirable to set the layer thickness of the impurity rare region to 3 nm or more. If the impurity carrier concentration in the impurity rare region is 1/5 or less of the impurity carrier concentration in the impurity added region, impurity diffusion into the active layer during energization can be effectively suppressed.

Further, by providing an impurity intermediate concentration region by impurity diffusion between the impurity added region and the impurity rare region, the impurity diffusion from the impurity added region during energization to the active layer can be reduced. Can be suppressed in both regions, which is further effective in preventing characteristic deterioration. In addition, since the potential barrier continuously changes in the impurity intermediate concentration region, the potential barrier can be relaxed. As a result, carriers can be smoothly injected into the active layer, so that the operating voltage can be further reduced. Can be. Preferably, the thickness of the impurity intermediate concentration region is 3 nm or more and 10 nm or less. With this range, the diffusion of impurities from the impurity-added region to the impurity-rare region during energization can be effectively prevented, and the carrier injection from the impurity-added region to the active layer is not hindered.

(Embodiment 2) In Embodiment 2, an example will be described in which the forbidden band width of the optical guide layer is smaller than the forbidden band width of the barrier layer and larger than the forbidden band width of the quantum well layer.

FIG. 5 is a sectional view of a semiconductor laser device according to the second embodiment.

This semiconductor laser device has an n-Ga _0.5 In _0.5 P buffer layer 202 on an n-GaAs substrate 201.
n- (Al _0.7 Ga _0.3 ) _0.5 In _0.5 P first cladding layer 2
03, (Al _0.7 Ga _0.3 ) _0.5 In _0.5 P first optical guide layer 204, non-doped multiple quantum well active layer 205, (Al
P- (A) having a _0.7 Ga _0.3 ) _0.5 In _0.5 P second light guide layer 206 and a ridge stripe 209 portion and a flat portion.
1 _0.7 Ga _0.3 ) _0.5 In _0.5 P second cladding layer 207 is laminated. On the ridge stripe 209 portion of the p-second cladding layer 207, a p-Ga _0.5 In _0.5 P cap layer 208 is formed. The p-second cladding layer 2 is buried on both sides of the ridge stripe 209.
07 on the flat portion of n-GaAs current light confinement layer 210
Is provided. A p-type electrode 212 is provided thereon over the cap layer 208 and the current / light confinement layer 210, and an n-type electrode 211 is provided on the surface of the substrate 201 opposite to the semiconductor layer growth surface.

This semiconductor laser device can be manufactured, for example, as follows.

First, an MOC is formed on an n-GaAs substrate 201.
The n-Ga _0.5 In _0.5 P buffer layer 20 is formed by the VD method.
2, n- (Al _0.7 Ga _0.3 ) _0.5 In _0.5 P first cladding layer 203 (layer thickness 1.5 μm), (Al _0.7 Ga _0.3 ) _0.5
In _0.5 P second optical guide layer 204, non-doped multiple quantum well active layer 205, (Al _0.7 Ga _0.3 ) _0.5 In _0.5 P second optical guide layer 206, p- (Al _0.7 Ga _0.3 ) _0.5 In
_0.5 P second cladding layer 207 (layer thickness 1.5 μm) and p
-Ga _0.5 In _0.5 P cap layer 208 (0.3 μm in thickness)
m) grow.

Here, the multiple quantum well active layer 205 is composed of three Ga _0.5 In _0.5 P quantum well layers 2 as shown in FIG.
20 (layer thickness 0.008 μm) and two layers (Al _0.5 G
a _0.5 ) _0.5 In _0.5 P barrier layer 221 (layer thickness 0.005)
μm) was grown so as to sandwich the barrier layer 221 between the multiple quantum well layers 220. Then, the first light guide layer 204
Means an impurity-added layer (layer thickness 0.015 μm, dopant Si, carrier concentration 7 ×) from the n-first cladding layer 203 side.
10 ¹⁷ cm ^-3 ) and impurity-free layer (layer thickness 0.02 μm)
And grew. Further, the second light guide layer 206 is formed from the active layer 205 side with an impurity-free layer (layer thickness 0.02 μm).
And an impurity-added layer (layer thickness 0.015 μm, dopant Z
n, and a carrier concentration of 1 × 10 ¹⁸ cm ⁻³ ).

The thermal history temperature (crystal growth temperature) during the MOCVD growth is from 500 ° C. to 700 ° C., whereby the first light guide layer 204 and the second light guide layer 206 change from an impurity-added layer to an impurity-free layer. Impurity diffusion of
The band diagram near the active layer is as shown in FIG.

That is, the first light guide layer 204 is formed from the side of the n-first cladding layer 203 to the impurity added region 230 (having a thickness of 0. 1).
01 μm) and the impurity intermediate concentration region 231 (layer thickness 0.01
5 μm) and impurity rare region 232 (layer thickness 0.01 μm)
Divided into On the other hand, the second light guide layer 206 is p-second
From the cladding layer 207 side, the impurity added region 240 (layer thickness 0.01 μm) and the impurity intermediate concentration region 241 (layer thickness 0.
015 μm) and the impurity concentration is divided into impurity rare regions 242 (layer thickness 0.01 μm). Therefore, the impurity added region, the impurity intermediate concentration region, and the impurity rare region are formed by a simple process with good controllability by the thermal history during the crystal growth of the semiconductor layer.

Next, the p-second cladding layer 207 and the cap layer 208 are etched and the p-second cladding layer 20 is etched.
Etching is stopped so that the remaining thickness of the flat portion 7 becomes 0.3 μm, and a ridge stripe 209 having a width of 5 μm is formed.

Subsequently, an n-GaAs current / light confinement layer 210 (1.2 μm thick) is grown by MOCVD so as to bury both sides of the ridge stripe 209.

Finally, a p-type electrode 212 and an n-type electrode 211 are formed on the growth layer and the outer surface of the substrate 201, respectively. Here, the cavity length of the semiconductor laser device is 5 by the cleavage method.
00 μm, and the end face on the light emission side of the resonator has a reflectance of 50 μm.
% And the opposite end face has a reflectance of 85%.

In the semiconductor laser device of Embodiment 2 obtained in this manner, as shown in FIG. 6, the forbidden band width of the first light guide layer 204 and the second light guide layer 206 is smaller than that of the quantum well layer 220. The forbidden band width is set to be larger than the forbidden band width and smaller than the forbidden band width of the barrier layer 221. Generally, since the Al mixed crystal ratio of the semiconductor layer containing Al and the forbidden band width are in a proportional relationship, the Al mixed crystal ratio (x = 0.3) of the first light guide layer 204 and the second light guide layer 206 is changed. Multiple quantum well active layer 205
Is set to be larger than the Al mixed crystal ratio (x = 0) of the quantum well layer 220 and smaller than the Al mixed crystal ratio (x = 0.5) of the barrier layer 221. Thereby, the Al mixed crystal ratio in the impurity added region of the light guide layer can be set relatively small.
Therefore, the diffusion of impurities from the impurity-added region to the active layer can be further reduced, which is further effective in preventing deterioration of characteristics.

Further, since impurity diffusion from the impurity-added region to the active layer can be further reduced, even if the layer thickness of the impurity-rare region is reduced, the impurity diffusion from the impurity-added region to the active layer during energization is reduced. Can be suppressed. Accordingly, since the current injection from the light guide layer to the active layer can be made smooth by reducing the layer thickness of the impurity rare region, the operating voltage can be reduced.

Further, since the forbidden band width of the compound semiconductor layer and the refractive index are generally in inverse proportion, the refractive index of the entire light guide layer is increased, the light confinement is increased, and the threshold current is reduced. Can be.

When a forward voltage is applied between the n-type electrode 211 and the p-type electrode 212 to the semiconductor laser device of the second embodiment, the oscillation wavelength is 0.65 μm and the threshold current is 30 m
A, the device characteristics when operated at a slope efficiency of 0.6 W / A of current-light output characteristics and a light output of 3 mW are an operation current of 35 mA and an operation voltage of 2 V. On the other hand, when the impurity is not added to the entire area of the light guide layer, the operating voltage increases to 2.3 V, and when the impurity is added to the entire area of the light guide layer, the operating voltage is 2 V. Has an operating current of 50 m due to impurity diffusion from the light guide layer during conduction to the active layer.
A. As described above, in the second embodiment, it is possible to reduce the operating voltage and prevent the characteristic deterioration due to the increase in the operating current.

(Embodiment 3) In Embodiment 3, the forbidden band width of the impurity added region of the optical guide layer is smaller than the forbidden band width of the barrier layer and larger than the forbidden band width of the quantum well layer. An example in which the forbidden band width of the impurity rare region is larger than the forbidden band width of the impurity added region will be described.

In this semiconductor laser device, the structure of the semiconductor laser device is the same as that of the second embodiment shown in FIG.

In the third embodiment, as in the second embodiment, the first light guide layer 204 is formed by the thermal history during the crystal growth.
In the second light guide layer 206, impurity diffusion occurs from the impurity added layer to the impurity non-added layer, and the band diagram near the active layer is as shown in FIG.

That is, the first light guide layer 204 is formed from the side of the n-first cladding layer 203 to the impurity added region 250 (having a layer thickness of 0. 1).
01 μm) and the impurity intermediate concentration region 251 (layer thickness 0.01
5 μm) and impurity rare region 252 (layer thickness 0.01 μm)
Divided into On the other hand, the second light guide layer 206 is p-second
From the side of the cladding layer 207, the impurity added region 260 (layer thickness 0.01 μm) and the impurity intermediate concentration region 261 (layer thickness 0.
015 μm) and the impurity concentration is divided into impurity rare regions 262 (layer thickness 0.01 μm). As described above, the impurity added region, the impurity intermediate concentration region, and the impurity rare region are formed by a simple process with good controllability by the thermal history during the crystal growth of the semiconductor layer.

Here, in the third embodiment, the impurity added region 250 of the first light guide layer 204 and the second light guide layer 2
06, the Al mixed crystal ratio of the impurity added region 260 is set to 0.2 or 0.3, and the quantum well layer 2 of the multiple quantum well active layer 205 is formed.
20 (x = 0) and the barrier layer 22
It is set smaller than the Al mixed crystal ratio of 1 (x = 0.5). That is, as shown in FIG. 7, the forbidden band width of the impurity added region 250 of the first light guide layer 204 and the forbidden band width of the impurity added region 260 of the second light guide layer 206 are larger than the forbidden band width of the quantum well layer 220. 221 is set smaller than the forbidden band width. On the other hand, the impurity rare region 2 of the first light guide layer 204
52 and impurity rare region 262 of second light guide layer 206
The Al mixed crystal ratio (x = 0.5) of the impurity added region 250 of the first light guide layer 204 and the Al mixed crystal ratio of the impurity added region 260 of the second light guide layer 206 (x = 0.2 or 0.5).
Set larger than 3). That is, as shown in FIG. 7, the forbidden band widths of the impurity rare region 252 of the first light guide layer 204 and the impurity rare region 262 of the second light guide layer 206 are set to be equal to those of the impurity added region 250 of the first light guide layer 204. The width is set to be larger than the forbidden band width of the impurity added region 260 of the two light guide layers 206. Thereby, the carriers are confined in the active layer in the impurity rare region, and the Al mixed crystal ratio of the impurity added region of the optical guide layer can be set smaller than in the second embodiment. Therefore, the impurity diffusion from the impurity added region to the active layer can be further reduced as compared with the second embodiment, which is more effective in preventing the characteristic deterioration.

Here, at least the impurity added region 25
The forbidden band widths of 0 and 260 may be set to be larger than the forbidden band width of the quantum well layer 220 and smaller than the forbidden band width of the barrier layer 221. The forbidden band widths of the impurity intermediate concentration regions 251 and 261 are shown in FIG. 7, the same forbidden band width as the impurity rare regions 252 and 262 may be used, or the same forbidden band width as the impurity added regions 250 and 260 may be used as shown in FIG. Alternatively, a forbidden band width may be set between the impurity rare region and the impurity added region.

The AlG shown in Embodiments 2 and 3 above
Since an aInP-based material is a material in which impurities are easily diffused as compared with an AlGaAs-based material, it is very effective to apply the present invention that can reduce impurity diffusion from an impurity-added region to an active layer.

(Embodiment 4) Embodiment 4 describes an example in which the present invention is applied to a light emitting diode element.

FIG. 9 is a sectional view of a semiconductor laser device according to the fourth embodiment.

This semiconductor laser device has a GaN buffer layer 302 and an n-GaN first layer on a sapphire substrate 301.
Cladding layer 303, non-doped single quantum well (SQW:
Single Quantum Well) Active Layer 30
5, Al _0.2 Ga _0.8 N second cladding layer 305 and p-G
An aN contact layer 306 is formed by lamination. n-first cladding layer 303, active layer 304, second cladding layer 3
05 and the contact layer 306 are the n-first cladding layer 30
3 is formed on a mesa stripe 313 partially exposed. An n-type electrode 320 is formed on the exposed portion of the n-first cladding layer 303, and a p-type electrode 321 is formed on the contact layer 306.

This semiconductor laser device can be manufactured, for example, as follows.

First, the MOCV is placed on the sapphire substrate 301.
GaN buffer layer 302 (layer thickness 0.05 μm)
m), n-GaN first cladding layer 303 (layer thickness 3 μm,
Dopant Si, carrier concentration 5 × 10 ¹⁸ cm ⁻³ ), non-doped single quantum well active layer 304, Al _0.2 Ga _0.8 N
Second cladding layer 305 and p-GaN contact layer 30
6 (layer thickness 0.2 μm, dopant Mg, carrier concentration 5
× 10 ¹⁷ cm ^-3 ).

Here, the single quantum well active layer 305 is a single Ga _0.2 In _0.8 P quantum well layer (having a thickness of 0.003 μm).
m) was grown. Then, the second cladding layer 305
From the active layer 304 side, an impurity-free layer (layer thickness 0.03 μm)
m) and an impurity added layer (layer thickness 0.07 μm, dopant M
g, and a carrier concentration of 5 × 10 ¹⁷ cm ⁻³ ).

The thermal history temperature (crystal growth temperature) during the MOCVD growth is 900 ° C. to 1100 ° C., whereby impurity diffusion from the impurity-added layer to the impurity-non-added layer occurs in the second cladding layer 305, and the active layer From the side 304, the impurity rare region 310 (layer thickness 0.01 μm), the impurity intermediate concentration region 311 (layer thickness 0.04 μm), and the impurity added region 3
12 (layer thickness 0.05 μm). Therefore, the impurity added region, the impurity intermediate concentration region, and the impurity rare region are formed by a simple process with good controllability by the thermal history during the crystal growth of the semiconductor layer.

Thereafter, a circular resist mask is formed on the surface, and the mesa stripe 313 is formed by dry etching.
Is formed, and an n-type electrode 320 and a p-type electrode 321 are formed on the exposed portion of the n-first cladding layer 303 and on the contact layer 306, respectively.

In the light emitting diode device of Embodiment 4 obtained in this way, the impurity rare region 310 is provided on the p-type cladding layer side. Since the diffusion coefficient of the p-type impurity is larger than that of the n-type impurity, the diffusion of the impurity (Mg) on the p-type cladding layer side into the active layer is controlled in the impurity rare region, thereby reducing the operating voltage and deteriorating the characteristics. Prevention can be achieved. Further, in this case, the characteristics can be optimized only by controlling the thickness of the impurity rare region on the p-type cladding layer side, so that there is an advantage that the design is easy.

When a forward voltage is applied between the n-type electrode 320 and the p-type electrode 321 to the light emitting diode element of the fourth embodiment, the emission wavelength is 0.45 μm and the operating current is 50
mA and an operating voltage of 4.5 V were obtained. In addition, since the diffusion of impurities from the second cladding layer to the active layer during energization can be suppressed, deterioration of device characteristics can be prevented. On the other hand, when impurities are added to the entire region of the second cladding layer, the operating voltage is 4.5 V, but the characteristics are deteriorated during energization. As described above, in the fourth embodiment, it is possible to prevent the characteristic deterioration without increasing the operating voltage.

In the InGaN-based material shown in this embodiment, the growth temperature is 100 times higher than the growth temperatures of AlGaAs-based materials and AlGaInP-based materials of 600 ° C. to 700 ° C.
Since the temperature is as high as 0 ° C. ± 100 ° C., the degree of impurity diffusion is large. Therefore, it is very effective to apply the present invention which can reduce impurity diffusion from the cladding layer to the active layer.

(Embodiment 5) In Embodiment 5, an example in which an impurity rare region is provided on the side of the p-type cladding layer and the n-type cladding layer adjacent to the active layer will be described.

FIG. 10 is a sectional view of a semiconductor laser device according to the fifth embodiment.

This semiconductor laser device has a GaN buffer layer 402 and a GaN first cladding layer 403, a non-doped single quantum well active layer 404 on a sapphire substrate 401.
Al _0.2 Ga _0.8 N second cladding layer 405 and p-GaN
A contact layer 406 is formed by lamination. n-first cladding layer 403, active layer 404, second cladding layer 405
The contact layer 406 is formed in a mesa stripe 413 that partially exposes the first cladding layer 403. The n-type electrode 4 is formed on the exposed portion of the first cladding layer 403.
20 is formed, and the p-type electrode 4 is formed on the contact layer 406.
21 are formed.

This semiconductor laser device can be manufactured, for example, as follows.

First, the MOCV is placed on the sapphire substrate 401.
GaN buffer layer 402 (layer thickness 0.05 μ
m), a GaN first cladding layer 403, a non-doped single quantum well active layer 404, an Al _0.2 Ga _0.8 N second cladding layer 405, and a p-GaN contact layer 406 (layer thickness 0.2
μm, dopant Mg, carrier concentration 5 × 10 ¹⁷ c
m ⁻³ ).

Here, the single quantum well active layer 405 is a single Ga _0.2 In _0.8 P quantum well layer (having a thickness of 0.003 μm).
m) was grown. Then, the first cladding layer 403 is
From the active layer 404 side, an impurity-free layer (layer thickness 0.03 μm)
m) and an impurity-added layer (layer thickness 2.97 μm, dopant S
i, and a carrier concentration of 5 × 10 ¹⁸ cm ⁻³ ).
The second cladding layer 405 includes an impurity-free layer (layer thickness 0.05 μm) and an impurity-added layer (layer thickness 0.05 μm, dopant Mg, carrier concentration 5) from the active layer 404 side.
× 10 ¹⁷ cm ^-3 ).

The thermal hysteresis temperature (crystal growth temperature) during the MOCVD growth is 900 ° C. to 1100 ° C., whereby impurity diffusion from the impurity added layer to the impurity non-added layer occurs in the first cladding layer 403, and the active layer From the 404 side, the impurity rare region 410 (layer thickness 0.01 μm), the impurity intermediate concentration region 411 (layer thickness 0.02 μm), and the impurity added region 4
12 (layer thickness 2.97 μm). On the other hand, in the second cladding layer 405, impurity diffusion occurs from the impurity added layer to the impurity non-added layer, and the impurity rare region 413 (layer thickness 0.02 μm) and the impurity intermediate concentration region 414 (layer thickness 0. 04 μm) and the impurity added region 415
(0.04 μm in thickness). Therefore, the impurity added region, the impurity intermediate concentration region, and the impurity rare region are formed by a simple process with good controllability by the thermal history during the crystal growth of the semiconductor layer.

Thereafter, the first cladding layer 303 is partially exposed by etching, and an n-type electrode 420 and a p-type electrode 421 are formed on the exposed portion and on the contact layer 406, respectively.

As described above, in the light emitting diode element of the fifth embodiment, the layer thickness of the impurity-free layer is larger on the p-type cladding layer side than on the n-type cladding layer side, and the n-type Since the diffusion coefficient is larger than that of the type impurity, the value of the impurity rare region can be adjusted to a desired thickness. Accordingly, the thickness of the impurity rare region can be adjusted according to the diffusion coefficient, and thus there is an advantage that the degree of freedom in design for realizing a low operating voltage and preventing deterioration of characteristics during energization is improved.

When a forward voltage is applied between the n-type electrode 420 and the p-type electrode 421 to the light emitting diode element of the fifth embodiment, the emission wavelength is 0.45 μm and the operating current is 50
mA and an operating voltage of 4.5 V were obtained.

The present invention is not limited to the above embodiment, but includes the structure of the quantum well active layer (number of quantum wells, mixed crystal ratio and layer thickness), layer thickness of each layer, Al mixed crystal ratio, dopant species. The present invention is also applicable to a semiconductor light emitting device having a carrier concentration different from that described above.

The growth method is not limited to the MOCVD method, but may be an MBE (molecular beam epitaxy) method, an LPE (liquid crystal epitaxy) method, a MOMBE method, an ALE (atomic beam epitaxy) method, or the like. Although the impurity intermediate concentration region is formed by impurity diffusion from the impurity added region to the impurity non-added region, the semiconductor layer may be grown separately. Further, in order to control diffusion, the growth temperature of the impurity intermediate concentration region is set to about 50 ° C.
The temperature may be lowered by about 0 ° C.

Further, the present invention can be applied to the case where other material systems than those described above are used.

[0118]

As described above in detail, in the case of the present invention, the diffusion of impurities from the impurity added region to the active layer during energization is suppressed by the impurity rare region provided in the cladding layer or the light guide layer. Therefore, an increase in operating current can be suppressed, deterioration of device characteristics can be prevented, and a highly reliable semiconductor light emitting device can be obtained. At the same time, the resistance of the entire light guide layer can be reduced by the impurity added region, and the diffusion potential between the light guide layer and the cladding layer can be reduced, so that the operating voltage can be reduced.

According to the fourth aspect of the present invention, the impurity is diffused from the impurity added region to the impurity rare region during energization by the impurity intermediate concentration region provided between the impurity rare region and the impurity added region. And the reliability of the element can be further improved.

In particular, in the case of claim 5 of the present invention,
The active layer is formed of a quantum well layer, and the layer structure is changed even by slight impurity diffusion during energization, and the characteristics are easily deteriorated. Therefore, the reliability of the device can be greatly improved.

According to the sixth and seventh aspects of the present invention, the operating voltage can be made effective by setting the impurity concentration in the p-type and n-type impurity-added regions of the light guide layer to respective predetermined ranges. And the characteristic degradation due to non-radiative recombination of carriers in the impurity-added region can be effectively suppressed.

According to the eighth aspect of the present invention, the impurity carrier concentration in the impurity-rare region is set to be 1/5 or less of the impurity carrier concentration in the impurity-added region. Diffusion can be effectively suppressed.

According to the ninth aspect of the present invention, by setting the thickness of the impurity rare region to 3 nm or more and 10 nm or less, it is possible to effectively suppress the characteristic deterioration and effectively reduce the operating voltage.

According to the tenth aspect of the present invention, by providing the impurity rare region at least on the side of the p-type cladding layer or the p-type light guide layer, the element design can be facilitated and the production yield can be improved. it can.

In the case of the eleventh aspect of the present invention, the thickness of the impurity rare region provided in the p-type clad layer or the p-type light guide layer is set in the n-type clad layer or the n-type light guide layer. By making the thickness greater than the thickness of the device, it is possible to improve the controllability of the element design and improve the production yield.

According to the twelfth aspect of the present invention, by setting the thickness of the intermediate impurity concentration region to 3 nm or more and 10 nm or less, it is possible to effectively diffuse the impurity from the impurity added region to the impurity rare region during energization. , The reliability of the device can be improved, and the carrier injection from the impurity added region to the active layer is not hindered, so that the operating voltage can be reduced.

According to a thirteenth aspect of the present invention, when the active layer comprises a multiple quantum well layer, at least the forbidden band width of the impurity-added region is smaller than the forbidden band width of the barrier layer, and By making the width larger than the forbidden band width of the well layer, the Al mixed crystal ratio can be reduced to further reduce impurity diffusion from the impurity added region to the active layer. In this case, since the thickness of the impurity rare region can be set to be thin, the operating voltage can be sufficiently reduced.

According to the fourteenth aspect of the present invention, by making the forbidden band width of the impurity-added region smaller than the forbidden band width of the impurity-rare region, the Al mixed crystal ratio of the impurity-added region can be further reduced. Therefore, the reliability of the device can be further improved.

According to the fifteenth aspect of the present invention, in particular, an AlGaInP-based material or In
Even in a GaN-based material, diffusion of impurities can be prevented, and the reliability of the device can be improved.

According to the sixteenth aspect of the present invention, the impurity is diffused from the impurity-added layer to the impurity-free layer by the thermal history during the crystal growth to form the impurity intermediate concentration region. The concentration region and the impurity rare region can be manufactured by a simple manufacturing process with good controllability. Therefore, it is possible to provide a semiconductor light emitting device with high reliability and low operating voltage at low cost.

According to the seventeenth aspect of the present invention, the thickness of the non-doped layer provided in the p-type cladding layer or the p-type light guide layer forming portion is set to the n-type clad layer or the n-type light guide layer. By making the thickness of the rare-earth region larger than that provided in the layer forming portion, the thickness of the impurity rare region can be controlled to a desired thickness with good controllability. Therefore, the controllability with respect to the element design can be improved, and the yield can be further improved.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a configuration of a semiconductor laser device according to a first embodiment.

FIG. 2 is a diagram showing a band diagram and a carrier concentration distribution near an active layer in the semiconductor laser device of the first embodiment.

FIG. 3 is a graph showing a relationship between a carrier concentration of an impurity-added region of a second light guide layer and an operating voltage in the semiconductor laser device of the first embodiment.

FIG. 4 is a graph showing a relationship between a carrier concentration of an impurity-added region of a first optical guide layer and an operating voltage in the semiconductor laser device of the first embodiment.

FIG. 5 is a cross-sectional view illustrating a configuration of a semiconductor laser device according to a second embodiment.

FIG. 6 is a diagram showing a band diagram in the vicinity of an active layer in the semiconductor laser device according to the second embodiment.

FIG. 7 is a view showing a band diagram in the vicinity of an active layer in the semiconductor laser device of Embodiment 3;

FIG. 8 is a diagram showing a band diagram in the vicinity of an active layer in another semiconductor laser device according to the third embodiment.

FIG. 9 is a cross-sectional view illustrating a configuration of a light emitting diode element according to a fourth embodiment.

FIG. 10 is a cross-sectional view illustrating a configuration of a light emitting diode element according to a fifth embodiment.

FIG. 11 is a diagram showing a band diagram near an active layer in a conventional semiconductor laser device.

[Explanation of symbols]

101, 201, 301, 401 Substrate 102, 202, 302, 402 Buffer layer 103, 203, 303, 403 First cladding layer 104, 204 First light guide layer 105, 205, 304, 404 Quantum well active layer 106, 206 Second light guide layer 107, 207, 305, 405 Second clad layer 108 Etch stop layer 109 Third clad layer 110, 208 Cap layer 111, 210 Current light confinement layer 112 Current blocking layer 113 Flattening layer 114, 306, 406 Contact layers 150, 212, 321, 421 P-type electrodes 151, 211, 320, 420 N-type electrodes 120, 220 Quantum well layers 121, 221 Barrier layers 130, 140, 230, 240, 250, 260, 3
12, 412, 415 impurity added regions 131, 141, 231, 241, 251, 261, 3
11, 411, 414 Intermediate impurity concentration regions 132, 142, 232, 242, 252, 262, 3
10, 410, 413 impurity rare region

Claims (17)

[Claims] 1. A semiconductor light emitting device having an active layer and cladding layers provided above and below the active layer, wherein at least one of the cladding layers has an impurity rare region and an impurity added region, A semiconductor light emitting device in which a region is arranged on a side closer to the active layer. 2. A semiconductor light emitting device having an active layer and light guide layers provided above and below the active layer, wherein at least one of the light guide layers has an impurity rare region and an impurity added region. A semiconductor light emitting device in which an impurity rare region is arranged on a side closer to the active layer. 3. A semiconductor light emitting device having an active layer and a light guide layer provided on one of upper and lower sides of the active layer, wherein the light guide layer has an impurity rare region and an impurity added region, A semiconductor light emitting device in which a rare region is disposed on a side closer to the active layer. 4. The semiconductor light emitting device according to claim 1, further comprising an impurity intermediate concentration region between said impurity rare region and said impurity added region. 5. The semiconductor light emitting device according to claim 1, wherein said active layer comprises a quantum well layer. 6. The impurity in the impurity-added region of the light guide layer is p-type, and the carrier concentration of the impurity is 4 × 10 ¹⁷ cm ⁻³ or more and 1.2 × 10 ¹⁸ cm ⁻³ or less. The semiconductor light emitting device according to claim 2. 7. An impurity in the impurity-doped region of the light guide layer is n-type, and a carrier concentration of the impurity is 2 × 10 ¹⁷ cm ⁻³ or more and 1 × 10 ¹⁸ cm ⁻³ or less. A semiconductor light emitting device according to claim 5. 8. The semiconductor light emitting device according to claim 1, wherein an impurity concentration in said impurity rare region is 1/5 or less of an impurity concentration in said impurity added region. 9. The semiconductor light emitting device according to claim 1, wherein said impurity rare region has a thickness of 3 nm or more and 10 nm or less. 10. The semiconductor device according to claim 1, wherein the impurity rare region has at least p
The semiconductor light emitting device according to claim 1, wherein the semiconductor light emitting device is provided on a mold cladding layer or a p-type light guide layer. 11. In the impurity-rare region, the thickness provided in the p-type cladding layer or the p-type light guide layer is greater than the thickness provided in the n-type cladding layer or the n-type light guide layer. The semiconductor light emitting device according to claim 1. 12. The impurity intermediate concentration region has a thickness of 3n.
The semiconductor light emitting device according to any one of claims 4 to 11, wherein the semiconductor light emitting device has a length of m to 10 nm. 13. The active layer includes a multiple quantum well layer including a plurality of quantum well layers and a barrier layer sandwiched between the plurality of quantum well layers, and includes the impurity rare region and the impurity added region. 6. The semiconductor light emitting device according to claim 5, wherein a forbidden band width of at least the impurity added region in the light guide layer is smaller than a forbidden band width of the barrier layer and larger than a forbidden band width of the quantum well layer. element. 14. The semiconductor light emitting device according to claim 13, wherein in the light guide layer, a forbidden band width of the impurity added region is smaller than a forbidden band width of the impurity rare region. 15. The method according to claim 15, wherein the cladding layer or the light guide layer is made of an AlGaAs-based material, an AlGaInP-based material, or InG.
15. The semiconductor light emitting device according to claim 1, wherein the semiconductor light emitting device is made of an aN-based material. 16. The method for manufacturing a semiconductor light emitting device according to claim 4, wherein an impurity-added layer and an impurity-free layer are grown, and the impurity-added layer is removed from the impurity-added layer by a thermal history during crystal growth. A method for manufacturing a semiconductor light emitting device, wherein an impurity is diffused into the impurity intermediate concentration region. 17. The thickness of the impurity-free layer provided in the p-type cladding layer or the p-type light guide layer forming portion is larger than the thickness of the impurity-free layer provided in the n-type cladding layer or the n-type light guide layer forming portion. The method for manufacturing a semiconductor light emitting device according to claim 16, wherein the thickness is also increased.