JPH1127965A - Drive device for capacitive loads - Google Patents

Abstract

(57) [Summary] [PROBLEMS] Digital I commonly used for logic circuits, etc.
To provide a capacitive load driving device capable of being controlled by a switching signal of C. A high-voltage driving voltage is supplied to a capacitive load via a mutually complementary first switching element and a second switching element, and the first switching element performs switching control by a third switching element. The second switching element is switching-controlled by a fourth switching element complementary to the third switching element,
The switching of the third switching element and the fourth switching element is controlled by the signal level of the digital IC.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a driving device for a capacitive load, and more particularly to a driving device for driving a capacitive load such as a piezoelectric element in a vibration actuator.

[0002]

2. Description of the Related Art For example, a piezoelectric element is joined to the surface of an elastic body, and a drive voltage is applied to the piezoelectric element to generate a plurality of vibration modes in the elastic body in harmony. There is known a vibration actuator that generates an elliptical motion and drives a relative motion member that is brought into pressure contact with the elastic body. In this type of vibration actuator, one using an ultrasonic vibration region is called an ultrasonic vibration actuator or an ultrasonic motor.

When driving the above-mentioned vibration actuator,
In general, a driving ultrasonic power source supplies a low-potential DC power source by performing a switching operation by a semiconductor and boosting a high voltage by a boosting transformer. However, since the switching transformer is an open loop and the switching transformer has an impedance due to windings, a current change due to a load fluctuation of the vibration actuator induces a change in output voltage, resulting in a speed fluctuation, a torque fluctuation, and the like. This may cause a decrease in control performance.

Further, as shown in FIG. 7, there is a capacitive load driving device that directly controls a high voltage by a semiconductor element (for example,
JP-A-9-9650). The capacitive load driving device shown in FIG. 7 causes the differential amplifier 501 to output a control signal Ve that fluctuates up and down around 0 V, thereby performing a charge / discharge operation of the capacitive load 502 that is a piezoelectric element.

The operation will be briefly described.
1 is connected to the ground terminal 504 by +
When the voltage becomes about 0.6 V or more, a base current starts to flow between the base and the emitter of the NPN transistor 503, and a collector current flows accordingly. This collector current is PNP
The current becomes the base current of the transistor 505, the collector current of the PNP transistor 505 flows according to the base current, and the driving voltage is supplied from the positive power supply 506 to the capacitive load 502. At this time, the control signal Ve is also applied to the PNP transistor 507. However, since the control signal Ve is about 0.6 V or more, the base current does not flow and the PNP transistor 507 does not operate. If PNP transistor 507 does not operate, NP
No base current flows through the N transistor 508, and the NPN transistor 508 is off.

Next, the control signal V from the differential amplifier 501 is
When e becomes less than about -0.6 V with respect to the ground terminal 504, a base current flows between the emitter and the base of the PNP transistor 507, and a collector current flows accordingly. This collector current becomes the base current of the NPN transistor 508, and the collector current flows through the NPN transistor 508 in accordance with the base current, and the potential charged in the capacitive load 502 is discharged toward the negative power supply 509 and in the opposite direction. Charged. That is, the capacitive load 50
2 is supplied with a negative drive voltage from the negative power supply 509. At this time, although the control signal Ve is also applied to the NPN transistor 503, the base current does not flow and the NPN transistor 503 does not operate because the control signal Ve is about -0.6 V or less. If the NPN transistor 503 does not operate, the PNP
No base current flows through the transistor 505, and the PNP transistor 505 is off.

In this manner, the low-potential differential amplifier 50
1, the power supply 506 is applied to the capacitive load 502,
509 can be supplied. Although it depends on the breakdown voltage of the transistor and the like, a driving voltage of several hundred volts can be controlled. Therefore, when this type of capacitive load driving device is used for a vibration actuator, it is not necessary to use the above-mentioned step-up transformer, and the above-mentioned problem caused by the step-up transformer can be solved.

[0008]

However, the drive voltage applied to the piezoelectric element, which is a capacitive load in a vibration actuator, is a periodic signal having a constant frequency. Therefore,
In order to control the periodic signal, it is convenient to use a digital IC that operates with a 5V power supply or the like used in a general logic circuit. However, in the circuit of FIG. 7, it is necessary to swing the control signal to ±, and the above-described general digital IC
Difficult to use. Further, the circuit of FIG. 7 utilizes the characteristics of each transistor in the non-saturation region, and cannot effectively perform switching control by a digital signal using a digital IC.

It is an object of the present invention to provide a capacitive load driving device which can be controlled by a switching signal of a digital IC generally used for a logic circuit or the like.

[0010]

The present invention will be described with reference to FIG. 5 showing an embodiment. In order to achieve the above object, a first aspect of the present invention provides a power supply system comprising: a first power supply + 30V and a second power supply -30V;
And the second switching elements TR1, TR2 and the first
A third switching element TR3 that opens and closes the first switching element TR3, and a fourth switching element TR4 that is complementary to the third switching element TR3 and opens and closes the second switching element TR2. The second switching element TR3 is applied to a capacitive load driving device that connects a capacitive load to the connection point 23 between the two switching elements TR1 and TR2, and the third switching element TR3 is connected between the first power supply + 30V and the second power supply −30V. The fourth switching element TR4 has a potential and is connected to a third power supply GND serving as a reference for its own switching.
And the third and fourth switching elements TR3 and TR4 are connected to a third power supply GND and a fourth power supply GND. It is opened and closed complementarily by a switching signal having a signal level based on the potential of the power supply + 5V. The invention according to claim 2 is applied to a capacitive load driving device that charges and discharges a capacitive load according to a switching signal having a high signal level and a low signal level.
A first PNP transistor TR1 having an emitter connected to the power supply + 30V and a collector connected to the capacitive load;
The emitter is connected to -30V power supply and the collector is connected to the first P.
A first NPN transistor TR2 connected to the collector of the NP transistor TR1 and the capacitive load;
A second NPN transistor TR3 having a collector connected to the base of the NP transistor TR1, an emitter connected to the third power supply GND, and a switching signal input to a first terminal 21 connected to the base; a first NPN transistor The collector is connected to the base of TR2, and the fourth power supply + 5V
Terminal 22 connected to the emitter and connected to the base
A first PNP transistor TR4, to which a switching signal is input, and a first resistance element defining a base current of a second NPN transistor TR3 inserted between the first terminal 21 and the third power supply GND. R3 and the second terminal 2
2nd PNP inserted between 2nd and 4th power supplies + 5V
A second resistor element R6 for defining a base current of the transistor TR4 and a first PNP transistor inserted between the base of the first PNP transistor TR1 and the third power supply GND.
A third resistor R4 defining the base current of the transistor TR1, and a third resistor R4 defining the base current of the first NPN transistor TR2 inserted between the base of the first NPN transistor TR2 and the fourth power supply + 5V. 4, the third power supply GND is a power supply having a potential serving as a reference for the low signal level of the switching signal, and is lower than the potential of the first power supply +30 V, and the potential of the fourth power supply +5 V The potential is a power source of a potential serving as a reference for the high signal level of the switching signal, and is set to be higher than the potential of the second power source -30V. According to a third aspect of the present invention, in the capacitive load device according to the first or second aspect, the fourth power supply + 5V is a positive potential side of a logic circuit power supply used for generating a switching signal. Power supply G
ND is the ground potential side of the logic circuit power supply.

In the section of the means for solving the above-mentioned problems, the description is made in correspondence with FIG. 5 of the embodiment for easy understanding, but the present invention is not limited to the embodiment.

[0012]

FIG. 1 is a configuration diagram of an embodiment of a driving device for driving a vibration actuator 1. FIG. 2 is a perspective view illustrating a schematic configuration of the vibration actuator 1.

In FIG. 2, the vibration actuator 1 is
Two piezoelectric elements 102 and 103 are adhesively bonded to the surface of the elastic body 101, and by applying drive voltages having different phases to the piezoelectric elements 102 and 103, a plurality of vibration modes are generated harmoniously in the elastic body 101. , Driving force take-out unit 1
Physical elliptical motion is generated in the driving force extraction parts 104 and 105, and the driving force extracting parts 104 and 105 are driven by relatively moving a relative motion member 106 which is brought into pressure contact with an urging member (not shown). 107 and 108 are vibration monitoring piezoelectric elements that monitor the vibration state of the elastic body 101. Since the above-mentioned operation principle is publicly known, a detailed description thereof will be omitted (for example, see Japanese Patent Application Laid-Open No. 8-184768).

A driving device for generating a driving voltage to be applied to the two piezoelectric elements 102 and 103 of the vibration actuator 1 will be described below in detail with reference to FIGS.

FIG. 1 is a configuration diagram showing a configuration of a driving device according to a first embodiment of the present invention. This drive is
An oscillation circuit 2 for defining the frequency of the drive voltage, a phase shift circuit 3 for generating different phase signals for applying signals having different phases to the two piezoelectric elements 102 and 103, and delay circuits 4A and 4B; Switching circuits 5A and 5B using semiconductor elements are provided. The signal having a constant frequency generated by the oscillation circuit 2 is π / 2
These are two signals having different phases. These signals are input to the delay circuits 4A and 4B, respectively, and after being delayed so that the ON states of the output transistors in the switching circuits 5A and 5B do not overlap, the signals are input to the switching circuits 5A and 5B. Switching circuit 5A, 5B
Generates a drive voltage having a maximum value of about ± 30 V by operating an internal semiconductor element based on an input signal.

FIG. 3 is a timing chart for explaining how the oscillation circuit 2 and the phase shift circuit 3 generate two signals having different π / 2 phases. A pulse signal of a constant frequency output from the oscillation circuit 2 is input as a clock signal to two D-type flip-flops 9 and 10 constituting the phase shift circuit 3. The two D-type flip-flops 9 and 10 are configured such that their outputs Q and NQ and the data input terminal D are connected at a certain distance, and generate the signals of Q1 and Q2 in FIG. That is, the signals Q1 and Q2
Both constitute one cycle with four clocks, and the signal Q1 and the signal Q2 are shifted in phase by exactly １ ／ cycle, that is, π / 2. The signal Q1 is sent to the delay circuit 4A, and the signal Q2 is sent to the XO
The signal is input to the delay circuit 4B via the R gate 6.

The delay circuit 4A and the delay circuit 4B
This is a circuit having the same configuration, and is a circuit for giving a delay to each signal in order to reliably prevent a state where the two output transistors of the switching circuits 5A and 5B described later are switched on and off at the same time. FIG. 4 is a timing chart for explaining the operation of the delay circuits 4A and 4B. Hereinafter, the operation of the delay circuit 4A for the signal Q1 generated by the phase shift circuit 3 will be described with reference to FIGS. The concept of the signal Q2 and the delay circuit 4B is the same, and the description is omitted. Signal D / S input to delay circuits 4A and 4B
Is a signal for determining whether the present driving device is to be in the drive state or the stop state. In this description, it is assumed that the drive state, that is, the HIGH signal is always input. In order to stop driving by the driving device, the signal D / S may be set to LOW.

A 3-input AND gate 7 supplies the signal D
/ S, the signal Q1, and the signal QD1 having a delay of time t defined by the time constant of the resistor R1 and the capacitor C1 with respect to the signal Q1 are input. The signal D / S is always HIGH, and the AND of the signal Q1 and the signal QD1 is
Is generated. In the NAND gate 8, the signal QN obtained by adding the signal D / S, the inverted signal QN1 of the signal Q1, and the signal QN1 to the signal QN having a time t defined by the time constant of the resistor R2 and the capacitor C2 in the same manner as described above.
D1 is input. Resistors R1 and R2 and capacitor C
1 and C2 may be the same value. The signal D / S is always high (HI
GH), and a signal S2 in which the signal QN1 and the signal QND1 are NANDed is generated.

As described above, as shown in FIG. 4, when the signal S1 falls, when the signal S2 falls, and when the signal S2
There is an interval of time t at both the rising edge of the signal S1 and the rising edge of the signal S1, and the high (HIGH) signal of the signal S1 and the low (LOW) signal of the signal S2 are generated so as not to overlap with each other. Signal S1 and signal S2 are input to switching circuit 5A.

FIG. 5 is a principle diagram of the switching circuit 5A. The switching circuit 5B has the same configuration. In FIG. 5, the emitter terminal of the PNP transistor TR1 is +3
0V power supply, the emitter terminal of NPN transistor TR2 is -30V power supply, the emitter terminal of NPN transistor TR3 is GND (ground), and PNP transistor TR
The 4 emitter terminals are respectively connected to a + 5V power supply via diodes. The flip-flops and gates used in the phase shift circuit 3 and the delay circuit 4A are +5 used in a general logic circuit.
It is a digital IC that operates on a V power supply, and is, for example, a TTL or CMOS device. Therefore, the HIGH signal has a potential of about 4 V, and the LOW signal has a potential of 0.5 V.
It has a potential before and after.

A signal S1 is supplied from a delay circuit 4A to a terminal 21.
Is input, a base current defined by the resistor R3 flows between the base and the emitter of the NPN transistor TR3, and the NPN transistor TR3 is turned on. When the NPN transistor TR3 turns on, the PNP
A base current defined by the resistor R4 flows between the emitter and the base of the transistor TR1, and the PNP transistor TR1
Turns on. When the PNP transistor TR1 is turned on, a voltage of about +30 V is supplied to the terminal 23.

The signal S1 input to the terminal 21 is high (HI).
GH), the signal S2 input to the terminal 22 also becomes a HIGH signal. PNP transistor TR
When a high (HIGH) signal is input to the base terminal of P.4, it is pulled up to a + 5V power supply by the resistor R5.
No base current flows between the emitter and the base of the NP transistor TR4, and the PNP transistor TR4 is turned off. When the PNP transistor TR4 is off, NP
No base current flows between the base and the emitter of the N transistor TR2, and the NPN transistor TR2 is turned off.
Therefore, the PNP transistor TR1 is turned on and the NPN transistor TR2 is turned off.
A voltage of 0V is supplied.

Next, a low (LO) signal S1 is applied to the terminal 21.
W) When the signal is input, a sufficient base current does not flow between the base and the emitter of the NPN transistor TR3 to turn on, and the NPN transistor TR3 is in the off state. When the NPN transistor TR3 is off, no base current flows between the emitter and the base of the PNP transistor TR1, and the PNP transistor TR1 turns off.

When a low signal is input to the signal S1, a low signal is input to the signal S2. When a LOW signal is input to the base terminal of the PNP transistor TR4, a base current defined by the resistor R6 flows between the emitter and the base of the PNP transistor TR4, and the PNP transistor TR4 is turned on. When the PNP transistor TR4 turns on, a base current defined by the resistor R7 flows between the base and the emitter of the NPN transistor TR2, and the NPN transistor TR2
Is turned on. When the NPN transistor TR2 is turned on, the terminal 23 becomes conductive with a -30V power supply.

Accordingly, since the PNP transistor TR1 is turned off and the NPN transistor TR2 is turned on, the terminal 23 becomes conductive with the -30V power supply, and a voltage of about -30V is supplied.

As described above, the high / low (LO) level of the switching signal having an amplitude of 5 V or less is obtained.
W) It is possible to supply a high driving voltage that is switched at about ± 30 V to the terminal 23 by the signal. In the above, when the PNP transistor TR1 is on, N
The PN transistor TR2 is off, and the NPN transistor TR2 is on when the PNP transistor TR1 is off, but both transistors are off for the time t in FIG. Therefore, a current that passes through both transistors does not flow excessively when both transistors are switched on and off, so that unnecessary power is not consumed, and excessive current may destroy elements such as transistors or reduce reliability. I do not even do.

The switching drive voltage of about ± 30 V generated as described above is supplied to one piezoelectric element of the vibration actuator 1 from the switching circuit 5A as an A-phase signal in FIG. The phase signal is supplied to another piezoelectric element of the vibration actuator 1 as a B-phase signal having a phase shifted by π / 2. The signal R / L in FIG. 1 is a signal supplied from a control circuit (not shown). The signal R / L indicates whether the driving direction of the vibration actuator is rightward or leftward (right or left rotation in the case of a rotary vibration actuator). It is specified. That is, whether or not the signal Q2 in FIG. 3 is inverted is determined depending on whether the signal R / L is high (HIGH) or low (LOW), whereby the signal Q2 input to the delay circuit 4B is compared with the signal Q1. π / 2 phase delayed signal or π /
Decide whether to use a signal with two phases advanced. Thereby, the driving direction of the vibration actuator 1 can be controlled.

FIG. 6 is a circuit diagram showing the principle diagram of FIG. 5 in a form close to an actual applied circuit. The PNP transistor TR1 and the NPN transistor TR2 in FIG. 5 are respectively composed of two-stage PNP transistors TR5 and TR6 and NPN transistors TR7 and TR8.
The operation principle is the same as that of FIG.

In this way, it is possible to supply a high-potential drive voltage to a capacitive load such as a piezoelectric element without using a step-up transformer for the output, and to generally transmit a control signal to a logic circuit or the like. It can be easily generated and controlled by the digital IC used.

In the above embodiment, the embodiment of the bipolar transistor such as the NPN transistor and the PNP transistor has been described. However, the present invention is not limited to these. These bipolar transistors can be replaced with FET transistors, IGBTs and other switching elements. Also, a TTL or CMOS level digital IC operating at +5 V has been described as a circuit for controlling a switching signal; however, the invention is not limited to this. The present invention can also be applied to a digital IC operating at +3 V or a digital IC operating at another power source. Further, the control may be performed by a microprocessor, a gate array, or another LSI. Furthermore, although the description has been given of the case where the drive voltage is ± 30 V, it is not necessary to be limited to this value. Although it depends on the withstand voltage of the transistor or the like to be used, the present invention can be applied to a driving voltage of ± 100 V or vice versa. Further, the drive voltage does not necessarily have to have a plus / minus symmetrical value, and the power supply may have different values on the plus side and the minus side.

[0031]

Since the present invention is configured as described above, it has the following effects. According to the first aspect of the present invention, the switching elements are opened and closed in a complementary manner by a switching signal having a signal level based on the potentials of the third power supply and the fourth power supply. A high-potential drive voltage can be supplied to the connected capacitive load, and the control signal can be easily generated and controlled by a digital IC or the like generally used for a logic circuit or the like. Claim 2
According to the invention, the same effect as that of the first aspect is obtained by using a bipolar transistor as the switching element. According to the third aspect of the present invention, a power supply for a logic circuit used for generating a switching signal can be effectively used.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an embodiment of a driving device that drives a vibration actuator.

FIG. 2 is a perspective view illustrating a schematic configuration of the vibration actuator of FIG. 1;

FIG. 3 is a timing chart illustrating how two signals having different phases of π / 2 are generated in an oscillation circuit and a phase shift circuit.

FIG. 4 is a timing chart illustrating the operation of a delay circuit.

FIG. 5 is a principle diagram of a switching circuit.

FIG. 6 is a circuit diagram showing the principle diagram of FIG. 5 in a form close to an actual applied circuit.

FIG. 7 is a prior art diagram of a capacitive load driving device that directly controls a high voltage by a semiconductor.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Vibration actuator 2 Oscillation circuit 3 Phase shift circuit 4A, 4B Delay circuit 5A, 5B switching circuit 6 XOR gate 7 AND gate 8 NAND gate 9, 10 D type flip-flop C1, C2 Capacitor R1-R7 Resistance TR1, TR4, TR5, TR6 PNP transistor TR2, TR3, TR7, TR8 NPN transistor 101 Elastic body 102, 103 Piezoelectric element 104, 105 Driving force extraction unit 106 Relative motion member 107, 108 Vibration monitoring piezoelectric element

Claims (3)

[Claims] A first switching element connected in series between a first power supply and a second power supply; and a third switching element for opening and closing the first switching element. And a fourth switching element, which is complementary to the third switching element and opens and closes the second switching element, wherein a capacitive load is connected to a connection point between the first and second switching elements. In the capacitive load driving device, the third switching element includes a first power supply and a second power supply.
And a fourth power supply element connected to a third power supply that is a reference for its own switching. The fourth switching element has a potential between the first power supply and the second power supply.
The third and fourth switching elements are connected to a fourth power supply, which is a reference for own switching, and have a potential between the third power supply and the fourth power supply. A capacitive load driving device that is opened and closed complementarily by a switching signal having a signal level based on the switching signal. 2. A capacitive load driving device for charging and discharging a capacitive load in response to a switching signal having a high signal level and a low signal level, wherein an emitter is connected to a first power supply, and the capacitive load is connected to the capacitive load. A first PNP transistor connecting a collector, a first NPN transistor connecting an emitter to a second power supply, and connecting a collector to a collector and a capacitive load of the first PNP transistor; and the first PNP transistor. A second NPN transistor having a collector connected to the base of the transistor, an emitter connected to the third power supply, and a switching signal input to a first terminal connected to the base; a base of the first NPN transistor; A switching signal is input to a second terminal connected to a collector, a emitter connected to a fourth power supply, and a second terminal connected to the base. A second PNP transistor, a first resistor element that defines a base current of the second NPN transistor inserted between the first terminal and the third power supply, and a second terminal. A second resistor element that defines a base current of the second PNP transistor inserted between the third PNP transistor and the fourth power supply; and a second resistance element between the base of the first PNP transistor and the third power supply. A third resistance element inserted to define a base current of the first PNP transistor; and a third resistance element inserted between the base of the first NPN transistor and the fourth power supply, and A fourth resistance element for defining a base current of the transistor, wherein the potential of the third power supply is a power supply of a potential serving as a reference for a low signal level of a switching signal, and is higher than the potential of the first power supply. Low, the potential of the fourth power supply, a capacitive load driving apparatus characterized by higher than the high signal level of a power source serving as a reference potential and the potential of the second power supply switching signal. 3. The capacitive load device according to claim 1, wherein the fourth power supply is a positive potential side of a power supply for a logic circuit used for generating a switching signal, and the third power supply. Is a ground potential side of the power supply for the logic circuit.