JPH11282761A - Microcomputer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To save data in a nonvolatile memory which has a long wire time and are electrically erasable en bloc by writing data that is the same as data in the nonvolatile memory whenever the data is written to a RAM or a register. SOLUTION: An address signal AD4 for a nonvolatile memory 2 is inputted to an address controlling part 2b of the memory 2 from a CPU 1 through selectors 12 and 13 in response to writing data to a RAM 5 and the address of the memory 2 is designated. And, after the data of the designated address are erased, input data DA1 are inputted to a data inputting part 2d through selectors 17 and 18. And, a write signal WR2 is inputted to a read/write controlling part 9a through an OR gate 10, write control of the data is performed and data that are the same as the data written in the RAM 5 are stored in a specified address area of the memory 2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer capable of saving data in an emergency such as power-off.

[0002]

2. Description of the Related Art Generally, as shown in FIG. 2, a microcomputer includes a mask ROM in which at least an operation control program is stored, a program counter PC for performing address control for reading a ROM program, and data in the mask ROM. An instruction decoder that decodes the program instruction into a program instruction is built in. further,
The microcomputer also includes a RAM and a register for storing data obtained as a result of the operation.

[0003]

By the way, when the power supply voltage VDD of the microcomputer is cut off, for example, an EPRO is used so that data in the RAM and the register is not lost.
The data is stored in a nonvolatile memory such as M or EEPROM. Conventionally, the power supply voltage V of the microcomputer
Since a capacitor is connected to the external terminal of DD, the power supply voltage VDD gradually decreases even if the power is cut off. During the period when the power supply voltage VDD decreases, the data of the RAM and the register is saved in the nonvolatile memory.

Recently, as one of nonvolatile memories, FIG.
Non-volatile memories (flash memories) having the structure shown in FIG. However, this flash memory uses a charge that flows from the source to the drain when storing data by applying a high voltage to the floating gate.
The charge is pulled up to the floating gate and stored. Therefore, the time for storing data in the flash memory becomes longer. Therefore, it has been proposed to use a flash memory as an emergency evacuation memory in a microcomputer, but all data is stored in the flash memory during a period in which the microcomputer is actually disabled after the power is turned off. It was difficult to evacuate. Here, in order to save all data, it is sufficient to extend the time from when the power is cut off to when the microcomputer does not operate. However, this has a disadvantage that the capacitor has a large capacity.

[0005]

According to the present invention, in a microcomputer having at least a RAM and / or a register for storing data at the time of operation, a nonvolatile memory in which program data is written and which can be electrically erased collectively. And a ROM in which a program for rewriting the program in the nonvolatile memory is written, and a ROM assigned the same address as a specific address of the nonvolatile memory. Accordingly, there is provided a means for storing data stored in the RAM and / or the register in a specific address area of the nonvolatile memory.

In addition, selector means for selecting an address of the ROM during normal operation and selecting an address of the nonvolatile memory at the time of writing for the same address assigned to the nonvolatile memory and the ROM are provided. And Further, when reading the data, a means for reading the data stored in the nonvolatile memory and transferring the data to the RAM or the register is provided.

Still further, in the nonvolatile memory, an address is specified based on an address signal corresponding to the RAM or a register, and the data is stored in the RAM.
Alternatively, writing is performed by a writing signal corresponding to a register. According to the present invention, when data is written to the RAM and / or the register, the same data as the data is written to a specific address area of the nonvolatile memory. The latest data has been written in the specific address area, and the data has been saved in an emergency such as when power is turned off.

[0008]

FIG. 1 is a diagram showing an embodiment of the present invention. Reference numeral 1 denotes a CPU for controlling the operation of the microcomputer, and 2 denotes a read / write control unit 2a, an address control unit 2b, a data output unit 2c, and a data input unit 2d. Erasable nonvolatile memory, 3 is nonvolatile memory 2
Is an instruction decoder for decoding program data in the non-volatile memory 2, 5 and 6 are RAMs and registers for storing data, and 7 and 8 are data for input to the RAM 5 and the register 6. The selectors 9 for selecting each include an address control unit 9a and a data output unit 9b, and a mask ROM in which a program for rewriting the program data in the nonvolatile memory 2 is stored.
An OR gate for inputting a write signal of the AM 5 and the register 6 and a write signal from the CPU 1 to the read / write control unit 2a; a selector 11 for selecting and transferring an address signal from the program counter 3 to the nonvolatile memory 2 or the mask ROM 9; 12 is a RAM 5 and a register 6
Selector for selecting an address signal corresponding to.
Is a selector for selecting an address signal of the selector 11 or 12 and transferring it to the address control unit 2b; 14 is a selector for selecting output data of the nonvolatile memory 2;
5 is a selector for selecting and transferring output data of the selector 14 to the selector 7 or 8, and 16 is a mask ROM 9
Selector 17 for selecting the output data of the RAM 5 or the register 6, and 18 for selecting the input data of the RAM 5 or the register 6.
Selector 19 for selecting output data or other input data of the external RA.
M.

In a microcomputer having a built-in nonvolatile memory, a mask RO for rewriting the program is used.
The address numbers of M9 and the nonvolatile memory 2 are assigned consecutive address numbers. For example, assuming that addresses of 0000H to 0100H are assigned to the mask ROM 1, 0101H to FFFFH are assigned to the nonvolatile memory 2.

Since the programs written in the mask ROM 9 and the non-volatile memory 2 are for operation control, it is desirable to control the addresses of the two memories by the same addressing signal. Since the computer uses the address control of a microcomputer having a built-in ROM or RAM as it is, the nonvolatile memory 2 and the mask ROM
9 are assigned consecutive addresses. Then, an area specified by addresses 0000H to 0100H also exists in the non-volatile memory 2, which has conventionally been an unused area.

First, the normal operation will be described. During a normal operation, the CPU 1 outputs select signals SEL1 to SEL4 at H level. Therefore, the selectors 11 and 16 select the non-volatile memory 2 side, the selector 13 selects the output data of the selector 11, and the selector 14 selects the selector 16 side. Further, the selectors 7 and 8 select the input data AD2 and AD3 on the bus side, respectively.

In this state, the count value of the program counter 3 is incremented, and an address signal AD1 is output according to the count value. The address signal AD1 is input to the address controller 2b of the nonvolatile memory 2 via the selectors 11 and 13, and the address of the nonvolatile memory 2 is designated by the address signal AD1, and the program data is read. Program data is output to data output unit 2
The instruction is input to the instruction decoder 4 from c through the selectors 14 to 16 and is decoded into a program instruction by the instruction decoder 4 to execute various operations. Thereafter, the count value of the program counter 3 is incremented, the next address is specified in the nonvolatile memory 2, and various instructions are executed according to the program data. During normal operation, the microcomputer operates according to the program data while repeating the above operation.

When storing data obtained during a normal operation or a program operation in the RAM 5, the CPU 1 sets the select signal SEL2 to the L level, causes the selector 13 to select the output of the selector 12, and causes the selector 18 to select the output of the selector 17.
Select the output of Further, since the selector signal SEL3 is set to the H level, the selectors 12 and 17 are caused to select the address signal AD4 and the input data DA2 to the RAM 5, respectively.

The address signal AD2 for the RAM 5
Is input to the RAM 5, and the address of the RAM 5 is designated. After addressing the RAM 5, the input data DA2 obtained by the operation of the microcomputer is input to the RAM 5 via the selector 7, and the write signal WR2 is output to the RAM 5.
5, the input data DA2 becomes RA
Stored in M5.

On the other hand, in response to writing data to the RAM 5, an address signal AD4 for the nonvolatile memory 2 is input from the CPU 1 to the address control unit 2b of the nonvolatile memory 2 via the selectors 12 and 13, The address of the nonvolatile memory 2 is specified. At this time, the address signal AD4 is stored in the specific address area 00 of the nonvolatile memory 2.
00H to 0100H, especially RA
This specifies the area allocated for M5.

After erasing the data at the designated address, the input data DA1 is input to the data input section 2d via the selectors 17 and 18. Then, the write signal W
R2 is connected via the OR gate 10 to the read / write controller 9
a, data write control is performed, and the same data as the data written to the RAM 5 is stored in a specific address area of the nonvolatile memory 2.

When data is stored in the register 6, the same operation as that of the RAM 5 is performed. The CPU 1 sets the select signal SEL2 to L level, causes the selector 13 to select the output of the selector 12,
7 is selected. Further, the selector signal SEL3
Is set to the L level, the selectors 12 and 17 are caused to select the address signal AD5 and the input data DA3 to the register 6.

The address signal AD for the register 6
3 is input to the register 6, and the address of the register 6 is designated. After the address is specified, the input data DA3 is input to the register 6 via the selector 8, and the write signal WR3
Is input to the register 6 so that the input data D
A3 is held in the register 6. On the other hand, in response to writing data to the register 6, the address signal AD 5 for the nonvolatile memory 2 is sent from the CPU 1 to the selector 12.
And the address control unit 2 of the nonvolatile memory 2
b, the address of the nonvolatile memory 2 is designated. At this time, the address signal AD5 becomes the address signal AD4.
Similarly, the specific address area 0000 of the nonvolatile memory 2
H to 0100H are specified, and in particular, an area allocated for the register 6 is specified.

After erasing the data at the designated address, the input data DA2 is input to the data input section 2d via the selectors 17 and 18. Then, the write signal W
R3 is read / write control unit 2 via OR gate 10
a, and the same data as the data written to the register 6 is stored in the specific address area of the nonvolatile memory 2.

As described above, the address signals corresponding to the RAM 5 and the register 6 are input to the address control unit 2b of the nonvolatile memory 2, and an address is specified according to each address signal. Therefore, the area corresponding to the RAM 5 or the register 6 is allocated to the nonvolatile memory 2. RA corresponding to the allocated area
The same data as the data in M5 or the register 6 is stored.

Here, it is assumed that the power supply is cut off. Since the latest data is written in the non-volatile memory 2 every time the data in the RAM 5 or the register 6 is rewritten, the data in the RAM 5 and the register 6 are saved in the non-volatile memory 2. When the power is restored, the CPU 1 sets the select signals SEL2 and SEL4 to the L level, causes the selector 14 to select the data to be transferred to the selector 15, and causes the selectors 7 and 8 to select the data from the nonvolatile memory 2. . In this state,
The CPU 1 sets the selector signal SEL3 to the H level and causes the selectors 12 and 15 to select the RAM5 side, and stores the address signals AD4 and AD2 in the nonvolatile memory 2 and the RAM5.
Output to each. According to the address signal AD1,
An address corresponding to the assigned area in the specific address area is designated. After that, the read signal R
E is output, and the save data in the RAM 5 is read from the nonvolatile memory 2. The read data is the selector 1
Input to the RAM 5 via the RAM 4, 5, and 7,
Is written to.

Next, the select signal SEL3 goes low, and the register 6 is selected. The CPU 1 outputs the address signals AD3 and AD5 to the register 6 and the nonvolatile memory 2, respectively. In accordance with address signal AD5, an address corresponding to the assigned area in the specific address area is specified. After that, the read signal R
E is output, and the save data of the register 6 is read from the nonvolatile memory 2. The read data is input to the register 6 via the selectors 14, 15, and 8, and is written.

In this way, when the power is restored, the data saved in the nonvolatile memory 9 is returned to the RAM 5 and the register 6, so that the data can be prevented from being lost. still,
In FIG. 1, the data of the RAM 5 and the register 6 are stored in the non-volatile memory 2. However, if the data does not want to be lost at the time of power-off or the like and should be temporarily saved,
It is possible to temporarily save not only the data of the above circuit but also the data of other circuits.

Next, rewriting of data by an external interrupt during normal operation will be described. First, the select signal SL1 from the CPU 1 becomes L level, the selector 11 outputs the address signal AD1 to the mask ROM 9, and the selector 16 selects the output data of the mask ROM 9. Thereafter, after the current count value of the program counter 3 is stored in a register (not shown), the count value of the program counter 3 is set to a predetermined value. As a result, an address signal AD1 designating any one of the addresses 0000H to 0100H for the mask ROM 9 is output. The address signal AD1 is supplied to the mask RO via the selector 11.
It is input to the address control unit 9a of M9. And RO
The address of M9 is specified, and the program data in ROM 9 is read. The program data is stored in the selector 16
To the instruction decoder 4 and decoded into a program instruction. Further, the program counter PC is incremented, and the next address in the ROM 9 is designated. A program for rewriting data in the nonvolatile memory 2 is written in the mask ROM 9, and the CPU 1 operates according to the program. First, data to be rewritten is read from the external RAM 19. The read data is held in a register (not shown) of the CPU 1 and then transferred to the data input unit 2a of the nonvolatile memory 2 as input data DA1. Data of the data input unit 2a is written to the nonvolatile memory 2,
Data rewriting is completed. When the rewriting is completed, the count value immediately before the external interrupt stored in the register (not shown) is set to the program count 3 and the operation returns to the normal operation.

[0025]

According to the present invention, every time data is written to the RAM or the register, the same data as the data is written to the nonvolatile memory, so that the data can be stored even in a nonvolatile memory having a long write time. Data can be prevented from being lost in an emergency such as power-off. Therefore, it is possible to shorten the time from when the power is cut off until the microcomputer actually stops operating, and it is not necessary to increase the size of the backup capacitor. In particular, since a non-volatile memory that can be electrically erased collectively is used as the memory, data can be stored even when the power is off.

Further, since data is saved in a part of the nonvolatile memory which has not been used in the related art, the nonvolatile memory can be effectively used.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram showing a conventional example.

FIG. 3 is a structural diagram showing the structure of a nonvolatile memory that can be electrically erased in a batch.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 CPU 2 Non-volatile memory 3 Program counter 4 Instruction decoder 5 RAM 6 Registers 7, 8, 11-18 Selector 9 ROM 10 OR gate 19 External RAM

Claims (4)

[Claims] At least R at which data at the time of calculation is held
In a microcomputer having an AM and / or a register, a nonvolatile memory in which program data is written and electrically erasable collectively, and a program for rewriting a program in the nonvolatile memory are written and the nonvolatile memory And a ROM assigned the same address as the specified address of the nonvolatile memory, and stores data stored in the RAM and / or the register in response to a write signal to the RAM and / or the register. A microcomputer comprising means for storing data in an area. 2. A selector for selecting an address of the ROM during normal operation and an address of the non-volatile memory during writing for the same address assigned to the nonvolatile memory and the ROM. The microcomputer according to claim 1, wherein 3. The microcomputer according to claim 1, further comprising means for reading data stored in said nonvolatile memory and transferring said RAM and registers when reading data. 4. The nonvolatile memory according to claim 3, wherein
3. The microcomputer according to claim 1, wherein an address is specified based on an address signal corresponding to M or a register, and the data is written by a write signal corresponding to the RAM or the register.