JPH11283397A - Semiconductor memory and its test method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a DRAM making a test time and disturbance by a testing burn-in test device equivalent to those of an ordinary tester. SOLUTION: This device is provided with a memory cell array 9, a row decoder 6, a column decoder 7, a sense amplifier 8 corresponding to data input/ output of the memory cell array 9, a data-out buffer 10, a data-in buffer 11, a clock generator 2 generating an internal control signal, a row address buffer 4, a column address buffer 5, an internal signal generating circuit (CBRCR circuit) 1, and a test mode entry discriminating circuit 3. Then, the CBRCR circuit 1 is provided with a generating circuit of a RTO signal for preventing erroneous reset of a RASB signal, a generating circuit of a CBRB counter signal 104 generated by timing of CAS before RAS, and a switch circuit receiving a test mode entry signal and inputting a RTO signal 101 to a generating circuit of the CBRB counter signal 104. Short cycle disturbance being equivalent to an ordinary tester can be realized.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory device functioning as a dynamic random access memory, and more particularly to a semiconductor memory device for performing a function test using a testing burn-in test device and a test method thereof.

[0002]

2. Description of the Related Art An example of a conventional semiconductor device functioning as a dynamic random access memory (hereinafter referred to as DRAM) is shown in a block diagram of FIG. DRAM
Is an input / output terminal I / O and an external clock RAS
B, CASB, OEB, WEB, ADDRESS signals, and the memory cell array 9 corresponding to the input / output signals, and the row decoder 6 corresponding to the memory cell array 9.
And a column decoder 7, a sense amplifier 8 corresponding to input / output of the memory cell array 9, and a data out buffer 1.
0, a data-in buffer 11, a clock generator 2 for generating an internal control signal by an external clock, a row address buffer 4 as an address input buffer, and a column address buffer 5. In addition to this, an internal signal 115 for preventing the erroneous reset of the RASB signal (hereinafter referred to as a "las time out signal: RTO signal").
And a cas-before-lass counter RT as an internal signal generation circuit for generating a CBRB counter signal 118 generated at the cas-before-lass timing
An O circuit (hereinafter referred to as a CBRCR circuit) 15 is provided.

In this type of DRAM, when data is read from the memory cell array 9, an address signal externally input via an input terminal is input to a row address buffer 4 and a column address buffer 5. A row address buffer signal 107 is output from the row address buffer 4 and input to the row decoder 6. Therefore, the word line 10 corresponding to the external row address
9 is selected. Therefore, data is output from the memory cell in the memory cell array 9 corresponding to the selected word line 109 to the I / O line 111, and the data of the memory cell selected by the sense amplifier 8 is amplified. Next, a column address buffer signal 108 is output from the column address buffer 5 and input to the column decoder 7. Therefore, the Y switch 110 corresponding to the external column address is selected. The data specified by the external address is selected from the data amplified by the sense amplifier 8 by the selected Y switch 110, and the data is output to the data bus 113. The data is output from the I / O pin to the outside via the data output buffer 10.

At the time of writing, the data flows from the data input buffer 11 via the I / O pin from the outside to the data bus 113, and the selected memory cell is selected in the same manner as at the time of reading. Will be written to the data.

The series of data is controlled by clock signals RASB, CASB, OEB and WEB.
It is. The RASB mainly controls the capture of the row address, the CASB controls the capture of the column address, the OEB controls the reading, and the WEB controls the writing. These clock signals are input to the clock generator 2, and the clock generator signals 102, 103, 105, 1 which are the respective internal control signals.
12 to control data such as row / column address, reading, and writing.

Here, the above-mentioned RTO signal 115 and CB
The RB counter signal 116 will be described. FIG. 5 is a detailed block diagram of the CBRCR circuit 15 that generates these signals. Upon receiving the clock generator signal 104 from the clock generator 2 in FIG.
5 and a CBRB counter signal 116
Is generated by a circuit 25 that generates

Regarding the RTO signal 115, if the externally input RASB signal is reset during internal operation, for example, while the word line is being raised, or during sensing,
Naturally, the internal operation becomes abnormal, and the data in the memory cell is destroyed. To prevent this erroneous reset of RASB, R
A TO signal 115 is present. This RTO signal 115
As shown in the timing chart of FIG. 6, is a one-shot pulse until the end of sensing. Even if an external RASB reset is input within this pulse width (within sensing completion), it is not accepted internally but reset by the RTO signal 115. It seems to take.

The CBRB counter signal 116
Is CB by external clocks RASB and CASB.
R timing (cas before RAS timing RAS
CASB is dropped to a low level before B is dropped to a low level. ) Is generated internally as shown in FIG. This is an internal signal for performing CBR refresh. In a DRAM, merely writing data causes internal cell data to be lost over time. Therefore, refresh (rewrite) is performed, and CBR refresh is one such refresh method. When the clock generator signal 104 is input, the CBR counter signal generation circuit 25 operates in response to the clock generator signal 104, generates the CBRB counter signal 116, inputs the signal to the row address buffer 4, and the row address is automatically advanced internally. , Lift all word lines inside,
It automatically refreshes. The clock of the CBRB counter signal is external RASB or external CAS.
It is generated by giving the clock of B from outside.

By the way, as a method of performing a function test of such a DRAM, a method using a tester which has been conventionally used along with an increase in the capacity of the DRAM avoids an increase in the time required for selecting the DRAM and an increase in the sorting cost. In recent years, a large-scale parallel tester, TBT, has been newly added to the sorting process.
(Testing burn-in testers) devices are appearing. Further, the TBT device is also used in a BT (burn-in) process for rejecting an initial failure in a sorting process. The BT step is a step of driving a word line and rejecting an initial operation defect in a stress test in which data 0/1 is alternately written.

[0010]

However, this T
The BT device has a very large limitation in operability. FIG. 7 shows the measurement board 2 of the TBT device.
7 as 4 × 16 MDRAM products (300 MIL, 2
As shown in the example of a 4 PIN, SOJ package), 272 chips are mounted on one board, but the external clock is configured to drive all 272 chips. Therefore, in a normal tester, the rise / fall time of the clock (hereinafter referred to as tT) is
Regardless of the order of about 2 ns, tT takes about 50 ns in the TBT device. This tT
In consideration of the above, when a basic clock cycle is created, the minimum clock cycle is about 500 ns as shown in FIG.

For this reason, the TBT is added to the BT process.
Assuming a case where the device is applied, a single tester normally requires only about 100 ns, but it takes about five times as long as 500 ns due to the above-described restriction. That is, the time required for the BT process is five times. In a BT stress test, the manner in which stress is applied greatly differs from that in a normal tester. In particular, the disturb of the word line becomes less severe, and the stress is naturally severer when the word line is raised or lowered in a short cycle. This is 5 times less when using a TBT device than when using a normal tester.
There will be a double difference. This is not necessarily true only for the BT process, and various tests performed by the TBT device,
This is especially true for disturb tests. In this case, a method of increasing the power supply capability of the TBT device side, that is, a method of increasing the capability of tT is also conceivable.
To make tT equal to that of a conventional tester, a power supply equivalent to that of a conventional tester must be mounted, and the number of simultaneous and parallel measurements must be reduced. This naturally contradicts the nature of the TBT device that has recently been used as a cost reduction method for increasing the capacity.

As described above, in a conventional semiconductor memory device formed by a DRAM, in a disturb test using a TBT device, particularly in a BT process, the restriction due to the tT capability of the TBT device is very large. In this case, a test must be performed, and there is a problem that the test time is increased and the disturb of the word line is less liable to occur as compared with a normal tester.

An object of the present invention is to provide a semiconductor memory device capable of realizing a short cycle disturbance equivalent to that of a normal tester and a test method therefor.

[0014]

A semiconductor memory device according to the present invention includes a test mode entry determination circuit for outputting a test mode entry signal for entering a test mode via a clock signal and an address signal input from the outside. , An internal signal generation circuit for generating a CBRB counter signal at the time of CBR refresh generated at the timing of cas before before and an RTO signal for preventing an external RASB clock signal from being reset erroneously. A switch circuit for inputting the RTO signal to a circuit for generating the CBRB counter signal;

Further, the method for testing a semiconductor memory device according to the present invention uses a predetermined cycle without using a first test step for entering a test mode and taking in a clock signal and an address signal input from outside. The method includes a second test step of executing the test mode entered in the first test step, and a third test step of resetting the test mode entered in the first test step. And

In the present invention, since the CBRB counter signal is generated using the RTO signal as a clock in response to the test mode entry signal output in the test mode, the internal RTO can be input without inputting an external clock.
It is possible to drive all the word lines in the chip by using the signals, and in consideration of the tT capability of the TBT device, it is possible to execute a test using an internal signal clock without using an external clock, Short cycle disturbance equivalent to that of a normal tester can be realized.

[0017]

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows a DRAM to which the present invention is applied.
It is a block diagram of. The basic configuration is the same as that of the conventional configuration shown in FIG. 4, in which input / output terminals I / O, external clocks RASB, CASB, OEB, WEB, and AD
A memory cell array 9, a row decoder 6 and a column decoder 7 corresponding to the memory cell array 9, a sense amplifier 8 corresponding to the input / output of the memory cell array 9, Out buffer 10, data in buffer 11,
A clock generator 2 that generates an internal control signal by an external clock, a row address buffer 4 that is an address input buffer, and a column address buffer 5 are provided. Although the configuration is the same as the conventional configuration, the configuration is different as will be described later.
A CBRCR circuit (casing circuit) as an internal signal generating circuit for generating a TO signal 101 and a CBRB counter signal 104 generated at the timing of the cas-before-lass.
(Before-lass counter / RTO circuit) 1 and a test mode entry determination circuit 3 that outputs a test mode entry signal 105.

The detailed block configuration of the CBRCR circuit 1 is shown in FIG. A circuit 14 for receiving a clock generator signal 102 and generating an RTO signal for preventing an erroneous reset of a CASB signal, and a circuit 12 for generating a CBRB counter signal 104 at a cas-before-lass timing
And an RTO signal 101 output from the RTO generation circuit 14 upon receiving the test mode entry signal 105
4 is constituted by a switch circuit 13 input to the CBRB counter signal generation circuit 12.

The test mode entry determination circuit 3 is configured to determine the test mode and then output the test mode entry signal 105. Here, the test mode is a mode for operating an internal circuit used only for reducing the time for product evaluation and selection, etc. In a normal DRAM, in order to prevent erroneous entry by a user, FIG. As shown in (1), an entry is made in a WCBR (write CBR) cycle. After the WEB signal and the CASB signal, which are external clocks, are set to low level, the RASB signal is lowered to low level. Next, CASB
Set the signal to high level, and then drop it to low level again.
Various test modes are entered depending on the external address at that time. In this test mode entry cycle, the entry is confirmed by the test mode entry determination unit 3, and the test mode entry signal 105 is output. The test mode entry signal 105 is input to the CBRCR circuit 1.

The DRA according to the present embodiment including the CBRCR circuit 1 and the test mode entry determination circuit 3 as described above.
The data read / write operation in M is the same as the conventional configuration in FIG. Here, the internal operation in the test mode will be described. The test mode entry signal 105 is output from the switch circuit 13 in the CBRCR circuit 1.
Input to the CBR counter 1
2 will receive. For this reason, conventionally, CBR
In order to take advantage of the prevention of erroneous reset of the external RASB during refresh, the count signal of CBRB is set to RTO.
Here, the CBRB count signal 104 and the RTO signal 101 are complementary to each other.
As can be seen from the timing chart of FIG. 2B, the CBRB count signal 10
4 will be driven. By doing so, C
At the time of BR refresh, the external RASB is
ASB is clocked and all word lines 109 in the chip are
Can be driven by using the internal RTO signal 101 without inputting an external clock.

As described above, by automatically holding the external clock input to the test mode thereafter, all word lines can be automatically accessed. Therefore, in the TBT device, it becomes possible to execute the word-related disturbance in a short cycle without considering the tT of the TBT device. As a method of escaping from the test mode, it is only necessary to execute a ROR cycle (lass-only refresh: timing at which only the external RASB is clocked and other external clocks are held at a high level).

[0022]

As described above, according to the present invention, the test mode entry signal output in the test mode is received, and the RTO signal for preventing the erroneous reset of the external RASB clock signal is used as a clock to form a cas-before-laser. Since the CBRB counter signal at the time of CBR refresh is generated according to the timing, it is possible to drive all the word lines in the chip using the internal RTO signal without inputting an external clock. Thereby, TBT
In consideration of the tT capability of the device, it is possible to execute a test using an internal signal clock without using an external clock, thereby realizing a short cycle disturbance equivalent to that of a normal tester. There is.

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a block diagram of a CBRCR circuit according to the present invention.

FIG. 3 is a timing chart showing an example of a test timing in the circuit of FIG. 1;

FIG. 4 is a block diagram of a conventional configuration of a DRAM to which the present invention is applied.

FIG. 5 is a block diagram of a conventional CBRCR circuit.

FIG. 6 is a diagram showing an example of a test timing in a conventional example.

FIG. 7 is a diagram illustrating an example of a measurement board in the TBT device.

FIG. 8 is a test timing chart in the TBT device.

[Explanation of symbols]

Reference Signs List 1 CBRCR circuit (cass-before-lass counter, RTO circuit) 2 Clock generator 3 Test mode entry determination circuit 4 17 Row address buffer 5 Column address buffer 6 Row decoder 7 Column decoder 8 Sense amplifier 9 Memory cell array 10 Data out buffer 11 Data-in buffer 12 Cas-before-lass counter 13 Switch circuit 14 RTO signal generation circuit 101 RTO signal 102 Clock generator signal 104 CBRB counter signal 105 Test mode entry signal

Claims (5)

[Claims] 1. A test for outputting a test mode entry signal for entering a test mode based on a clock signal and an address signal input from the outside in a semiconductor memory device to be functionally tested using a testing burn-in test apparatus. A mode entry determination circuit;
CBRB counter signal at the time of CBR refresh generated by before-lass timing and external RASB
An internal signal generation circuit for generating an RTO signal for preventing an erroneous reset of a clock signal; and the internal signal generation circuit includes a switch circuit for inputting the RTO signal to a circuit for generating the CBRB counter signal. A semiconductor memory device characterized by the above-mentioned. 2. The circuit according to claim 1, wherein the internal signal generation circuit receives a clock generator signal and generates a CBRB counter signal at a cas-before-lass timing, and a CASB signal error signal receives the clock generator signal and the CBRB counter signal. 2. A circuit for generating an RTO signal for reset prevention, and a switch circuit for receiving the test mode entry signal and inputting an RTO signal output from the RTO signal generation circuit to the CBRB counter signal generation circuit. 3. The semiconductor memory device according to claim 1. 3. The semiconductor memory device according to claim 1, wherein the semiconductor memory device to be functionally tested using the testing burn-in test device is a dynamic random access memory. 4. A method of performing a function test of a semiconductor memory device using a testing burn-in test device,
Using a predetermined cycle, execute a first test step for entering the test mode, and execute the test mode entered in the first test step without taking in an externally input clock signal and address signal. And a third test step for resetting the test mode entered in the first test step. 5. A method for performing a function test of a semiconductor memory device using a testing burn-in test device,
A test mode entry determination circuit provided in the semiconductor memory device outputs a test mode entry signal for entering a test mode based on a clock signal and an address signal input from the outside, and an internal circuit provided in the semiconductor memory device. Upon receiving the test mode entry signal, the signal generation circuit uses the RTO signal as a clock to prevent an erroneous reset of the external RASB clock signal and performs a CBR during CBR refresh at a cas before before timing.
A method for testing a semiconductor memory device, comprising generating a BRB counter signal.