JPH11284084A - Nonvolatile semiconductor storage device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable improvement of erasing speed and erasable life of data, and reduction of tunnel current irregularities between memory cells. SOLUTION: This device is provided with a floating gate 5 formed on a gate oxide film 2 on a semiconductor substrate 1, and a control gate 7 formed on an end portion of the floating gate 5 via a tunnel oxide film 6 and overlaps with the end portion. Polysilicon films, constituting the floating gate 5, are formed by heat-treating first and second amorphous silicon films, in which at least a lower layer polysilicon film and an upper layer polysilicon film are formed at different film forming temperatures. The grain size of the upper layer polysilicon film becomes smaller than that of the lower layer polysilicon film.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a nonvolatile semiconductor memory device, and more particularly, to a technique for improving data rewriting characteristics in a split gate flash memory.

[0002]

2. Description of the Related Art A method of manufacturing a split gate flash memory, which is a conventional nonvolatile semiconductor memory device, will be described below with reference to the drawings. This split gate type flash memory is a flash memory in which a control gate 59 is formed from the upper part to the side part of the floating gate 57 via a tunnel oxide film 58 as shown in FIG.

In order to fabricate this, first, as shown in FIG. 13, a gate oxide film 52 made of a SiO 2 film, a polysilicon film 53 and a silicon nitride film as an oxidation resistant film having an opening 55 are formed on a semiconductor substrate 51. Films (SiN films) 54 are sequentially formed, and the silicon nitride film 54 is
The polysilicon film 5 at the opening 55 is thermally oxidized by a COS (Local Oxidation of Silicon) method.
A selective oxide film 56 is formed on 3 (see FIG. 14).

Next, the polysilicon film 53 is removed by etching using the selective oxide film 56 as a mask to form a floating gate 57 as shown in FIG. Subsequently, the insulating film 52 was isotropically etched with a hydrofluoric acid-based etchant and remained only directly below the floating gate, or was removed by etching so that the insulating film 52 was thinly left on the substrate. Thereafter, as shown in FIG. 16, C is deposited on the entire surface by a chemical vapor deposition (CVD) method.
A tunnel oxide film 58 composed of a VD oxide film and a thermal oxide film formed by thermally oxidizing the surface is formed.

Thereafter, a polysilicon film is formed on the tunnel oxide film 58 and is patterned so as to remain from the upper portion to the side portion of the floating gate 57 to form a control gate 59. The floating gate 57 and the floating gate 57 thus formed are formed. Using control gate 59 as a mask, impurities are implanted into semiconductor substrate 51 to form source / drain diffusion regions 60 and 61. Thus, a split gate type flash memory as shown in FIG. 17 is formed.

In the above-mentioned split gate type flash memory, a transistor of a memory cell to be written (hereinafter, referred to as a selected cell) is turned on, and electrons are injected into the floating gate 57 to write a program. I was going. FIG.
5, the polysilicon film 53 shown in FIG. 14 is thermally oxidized at the corners on the upper surface of the floating gate 57, as indicated by the portion surrounded by the alternate long and short dash line.
By forming the selective oxide film 56 on 3, an acute sharp portion 57 </ b> A is formed at the corner.

The sharp portion 57 formed at the acute angle
In the portion A, the electric field concentration easily occurs, thereby improving the erasing characteristic when electrons are extracted from the floating gate 57 to the control gate 59.

[0008]

However, according to the above-mentioned conventional nonvolatile semiconductor memory device, the LOCOS (sharp) is formed at the corner of the floating gate 57 in order to improve the electron erasing characteristics. Lo
The polysilicon film is selectively oxidized by a cal 0xidation of Silicon) method.

At this time, as shown in FIG. 14 and the like, the polysilicon film 53 which will later become the floating gate 57 is formed.
Are formed with uneven and jagged irregularities (see convex portions 57B in the schematic perspective view of the floating gate 57 shown in FIG. 18). As a cause of forming such uneven jagged convex portions 57B, for example, when the selective oxide film 56 is formed, it is easily formed along the adjacent grain grains of the polysilicon film 53, It is considered that, in the region having such a gap, the terminal end of the selective oxide film 56 is extended, and is affected by the arrangement of the grains.

As described above, when the uneven and rugged projections 57B are formed on the surface of the polysilicon film 53, when the floating gate 57 is formed, the sharp portion of the floating gate 57 is formed as shown in FIG. Non-uniform jagged projections 57B are also formed on the periphery of 57A. Here, the erasing operation will be described with reference to FIG. 19. For example, the voltage (VCG) of the control gate 59 is 14 V, the source voltage (Vs) is 0 V, and the drain voltage (V
By setting D) to 0 V, the data (electrons) stored in the floating gate 57 is drawn out to the control gate 59, and the data is erased. That is, the flash memory includes the capacitance between the floating gate 57 and the drain region 60 and the control gate 5
9 and the capacitance between the floating gate 57, the former is overwhelmingly larger, and the control gate voltage (VCG) is 14V as described above.
When the drain voltage (VD) is 0 V, a high electric field is generated between the control gate 59 and the floating gate 57. As a result, a Fowler-Nordheim Tunnel Current (referred to as FN tunnel current) flows and the floating gate 57 flows.
Are extracted to the control gate 59 side (see arrow A in FIG. 19), and data is erased.

During the erase operation, if the uneven portion 57B is formed on the sharp portion 57A of the floating gate 57 as described above, the electric field concentrates on a particularly sharp portion in the convex portion 57B. That is, during the data erasing operation, the electrons in the floating gate 57 are always drawn out to the control gate 59 via several identical protrusions 57B.

[0012] Therefore, in order to deal with data rewriting requests of tens of thousands to hundreds of thousands of times, and even millions of times, in consideration of the sharp portion 57A as described above, some convex portions 57B are required. The erasing structure in which the erasing operation is performed only in one station cannot improve the erasing speed or the data rewriting life. Further, as described above, if the uneven portion 57B is formed on the sharp portion 57A of the floating gate 57, the variation in tunnel current between the memory cells becomes large, so that the miniaturization for increasing the storage capacity and the miniaturization are required. This has hindered multi-leveling.

Accordingly, in the present invention, a relatively uniform sharp portion is formed instead of the above-described one-point concentrated erasing structure of the sharp portion 57A only from a certain number of convex portions 57B. It is an object of the present invention to provide a nonvolatile semiconductor memory device capable of improving erasing speed and data rewriting life and reducing tunnel current variation between memory cells, and a method of manufacturing the same.

[0014]

SUMMARY OF THE INVENTION Accordingly, the present invention provides a floating gate 5 formed on a gate oxide film 2 on a semiconductor substrate 1 so as to overlap one end of the floating gate 5 with a tunnel oxide film 6 interposed therebetween. In the nonvolatile semiconductor memory device having the control gate 7 formed in the above, the polysilicon film 4 forming the floating gate 5 is formed at a different deposition temperature at least at a lower polysilicon film 4A and an upper polysilicon film 4B. By forming the first and second amorphous silicon films 3A and 3B by heat treatment, the grain size of the upper polysilicon film 4B is smaller than the grain size of the lower polysilicon film 4A. Is what you do.

In the manufacturing method, the step of forming the polysilicon film forming the floating gate 4 includes the steps of forming at least the lower polysilicon film 4A and the upper polysilicon film 4B at different deposition temperatures at the first and second temperatures. After forming the two amorphous silicon films 3A and 3B, the amorphous silicon films 3A and 3B are polycrystallized by heat treatment.

Further, according to the present invention, a sharp corner 18 is formed at an upper corner formed on the gate oxide film 12 on the semiconductor substrate 11.
In a nonvolatile semiconductor memory device having a floating gate 18 having a T and a control gate 20 formed so as to overlap one end of the floating gate 18 with a tunnel oxide film 19 interposed therebetween, a poly-silicon constituting the floating gate 18 is formed. The first and second amorphous silicon films 13A, in which the silicon film 14 is formed at different film forming temperatures of at least the lower polysilicon film 4A and the upper polysilicon film 4B where the sharp corners 18T are formed, 13B, the grain size of the upper polysilicon film 18B in which at least the sharp corner portion 18T is formed is smaller than the grain size of the lower polysilicon film 18A. .

In the manufacturing method, the step of forming the polysilicon film 14 constituting the floating gate 18 includes the step of forming at least the lower polysilicon film 4A and the upper polysilicon film 4B where the sharp corners 18T are formed. After forming the first and second amorphous silicon films 13A and 13B at different film forming temperatures, the amorphous silicon films 13A and 13B are heat-treated to be polycrystallized.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a nonvolatile semiconductor memory device according to a first embodiment of the present invention and a method for manufacturing the same will be described. The nonvolatile semiconductor memory device according to the first embodiment of the present invention includes a floating gate 5 formed on a gate oxide film 2 on a semiconductor substrate 1 as shown in FIG. A split gate type flash memory characterized in that a control gate 7 is formed over a portion of the flash memory through a tunnel oxide film 6.

Hereinafter, a method of manufacturing a memory cell of such a flash memory will be described with reference to the drawings. First, as shown in FIG.
After forming the gate oxide film 2 having a thickness of about 00 °, a first amorphous silicon film 3A having a thickness of about 1200 ° is formed at a deposition temperature of about 525 ° C.
A second amorphous silicon film 3B having a thickness of about 20 ° to 200 ° is formed at a film forming temperature of 25 ° C. The amorphous silicon films 3A and 3B can be formed by CVD using monosilane (SiH4) and phosphine (PH3) at the respective film forming temperatures described above.

Next, as shown in FIG. 3A, the first and second amorphous silicon films 3A and 3B are
The polysilicon film 4 is formed by heat treatment at 50 ° C. to 950 ° C. and polycrystallization. At this time, of the polysilicon film 4, at least a lower polysilicon film 4A and an upper polysilicon film 4B are formed at different film forming temperatures.
Since the first and second amorphous silicon films 3A and 3B are formed by heat treatment, the temperatures for polycrystallization are different. Therefore, the first and second amorphous silicon films 3A and 3B are polycrystallized around different nuclei to form grains of different sizes. The thickness of the second (upper) amorphous silicon film 3B is sufficiently smaller than that of the first (lower) amorphous silicon film 3A, and the grain size of the upper polysilicon film 4B is at most the second amorphous silicon film. 3B. For example, the grain size of the upper polysilicon film 4B is about 20 nm to 20 nm.
At 0 nm, a silicon grain of this size is formed, a grain boundary considered to have a large tunnel current locally increases, and variation between memory cells can be reduced. The grain size of the lower polysilicon film 4A is about 1000 nm to 2000 nm.

Subsequently, the polysilicon film 4 is patterned by using a photoresist film (not shown) as a mask.
A floating gate 5 is formed as shown in FIG. At this time, the lower layer portion 5A and the upper layer portion 5B of the floating gate 5 correspond to the lower polysilicon film 4A and the upper polysilicon film 4B of the polysilicon film 4, respectively. Polysilicon film 4A
And the upper polysilicon film 4B are formed at different film forming temperatures.
Since B is formed by heat treatment, the grain size of the upper polysilicon film 4B is formed smaller than the grain size of the lower polysilicon film 4A, so that the polysilicon film 4 is patterned and the floating gate 5 is formed.
Is formed, it is possible to reduce the variation in the protruding state of the corner portion 5T formed thereon. Therefore, it is possible to suppress the erasing structure from being concentrated only at a certain number of convex portions which are particularly sharp as in the conventional device.

Therefore, when the data (electrons) stored in the floating gate 5 is extracted to the control gate 7 side, the movement path of the electrons in the tunnel oxide film 6 is less concentrated, and the tunnel current increases.
The erasing time can be shortened. In addition, by improving the erasing efficiency, a voltage value used in a writing operation, an erasing operation, or the like can be reduced. Further, the wear deterioration of the oxide film 6 caused by the stress applied to the tunnel oxide film 6 during the transfer of electrons can be dispersed and delayed, and the life of rewriting data can be improved.

Further, as described above, since the surface of the floating gate 5, especially the corner 5T, can be formed in a substantially uniform state, it is possible to reduce the variation in tunnel current between memory cells. Subsequently, as shown in FIG. 5, the surface of the substrate is thermally oxidized so as to cover the floating gate 5, thereby forming a tunnel oxide film 6 having a thickness of about 300.degree.

Next, a polysilicon film is formed for about 1500
{Circle around (1)} After forming a conductive film by sequentially forming a tungsten silicide film (WSix film) of about 1500 °, patterning is performed so that the tungsten silicide film remains from the upper portion to the side portion of the floating gate 5 via the tunnel oxide film 6. Then, a control gate 7 as shown in FIG. 6 is formed. Then, impurity ions are implanted into the surface layer of the substrate in the source region forming region via a resist film (not shown) having an opening on the source region 8 described later. Further, impurity ions are implanted into the surface layer of the substrate in the drain region forming region through a resist film (not shown) having an opening on the drain region 9 described later. Then, by subjecting the entire surface to heat treatment to diffuse the above-described impurity ions implanted into the surface layer of the substrate to form source / drain regions 8 and 9, a split gate type flash memory as shown in FIG. 1 is formed. You. The control gate 7 is not limited to the above-described laminated structure of the polysilicon film and the tungsten silicide film, but may be a single-layer film made of a polysilicon film.

Hereinafter, a nonvolatile semiconductor memory device according to a second embodiment of the present invention and a method for manufacturing the same will be described. Note that the nonvolatile semiconductor memory device of the second embodiment
As shown in FIG. 7, a gate oxide film 12 on a semiconductor substrate 11 is formed.
A floating gate 18 having a sharp corner 18T formed thereon, and a floating gate 18
The structure of the first embodiment described above is applied to a split gate type flash memory in which a control gate 20 is formed from the upper part to the side part through a tunnel oxide film 19, that is, the sharp corner part An upper layer portion of the floating gate 18 on which the 18T is formed is formed in a substantially uniform convex state. Hereinafter, a method for manufacturing the nonvolatile semiconductor memory device according to the second embodiment will be described.

First, as shown in FIG. 8, after a gate oxide film 12 having a thickness of about 100 ° is formed on a semiconductor substrate 11, a first amorphous silicon film having a thickness of about 1200 ° is formed at a deposition temperature of about 525 ° C. Forming a film 13A,
Furthermore, at a film forming temperature of about 425 ° C., about 20 ° to 2 ° C.
A second amorphous silicon film 13B having a thickness of 00 ° is formed. Incidentally, the amorphous silicon film 13A, 1
3B can be formed by CVD using monosilane (SiH4) and phosphine (PH3) at the respective film forming temperatures described above.

Next, after the first and second amorphous silicon films 13A and 13B are heat-treated at about 850 ° C. to 950 ° C. to be polycrystallized to form a polysilicon film 14, as shown in FIG. On the polysilicon film 14, a silicon nitride film (SiN film) 15 having a thickness of about 500 ° is formed. A desired opening 16 is formed on the silicon nitride film 15 by a photolithography process. Here, the first and second amorphous silicon films 13A and 13B in which at least the lower polysilicon film 14A and the upper polysilicon film 14B of the polysilicon film 14 are formed at different film forming temperatures are heat-treated. Therefore, the polycrystallization temperatures are different. Therefore, the first and second amorphous silicon films 3A and 3B are polycrystallized around different nuclei to form grains of different sizes.
The thickness of the second (upper layer) amorphous silicon film 13B is sufficiently smaller than that of the first (lower) amorphous silicon film 13A, and the grain size of the upper polysilicon film 14B is at most the second amorphous silicon film. 13B
For example, the grain size of the upper polysilicon film 4B is about 20 nm to 200 nm, and a silicon grain of this size is formed, and the grain boundary, which is considered to be locally large in tunnel current, increases. In addition, variation between memory cells can be reduced. The grain size of the lower polysilicon film 14A is approximately 1000 nm to 2000 nm (see FIG. 3B described in the first embodiment).

Next, as shown in FIG. 10, using the silicon nitride film 15 as a mask, the surface of the polysilicon film 14 below the opening 16 is covered with a LOCOS (Local Oxidation of Silic).
The selective oxidation is performed by the on) method to form the selective oxide film 17.
In the present embodiment, the thickness of the central portion where the thickness of the selective oxide film 17 is maximum is approximately 1500 °,
7, the film thickness becomes thinner toward the outer peripheral portion. Therefore,
As shown in FIG. 11, when the polysilicon film 14 is etched using the selective oxide film 17 as a mask to form the floating gate 18, the floating gate 18
Is formed in a depressed state with its center at the center, and a sharp corner 18T is formed at the upper corner. In this step, for example, the flow rate is 80 sccm with an ECR type etcher.
Cl2 gas, 02 gas at a flow rate of 5 sccm, pressure 5 mT
The polysilicon film 14 is etched under the conditions of orr, a PF power of 50 W, and a magnetron of 250 mA.

At this time, the floating gate 18
The lower layer portion 18A and the upper layer portion 18B (sharp corner portions 18T are formed) correspond to the lower polysilicon film 14A and the upper polysilicon film 14B of the polysilicon film 14, and the polysilicon film 14 is formed. Since at least the lower polysilicon film 14A and the upper polysilicon film 14B are formed by heat-treating the first and second amorphous silicon films 13A and 13B formed at different deposition temperatures, the upper polysilicon film 14A and the upper polysilicon film 14B are formed by heat treatment. Since the grain size of the polysilicon film 14B can be formed smaller than the grain size of the lower polysilicon film 14A, the surface of the sharp portion 18T does not have as much unevenness as the conventional one, and the variation of the sharp angle portion 18T can be reduced. . Therefore, it is possible to suppress the erasing structure from being concentrated only at a certain number of convex portions which are particularly sharp as in the conventional device.

Therefore, data (electrons) stored in the floating gate 18 is transferred to the control gate 20.
When the electrons are pulled out to the side, the movement path of the electrons in the tunnel oxide film 19 is less concentrated, and the tunnel current increases, so that the erasing time can be shortened. In addition, by improving the erasing efficiency, a voltage value used in a writing operation, an erasing operation, or the like can be reduced. Further, the wear deterioration of the oxide film 19 caused by the stress applied to the tunnel oxide film 19 during the transfer of electrons can be dispersed and delayed, and the life of rewriting data can be improved.

Further, as described above, since the surface of the floating gate 18, particularly the sharp corner portion 18T can be formed in a substantially uniform state, the variation in tunnel current between memory cells can be reduced. Subsequently, the gate oxide film 12 formed in a region other than the region immediately below the floating gate 18 by, for example, hydrofluoric acid (for example, HF: H20 = 1: 25) is removed. In this etching, the etching may be completed halfway without removing the entire gate oxide film 12 except for the region immediately below the floating gate 18.

Further, as shown in FIG. 12, a CVD oxide film is deposited on the entire surface of the substrate by a chemical vapor deposition (CVD) method so as to cover the floating gate 18, and is formed by thermally oxidizing the surface. A tunnel oxide film 19 made of a thermal oxide film and having a thickness of about 300 ° is formed.
Next, a polysilicon film is formed at approximately 1500 ° and a tungsten silicide film (WSix film) is formed at approximately 1500 ° sequentially, and is patterned so as to remain from the upper portion to the side portion of the floating gate 18 via the tunnel oxide film 19. The control gate 20 as shown in FIG. 7 is formed. Then, impurity ions are implanted into the surface layer of the source region forming region through a resist film (not shown) having an opening on the source region 21 described later. Further, impurity ions are implanted into the surface layer of the drain region forming region through a resist film (not shown) having an opening on the drain region 22 described later. The heat treatment of the entire surface diffuses the impurity ions implanted into the surface layer of the substrate to form source / drain regions 21 and 22, thereby forming a split gate type flash memory as shown in FIG. You. The control gate 20 is not limited to the above-described laminated structure of the polysilicon film and the tungsten silicide film, but may be a single-layer film made of a polysilicon film.

As described above, in the present invention, by forming the sharp corner portion 18T on the upper portion of the floating gate 18 relatively uniformly, the sharp portion 57A as in the conventional device is formed.
The data (electrons) stored in the floating gate 18 is not transferred to the control gate 20 because the local erasing structure is not a local erasing structure only from a certain number of convex portions 57B.
When the electrons are extracted to the side, the movement path of the electrons in the tunnel oxide film 19 is less concentrated, and the tunnel current is increased, so that the erase time can be shortened. Further, the wear deterioration of the oxide film 19 caused by the stress applied to the tunnel oxide film 19 during the transfer of electrons can be dispersed and delayed, so that the data rewrite life can be improved and the tunnel current variation between memory cells can be reduced. Can be reduced.

[0034]

As described above, according to the present invention, in the polysilicon film constituting the floating gate, the grain size of the upper polysilicon film is smaller than the grain size of the lower polysilicon film and is relatively uniform. Therefore, when a floating gate made of the polysilicon film is formed, it is possible to reduce the variation of the convex portion at the upper corner. Therefore, it is possible to suppress the erasing structure from being concentrated only at a certain number of convex portions which are particularly sharp as in the conventional device. Therefore, when data (electrons) stored in the floating gate are pulled out to the control gate side, the movement path of the electrons in the tunnel oxide film is less concentrated, and the tunnel current increases, so that the erasing time can be shortened. In addition, by improving the erasing efficiency, a voltage value used in a writing operation, an erasing operation, or the like can be reduced. Further, the wear deterioration of the oxide film caused by the stress applied to the tunnel oxide film during the transfer of electrons can be dispersed and delayed, and the life of rewriting data can be improved.

Further, since a substantially uniform convex portion is formed on the floating gate, it is possible to reduce a variation in tunnel current between memory cells.

[Brief description of the drawings]

FIG. 1 is a first sectional view illustrating a method for manufacturing a nonvolatile semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a second sectional view illustrating the method for manufacturing the nonvolatile semiconductor memory device according to the first embodiment of the present invention.

FIG. 3 is a third sectional view illustrating the method for manufacturing the nonvolatile semiconductor memory device according to the first embodiment of the present invention.

FIG. 4 is a fourth sectional view illustrating the method for manufacturing the nonvolatile semiconductor memory device according to the first embodiment of the present invention.

FIG. 5 is a fifth sectional view illustrating the method for manufacturing the nonvolatile semiconductor memory device according to the first embodiment of the present invention.

FIG. 6 is a sixth sectional view illustrating the method for manufacturing the nonvolatile semiconductor memory device according to the first embodiment of the present invention.

FIG. 7 is a first sectional view illustrating the method for manufacturing the nonvolatile semiconductor memory device according to the second embodiment of the present invention.

FIG. 8 is a second sectional view illustrating the method for manufacturing the nonvolatile semiconductor memory device according to the second embodiment of the present invention.

FIG. 9 is a third sectional view illustrating the method for manufacturing the nonvolatile semiconductor memory device according to the second embodiment of the present invention.

FIG. 10 is a fourth sectional view illustrating the method for manufacturing the nonvolatile semiconductor memory device according to the second embodiment of the present invention.

FIG. 11 is a fifth sectional view illustrating the method for manufacturing the nonvolatile semiconductor memory device according to the second embodiment of the present invention.

FIG. 12 is a sixth sectional view illustrating the method for manufacturing the nonvolatile semiconductor memory device according to the second embodiment of the present invention.

FIG. 13 is a first cross-sectional view illustrating a method for manufacturing a conventional nonvolatile semiconductor memory device.

FIG. 14 is a second sectional view illustrating the method for manufacturing the conventional nonvolatile semiconductor memory device.

FIG. 15 is a third sectional view illustrating the method for manufacturing the conventional nonvolatile semiconductor memory device.

FIG. 16 is a fourth sectional view illustrating the method for manufacturing the conventional nonvolatile semiconductor memory device.

FIG. 17 is a fifth sectional view illustrating the method for manufacturing the conventional nonvolatile semiconductor memory device.

FIG. 18 is a schematic perspective view showing a state of formation of a conventional floating gate.

FIG. 19 is a cross-sectional view for explaining an erasing operation of a conventional nonvolatile semiconductor memory device.

Claims (8)

[Claims] 1. A nonvolatile semiconductor memory device having a floating gate formed on a gate oxide film on a semiconductor substrate and a control gate formed so as to overlap one end of the floating gate via a tunnel oxide film. And a grain size of at least an upper polysilicon film of the polysilicon film forming the floating gate is smaller than a grain size of a lower polysilicon film. 2. A nonvolatile semiconductor memory device comprising: a floating gate formed on a gate oxide film on a semiconductor substrate; and a control gate formed so as to overlap one end of the floating gate via a tunnel oxide film. Wherein the polysilicon film constituting the floating gate is formed by heat-treating an amorphous silicon film in which at least an upper polysilicon film and a lower polysilicon film are formed at different deposition temperatures. Non-volatile semiconductor storage device. 3. A floating gate having a sharp corner formed on a gate oxide film on a semiconductor substrate and a control gate formed so as to overlap one end of the floating gate with a tunnel oxide film interposed therebetween. Wherein the grain size of the upper polysilicon film, in which at least the sharp corner is formed, is smaller than the grain size of the lower polysilicon film in the polysilicon film forming the floating gate. A nonvolatile semiconductor memory device characterized by being small. 4. A floating gate having a sharp corner formed on a gate oxide film on a semiconductor substrate and a control gate formed to overlap one end of the floating gate with a tunnel oxide film interposed therebetween. Wherein the polysilicon film forming the floating gate is formed at a deposition temperature at which at least the upper polysilicon film and the lower polysilicon film at which the sharp corners are formed are formed. A non-volatile semiconductor memory device formed by heat-treating a formed amorphous silicon film. 5. A floating gate is formed by patterning a polysilicon film formed on a gate oxide film on a semiconductor substrate, and then a control gate is formed so as to overlap one end of the floating gate via a tunnel oxide film. The method of forming a polysilicon film forming the floating gate, wherein at least the upper polysilicon film and the lower polysilicon film are formed at different deposition temperatures at different temperatures. Forming a polycrystalline silicon film by heat-treating the amorphous silicon film after forming the amorphous silicon film. 6. An oxidation-resistant film having an opening formed on a polysilicon film formed on a gate oxide film on a semiconductor substrate, and then selectively oxidizing the polysilicon film using the oxidation-resistant film as a mask. Forming a selective oxide film, etching the polysilicon film using the selective oxide film as a mask to form a floating gate having a sharp corner on the upper portion thereof, and then forming a tunnel oxide on one end of the floating gate. In a method for manufacturing a nonvolatile semiconductor memory device having a step of forming a control gate so as to overlap with a film interposed therebetween, a step of forming a polysilicon film forming the floating gate includes an upper layer in which at least the sharp corner portion is formed. After forming an amorphous silicon film at different film forming temperatures of the polysilicon film and the lower polysilicon film, Method of manufacturing a nonvolatile semiconductor memory device characterized by comprising the step of multi-crystallized by heat-treating the fastest silicon film. 7. After forming a lower amorphous silicon film at a first film forming temperature on a semiconductor substrate via a gate oxide film, the upper layer is formed at a second film forming temperature lower than the first film forming temperature. A step of forming an amorphous silicon film, a step of heat-treating the upper and lower amorphous silicon films and polycrystallizing to form a polysilicon film, and a step of forming a floating gate by patterning the polysilicon film. A step of forming a tunnel oxide film so as to cover the floating gate, and a step of forming a control gate so as to overlap one end of the floating gate via the tunnel oxide film. Production method. 8. After forming a lower amorphous silicon film at a first film forming temperature on a semiconductor substrate via a gate oxide film, an upper layer is formed at a second film forming temperature lower than the first film forming temperature. Forming an amorphous silicon film, heat-treating the upper and lower amorphous silicon films and polycrystallizing to form a polysilicon film, and forming a silicon nitride film having an opening on the polysilicon film. Selectively oxidizing the surface of the polysilicon film using the silicon nitride film as a mask to form a selective oxide film; and etching the polysilicon film using the selective oxide film as a mask after removing the silicon nitride film. Forming a floating gate by oxidizing the entire surface to cover the selective oxide film and the floating gate. A step of forming, method for manufacturing a nonvolatile semiconductor memory device characterized by a step of forming the floating gate end control gate so as to overlap through a tunnel oxide film on the.