JPH11284128A - Protection circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To raise the junction breakdown voltage of an impurity diffused layer of a protection element constituting a protection circuit and obtain a protection circuit having a small element area. SOLUTION: Impurity diffused layers 22, 23 of a protection circuit are enclosed with wells 24, 25 of the same conductivity type to raise the junction withstand voltage of a protection element and each formed into a regular polygonal shape to disperse the current path during the conduction, thereby raising the junction withstand voltage. If hence the size of the protection element is reduced, the electrostatic damage(ESD) resistance can be ensured. Resistance elements of the protection circuit are formed with wiring layers 26, 27 and through-holes 28, 29 to reduce the element area of the resistance element.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a protection circuit for a semiconductor integrated circuit, and more particularly, to an ESD (electrostatistic) circuit.
c discharge damage).

[0002]

2. Description of the Related Art With the recent miniaturization of semiconductor manufacturing technology, the withstand voltage of MOS transistors and the like constituting a semiconductor integrated circuit tends to decrease. When static electricity is applied to the input / output terminals of such a semiconductor integrated circuit, the MOS inside the circuit becomes
Usually, a protection circuit is provided at an input / output terminal of a semiconductor integrated circuit because a transistor or the like may be destroyed.
Hereinafter, a conventional protection circuit will be described as an example.

FIG. 6 shows an example in which a protection circuit is constituted by a diode, which is hereinafter referred to as a first prior art. Protection circuit 60
Is provided between the input terminal 3 and the internal circuit 7,
A diode 4 ′ connected in series between a power supply line (V _DD ) 1 and a ground power supply line (GND, hereinafter referred to as a ground line) 2
And 5 'and a resistor 6. Input terminal 3
Then, when a positive surge voltage (higher voltage than the power supply line 1) due to static electricity is applied, the diode 5 'conducts and the voltage applied to the input terminal 3 is reduced. When a negative surge voltage due to static electricity (a voltage lower than that of the ground line 2) is applied to the input terminal 3, the diode 4 'is turned on to increase the voltage applied to the input terminal 3. In this way, the input voltage outside the specified range is kept within the specified range, and the destruction of the internal circuit 7 is prevented. The resistor 6 is provided to alleviate abrupt application of a voltage to an internal circuit when a surge voltage due to static electricity is applied to the input terminal 3. A protection circuit using a diode is disclosed in JP-A-7-176.
No. 735, etc.

FIG. 7A shows a sectional view of the diode 4 'or 5', and FIG. 7B shows a plan view. In FIG. 7B, the cross section taken along the line AA ′ is FIG. 7A, and the range indicated by BB ′ is one diode. In the case of this conventional technique, a P well 74 is formed in a P-type semiconductor substrate 71, and an N + diffusion layer 72 and a P + diffusion layer 73 are formed therein. A wiring layer 75 is connected to the N + diffusion layer 72 via a through hole 77, and a wiring layer 76 is connected to the P + diffusion layer 73.
Are connected via a through hole 78. Wiring layer 7
5 is connected to the input terminal 3 in the case of the diode 4 ',
In the case of the diode 5 ′, it is connected to the power supply line 1. The wiring layer 76 is connected to the ground line 2 in the case of the diode 4 ′, and is connected to the input terminal 3 in the case of the diode 5 ′. That is, the wiring layer 75 becomes an anode-side electrode,
The wiring layer 76 becomes a cathode-side electrode.

Further, the diode serving as a protection circuit needs to have an impedance lower than that of the internal circuit so that a current due to static electricity does not flow into the internal circuit. Therefore, the P-type diffusion layer and the N-type diffusion layer constituting the diode are required. Is a high concentration (P +, N +).

FIG. 8 shows an example in which a protection circuit is constituted by transistors, which will be hereinafter referred to as a second prior art. Protection circuit 80
Means that the first prior art diodes 4 'and 5'
The other parts are the same except that they are changed to T2 type NMOS transistors 4 ″ and 5 ″. Here, the VT2-type NMOS transistor is a transistor having a higher threshold VT than a normal NMOS transistor (VT ≒
12V), which does not operate at a normal input voltage, and thus is suitable for a protection circuit. In the case of the prior art, when a positive or negative surge voltage due to static electricity is applied to the input terminal 3, one of the transistors 4 ″ and 5 ″ is turned on to protect the internal circuit. A protection circuit using a VT2 type NMOS transistor is disclosed in Japanese Unexamined Patent Publication No. Hei 5-326865.
No., etc.

FIG. 9 is a sectional view of VT2 type NMOS transistors 4 ″ and 5 ″. In the case of this conventional technique, a P well 97 is formed in a P-type semiconductor substrate 91, and N + diffusion layers 92a to 92c are formed therein. Then, the wiring layer 93 is formed in the N + diffusion layer 92a through holes 96.
a, and a wiring layer 94 is connected to the N + diffusion layer 92b through a through hole 96b.
c is connected to a wiring layer 95 via a through hole 96c. The wiring layer 93 is connected to an input terminal, the wiring layer 94 is connected to a ground line, and the wiring layer 95 is connected to a power supply line. That is, the transistor 4 ″ is formed using the N + diffusion layer 92a as a drain and the N + diffusion layer 92b as a source, and the transistor 5 ″ is formed using the N + diffusion layer 92a as a drain and the N + diffusion layer 92c as a source. In the VT2 type NMOS transistor, a wiring layer 93 formed of aluminum
Replaces the gate electrode, and an insulating film (not shown) having the same thickness as the element isolation film formed between the wiring layer 93 and the N + diffusion layer 92a becomes the gate insulating film.

In recent years, integrated circuits of the hot-swap type have been increasing. As a hot-swap integrated circuit, for example, there is an IC card or the like that can be inserted and removed while the apparatus is powered on. Although a protection circuit used for the hot-swap integrated circuit is not shown, the protection circuit 60 shown in FIG. 6 is obtained by removing the diode 5 ′. That is, in the protection circuit of the hot-swap integrated circuit, no current path to the power supply line 1 is formed.

In a hot-swappable integrated circuit, a protection element for directly connecting an input terminal and a power supply line cannot be provided. The reason for this is that, in the case of a hot-swappable integrated circuit, an input signal is applied to an input terminal before power is supplied from the device to a power supply line of the hot-swappable integrated circuit, particularly when the integrated circuit is inserted into a certain device. Because things can happen. In such a case, the voltage applied to the input terminal may be higher than that of the power supply line. If the protection circuit 60 of FIG.
Raises the potential of. The power supply line 1 is connected to the internal circuit 7
If the power supply line is shared with the power supply line, there is a possibility that the internal circuit may malfunction and output incorrectly. for that reason,
In the protection circuit of the hot-swappable integrated circuit, a protection element such as a diode cannot be provided between the input terminal and the power supply line.

[0010]

In the first and second prior arts described above, the high concentration diffusion layer is in direct contact with the well of the opposite conductivity type. Therefore, the junction withstand voltage of the protection circuit itself is not so high, and the protection circuit is destroyed when static electricity is applied. As a result, there is a high possibility that the internal circuit is also destroyed.

In the diode protection circuit shown in FIG. 7B, a current path of the diode is formed between the N + diffusion layer 72 and the P + diffusion layer 73. Therefore, the current when the diode is conducting is concentrated at this one location, and there is a high possibility that junction breakdown will occur at this location. A diode as a protection element needs to have a small element area in order to increase the response of the protection circuit to the application of static electricity. Therefore, if priority is given to responsiveness, the diffusion layer becomes smaller (that is, the width of the current path becomes smaller).
Further, there is a problem that the junction breakdown voltage is reduced, and if the breakdown voltage is prioritized, the element area is increased.

Further, the resistor 6 used in the first and second prior arts is usually formed of polysilicon. Therefore, there is a problem that not only the element area of the protection circuit increases but also a mask and a process for forming high-resistance polysilicon are required, and the number of manufacturing steps is increased.

Furthermore, the protection circuit used in the hot-swap integrated circuit has no current path to the power supply line as described above. When static electricity is actually applied, the potentials of the power supply line and the ground line may not be determined. Therefore, a current path is usually formed to both the power supply line and the ground line. Therefore, when there is only a current path to the ground line, there is a higher possibility that the internal circuit is destroyed than when there is a current path to the power supply line. It is also conceivable to provide a power supply line for the protection circuit and the internal circuit in separate systems to prevent malfunction of the internal circuit. However, in this case, the element area of the integrated circuit increases.

Therefore, the present invention provides a protection circuit that solves the above problem.

[0015]

According to the present invention, in the high-concentration impurity diffusion layer forming the protection circuit, the high-concentration impurity diffusion layer connected to the input / output terminal is the same conductivity type low-concentration impurity diffusion layer. Since the high concentration impurity diffusion layer formed therein and connected to the power supply line is formed in the same conductivity type impurity diffusion layer, the ESD resistance is increased.

Further, the diode forming the protection element is
A first impurity diffusion layer of a first conductivity type and a second impurity layer of a second conductivity type formed continuously around the impurity diffusion layer of the first conductivity type;
, The current path of the diode is dispersed, and the junction breakdown voltage is increased.

Further, the resistance element includes a first wiring of a first wiring layer connected to the first node, a first through hole having one end connected to the first wiring, and a first through hole. A second wiring of a second wiring layer connected to the other end of the hole;
A second through hole having one end connected to the wiring of
And the third wiring of the first wiring layer connected to the other end of the through hole and to the second node, thereby reducing the element area of the resistance element.

Further, when the protection circuit is formed by a diode, a first diode having an anode connected to the input / output terminal and a cathode connected to the ground line, and a first diode having an anode connected to the power supply line and having a cathode connected to the first diode And a second diode connected to the cathode of the power supply line, a current path to the power supply line is formed while eliminating a protection element directly connected from the input / output terminal to the power supply line.

[0019]

Embodiments of the present invention will be described below with reference to the drawings. In the following description,
The same parts as those in the first and second prior arts are denoted by the same reference numerals, and description thereof will be omitted.

FIG. 1 shows a first embodiment of the present invention. In the protection circuit 10 of the present embodiment, the cathode of the diode 4 is connected to the ground line 2, and the anode is connected to the input terminal 3 to form a current path to the ground line 2. Also, the cathode of the diode 5 is connected to the cathode of the diode 4, the anode is connected to the power supply line 1,
A current path to the power supply line 1 is formed. In such a configuration, there is no protection element directly connected to the power supply line 1 from the input terminal 3, but a current path to the power supply line 1 is formed. Therefore, even when used as a protection circuit for a hot-swappable integrated circuit, it has high ESD resistance. In addition,
When a current path is formed to power supply line 1, diode 4 enters a punch-through state.

FIG. 2 shows a second embodiment of the present invention.
FIG. 2 shows a cross-sectional view and a plan view of a diode 4 or 5 according to the first embodiment. Referring to the cross-sectional view of FIG.
N + diffusion layer 22 and P + diffusion layer 2
3 are formed, the N + diffusion layer 22 is surrounded by an N well 24, and the P + diffusion layer 23 is surrounded by a P well 25. Then, the N + diffusion layer 22 and the wiring layer 26 are
8, and the P + diffusion layer 23 and the wiring layer 27 are connected via a through hole 29. Wiring layer 26
Is connected to the input terminal 3 in the case of the diode 4 and to the first power supply line 1 in the case of the diode 5. The left and right wiring layers 27 are connected to the ground line 2 in the case of both the diode 4 and the diode 5. That is,
The wiring layer 26 serves as an anode electrode, and the wiring layer 27 serves as a cathode electrode.

According to the present embodiment, the high-concentration diffusion layer is surrounded by the same conductivity type well having a lower impurity concentration than the high-concentration diffusion layer.
The junction withstand voltage of the junction surface (that is, the junction surface between the P well and the N well) is improved. The wiring layer 27 is a first-layer wiring, and the wiring layer 26 is a second-layer wiring, and is formed of aluminum.

FIG. 2B is a plan view of the diode 4 or 5. In the figure, the section taken along the line AA ′ is FIG. 2A, and the range indicated by BB ′ is one diode. In the present embodiment, as shown, the P + diffusion layer 2
3 are continuously formed around the N + diffusion layer 22 so as to surround the N + diffusion layer 22. In the drawing, the N + diffusion layer 2
2, an N well 24 and a P well 25 are formed in a regular polygon, and a region outside the P well 25 becomes a P + diffusion layer 23. The contact region 28 'for the N + diffusion layer 22 is
A plurality are formed along the inside of the outer shape of the N + diffusion layer 22, and similarly, a contact region 29 ′ for the P + diffusion layer 23 is formed.
Are formed along the inside of the outer shape of the P + diffusion layer 23. In other words, the contact region 29 'is
5 is formed along the outside of the outer shape.

The number of polygons forming the N + diffusion layer 22, the N well 24, and the P well 25 is preferably as large as possible and ideally a circle. This is to uniformly distribute the current path from the anode to the cathode. Therefore, when the contact regions 29 'are arranged at the minimum pitch based on the design rule, the polygon is determined so as to be as close as possible to a circle. By doing so, the current paths are dispersed not only in the four directions (up, down, left and right) but also in the oblique directions, so that the junction breakdown voltage is further increased. Therefore, the junction withstand voltage can be ensured even if the element area is reduced in order to enhance the response to the application of static electricity.

FIG. 3 shows a third embodiment of the present invention.
2 shows a sectional view and a plan view of the resistor 6 in FIG. FIG. 3 (a)
Referring to the cross-sectional view of FIG. 5, the resistor 6 is formed as a portion 30 surrounded by a dotted line in the figure. That is, the second layer wiring 31 connected to the input terminal 3 is connected to the first layer wiring 33 via the through hole 35 and further connected to the second layer wiring 32 via the through hole 36 to form a resistor. I have.
A resistor having such a structure is hereinafter referred to as a through-hole resistor. The through holes 35 and 36 are provided in rows in the wiring layers 31 and 32 as shown in the plan view of FIG. The first layer wirings 33 and 34 and the second
The layer wirings 31, 32 are formed of aluminum, and the through holes 35, 36 are also filled with aluminum. The resistance value per through hole is about 0.5Ω.

Here, considering the case where the through-hole resistor 30 is not provided, the second-layer wiring 31 usually wired from the input terminal is not interrupted on the way, and It is connected to the first layer wiring 34 constituting the circuit. Then, the N +
It is connected to the diffusion layer 39 via the through hole 38. Usually, there is a margin for forming a guard ring or the like between the protection circuit and the internal circuit, and the second-layer wiring extends above this. Therefore, the through-hole resistor 30 according to the present embodiment does not substantially require an element area for providing a resistor or can be formed with a small element area by utilizing the above-mentioned margin. Further, since the resistance is formed using the wiring layer as it is, the manufacturing process does not substantially increase.

FIG. 4 shows a fourth embodiment of the present invention. According to the above-described present invention, the protection circuit 1 is different from the prior art.
0, the element area of the PMOS off transistor 8 and N
By providing the MOS off transistor 9, the ESD resistance can be further increased. When the protection circuit 40 of FIG. 4 is used as a protection circuit of a hot-swap type semiconductor integrated circuit, the configuration is such that the PMOS off transistor 8 is not provided.

FIG. 5 shows a fifth embodiment of the present invention. In this embodiment mode, an equivalent circuit diagram of the protection circuit is shown in FIG.
This is the same as the second prior art shown in FIG. The inventor
When an ESD test was performed on the ground line (power supply line) with the reference of 0 V with respect to the prior art, the junction withstand voltage when a positive surge voltage was applied to the input terminal was as follows:
The result was lower than when a negative surge voltage was applied to the input terminal. That is, the P well 9 in FIG.
7 and the junction breakdown voltage when a reverse current flows through the N + diffusion layer 92a is reduced. However, according to the present embodiment, as shown in FIG. 5A, the N + diffusion layer 52a constituting the VT2-type NMOS transistor has the N well 58.
Surrounded by Therefore, since the N well 58 is connected to the P well 57 and the PN junction, the junction breakdown voltage therebetween is improved. Therefore, the VT2 type NMOS
A high ESD resistance can be obtained even in a protection circuit using a transistor.

In the operation of the protection circuit, a reverse current may flow through P well 57 and N + diffusion layer 52b or 52c. Therefore, as shown in FIG.
P well 5 also for N + diffusion layers 52b and 52c.
By enclosing with 8, an even higher ESD resistance can be obtained.

In each of the embodiments described above,
Although the example in which the wiring layer is formed of aluminum has been described, the present invention is not limited to this, and may be formed of copper, tungsten, or the like.

[0031]

According to the present invention described above, the high-concentration diffusion layer of the diode or transistor forming the protection element of the protection circuit is surrounded by the well of the same conductivity type, so that the well and the substrate of the opposite conductivity type are surrounded. Junction withstand voltage is improved.
Therefore, a high ESD resistance is obtained.

In a protection circuit using a diode, since a contact region is formed along a PN junction surface on which a diode is formed, a current path is dispersed and the withstand voltage of the protection element is improved. In this case, by forming the PN junction surface in a regular polygon, the length of the plurality of current paths becomes uniform, so that the withstand voltage is further improved. Therefore, a sufficient withstand voltage can be obtained even if the element area of the diode is reduced in order to improve the response, so that the element area of the protection circuit can be reduced. According to the technical idea of the present invention, the contact to the N + diffusion layer may be provided at the center of the diffusion layer.

Further, by forming the resistance of the protection circuit with a through-hole resistance, the step of forming the conventional resistance using polysilicon can be omitted, and the element area of the protection circuit can be reduced.

Furthermore, since the current path to the power supply line is not formed directly from the input terminal, when a protection circuit formed by a diode is used in a hot-swap integrated circuit, a high E is obtained.
SD tolerance is obtained.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a protection circuit according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view and a plan view of a protection circuit according to a second embodiment of the present invention.

3A and 3B are a cross-sectional view and a plan view of a through-hole resistor according to a third embodiment of the present invention.

FIG. 4 is a circuit diagram of a protection circuit according to a fourth embodiment of the present invention.

FIG. 5 is a sectional view of a protection circuit according to a fifth embodiment of the present invention.

FIG. 6 is a circuit diagram of a protection circuit according to a first related art.

FIG. 7 is a cross-sectional view and a plan view of a protection circuit according to a first related art.

FIG. 8 is a circuit diagram of a second prior art protection circuit.

FIG. 9 is a sectional view of a second prior art protection circuit.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Power supply line (V _DD ) 2 Ground line (GND) 3 Input terminal 4, 5, 4 ', 5' Diode 4 ", 5" VT2 type NMOS transistor 6 Resistance element 7 Internal circuit 8 PMOS off transistor 9 NMOS off Transistor 10, 40, 60, 80 Protection circuit 21, 51, 71, 91 P-type semiconductor substrate 22, 39, 52a-c, 72, 92a-c N + diffusion layer 23, 73P + diffusion layer 24, 58 N well 25, 57, 74, 97 P well 26, 31, 32, 75 Second layer wiring layer 27, 33, 34, 53 to 55, 76, 93 to 95
First wiring layer 28, 29, 35 to 38, 56 a to c, 77, 78, 9
6a-c Through-hole 28 ', 29' Contact area 30 Through-hole resistance

Claims (12)

[Claims] In a protection circuit connected between an input / output terminal of a semiconductor integrated circuit and an internal circuit, a high-concentration impurity diffusion layer connected to the input / output terminal is a low-concentration impurity diffusion layer of the same conductivity type. A protection circuit, wherein a high-concentration impurity diffusion layer formed therein and connected to a power supply line is formed in the same conductivity type impurity diffusion layer. 2. A protection circuit comprising a transistor connected between an input / output terminal of a semiconductor integrated circuit and an internal circuit, wherein a high-concentration impurity diffusion layer connected to the input / output terminal has a low conductivity type of the same conductivity type. A protection circuit formed in a high concentration impurity diffusion layer. 3. A protection circuit connected between an input / output terminal of a semiconductor integrated circuit and an internal circuit, a first diode having an anode connected to the input / output terminal and a cathode connected to a ground line; And a second diode having a cathode connected to a power supply line and a cathode connected to the cathode of the first diode. 4. A first wiring of a first wiring layer connecting the input / output terminal to a first through hole;
A second wiring of a second wiring layer that connects from the through hole to the second through hole, and a third wiring of the first wiring layer that connects from the second through hole to the internal circuit. 4. The protection circuit according to claim 3, further comprising a resistance element composed of: 5. The first to third wiring layers and the first to third wiring layers.
5. The protection circuit according to claim 4, wherein said second through hole is formed of aluminum, copper or tungsten. 6. A first impurity diffusion layer of a first conductivity type, and a second impurity diffusion layer of a second conductivity type continuously formed around the impurity diffusion layer of the first conductivity type. Diode. 7. The first impurity diffusion layer and the second impurity diffusion layer.
7. The diode according to claim 6, wherein the impurity diffusion layer is formed in a concentric circle. 8. The first impurity diffusion layer and the second impurity diffusion layer.
7. The diode according to claim 6, wherein said impurity diffusion layer has a center point formed by the same regular polygon. 9. A third impurity diffusion layer of the first conductivity type having an impurity concentration lower than that of the first impurity diffusion layer is formed around the first impurity diffusion layer, and the third impurity diffusion layer is formed. 7. A fourth impurity diffusion layer of the second conductivity type having an impurity concentration lower than that of the second impurity diffusion layer is formed between the second impurity diffusion layer and the second impurity diffusion layer. 7. The diode according to 7 or 8. 10. A plurality of contact regions are formed in the second impurity diffusion layer along a side of the outer shape of the second impurity diffusion layer near the first impurity diffusion layer. The diode according to claim 6, 7, 8, or 9. 11. The semiconductor device according to claim 7, wherein a plurality of contact regions are formed in the first impurity diffusion layer along the inside of the outer shape of the first impurity diffusion layer.
The diode according to 9 or 10. 12. A resistive element connected between a first node and a second node, the first element being a first wiring of a first wiring layer connected to the first node; A first through hole having one end connected to the first wiring, a second wiring of a second wiring layer connected to the other end of the first through hole,
A second through hole having one end connected to the second wiring, and a third through hole of the first wiring layer connected to the other end of the second through hole and connected to the second node. A resistive element comprising a wiring.