JPH11284191A5 - - Google Patents

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Publication number
JPH11284191A5
JPH11284191A5 JP1998084656A JP8465698A JPH11284191A5 JP H11284191 A5 JPH11284191 A5 JP H11284191A5 JP 1998084656 A JP1998084656 A JP 1998084656A JP 8465698 A JP8465698 A JP 8465698A JP H11284191 A5 JPH11284191 A5 JP H11284191A5
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Japan
Prior art keywords
semiconductor film
formation region
channel formation
region
polycrystalline semiconductor
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JP1998084656A
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Japanese (ja)
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JPH11284191A (en
JP3788021B2 (en
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Priority claimed from JP08465698A external-priority patent/JP3788021B2/en
Publication of JPH11284191A publication Critical patent/JPH11284191A/en
Publication of JPH11284191A5 publication Critical patent/JPH11284191A5/ja
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Description

【発明の名称】薄膜トランジスタおよびその製造方法[Title of Invention] Thin film transistor and its manufacturing method

【0011】
このような構成の薄膜トランジスタの製造方法では、たとえば、前記チャネル形成領域を形成するためのアモルファス半導体膜に結晶化処理を行って前記基板の面外方向に柱軸を向ける柱状構造の多結晶半導体膜を形成した後、該多結晶半導体膜をパターニングして柱軸に略平行な側端面を露出させ、しかる後に、前記ゲート絶縁膜および前記ゲート電極を順次形成する(請求項5)。
[0011]
In a method for manufacturing a thin film transistor having such a configuration, for example, a crystallization process is performed on an amorphous semiconductor film for forming the channel formation region to form a polycrystalline semiconductor film having a columnar structure with its column axis directed in an out-of-plane direction of the substrate, and then the polycrystalline semiconductor film is patterned to expose side end faces approximately parallel to the column axis, and thereafter the gate insulating film and the gate electrode are formed in this order (claim 5).

Claims (8)

基板上にソース・ドレイン領域の一方となる第1領域と他方となる第2領域との間にチャネルを形成するチャネル形成領域、および該チャネル形成領域に対してゲート絶縁膜を介して対峙するゲート電極を有する薄膜トランジスタであって、
前記チャネル形成領域は、アモルファス半導体膜に対する結晶化処理により形成されて前記基板の面外方向に柱軸を向ける柱状構造の多結晶半導体膜から構成され、
前記ゲート電極は、前記チャネル形成領域を構成する多結晶半導体膜の柱軸に略平行な側端面に対して前記ゲート絶縁膜を介して対峙していることを特徴とする薄膜トランジスタ。
A thin film transistor having a channel formation region on a substrate, the channel formation region forming a channel between a first region which is one of source and drain regions and a second region which is the other of source and drain regions, and a gate electrode facing the channel formation region via a gate insulating film,
the channel formation region is formed by a polycrystalline semiconductor film having a columnar structure formed by a crystallization process on an amorphous semiconductor film, the columnar axis of which is oriented in an out-of-plane direction of the substrate,
The thin film transistor is characterized in that the gate electrode faces a side end face of the polycrystalline semiconductor film constituting the channel formation region, the side end face being substantially parallel to a column axis, via the gate insulating film.
請求項1において、前記第1領域および前記第2領域は、前記チャネル形成領域を構成する多結晶半導体膜の下層側および上層側にそれぞれ形成された下層側半導体膜および上層側半導体膜から構成されていることを特徴とする薄膜トランジスタ。2. The thin film transistor according to claim 1, wherein the first region and the second region are composed of a lower semiconductor film and an upper semiconductor film formed on the lower and upper sides, respectively, of a polycrystalline semiconductor film constituting the channel formation region. 請求項2において、前記チャネル形成領域を構成する多結晶半導体膜と前記上層側半導体膜とは、同一のパターニング形状を有していることを特徴とする薄膜トランジスタ。3. A thin film transistor according to claim 2, wherein the polycrystalline semiconductor film constituting the channel forming region and the upper semiconductor film have the same patterning shape. 請求項1ないし3のいずれかにおいて、前記チャネル形成領域を構成する多結晶半導体膜は、チャネルを形成する側端面が前記下層側半導体膜の形成領域上に位置し、
当該多結晶半導体膜の側端面と前記下層側半導体膜との間には、これらの膜間にわずかに割り込む絶縁膜を有していることを特徴とする薄膜トランジスタ。
4. The polycrystalline semiconductor film constituting the channel formation region according to claim 1, wherein a side end face forming a channel is located on a formation region of the lower semiconductor film,
A thin film transistor characterized in that an insulating film is provided between the side end face of the polycrystalline semiconductor film and the lower semiconductor film, and is slightly sandwiched between these films.
請求項1または2に規定する薄膜トランジスタの製造方法であって、前記チャネル形成領域を形成するためのアモルファス半導体膜に結晶化処理を行って前記基板の面外方向に柱軸を向ける柱状構造の多結晶半導体膜を形成した後、該多結晶半導体膜をパターニングして柱軸に略平行な側端面を露出させ、しかる後に、前記ゲート絶縁膜および前記ゲート電極を順次形成することを特徴とする薄膜トランジスタの製造方法。3. A method for manufacturing a thin film transistor according to claim 1, wherein a crystallization process is performed on an amorphous semiconductor film for forming the channel formation region to form a polycrystalline semiconductor film having a columnar structure with its column axis directed in an out-of-plane direction of the substrate, and then the polycrystalline semiconductor film is patterned to expose side end faces approximately parallel to the column axis, and thereafter the gate insulating film and the gate electrode are formed in this order. 請求項3に規定する薄膜トランジスタの製造方法であって、前記チャネル形成領域および前記上層側半導体膜を形成するための各半導体膜をこの順に形成した後、該2つの半導体膜を一括してパターニングすることを特徴とする薄膜トランジスタの製造方法。4. A method for manufacturing a thin film transistor as defined in claim 3, characterized in that after forming semiconductor films for forming the channel formation region and the upper layer side semiconductor film in this order, the two semiconductor films are patterned collectively. 請求項4に規定する薄膜トランジスタの製造方法であって、前記下層側半導体膜および前記絶縁膜をこの順に形成した後、該絶縁膜を所定の形状にパターニングした後に、前記基板の全面に前記チャネル形成領域を形成する前記多結晶半導体膜を形成し、しかる後に、当該多結晶半導体膜をパターニングすることを特徴とする薄膜トランジスタの製造方法。5. A method for manufacturing a thin film transistor as defined in claim 4, characterized in that after forming the lower layer side semiconductor film and the insulating film in this order, the insulating film is patterned into a predetermined shape, the polycrystalline semiconductor film that forms the channel formation region is formed on the entire surface of the substrate, and then the polycrystalline semiconductor film is patterned. 基板上にソース・ドレイン領域の一方となる第1領域と他方となる第2領域との間にチャネルを形成するチャネル形成領域、および該チャネル形成領域に対してゲート絶縁膜を介して対峙するゲート電極を有する薄膜トランジスタであって、
前記チャネル形成領域は、前記基板の面外方向に柱軸を向ける柱状構造の多結晶半導体膜から構成され、
前記ゲート電極は、前記チャネル形成領域を構成する多結晶半導体膜の柱軸に略平行な側端面に対して前記ゲート絶縁膜を介して対峙していることを特徴とする薄膜トランジスタ。
A thin film transistor having a channel formation region on a substrate, the channel formation region forming a channel between a first region which is one of source and drain regions and a second region which is the other of source and drain regions, and a gate electrode facing the channel formation region via a gate insulating film,
the channel formation region is made of a polycrystalline semiconductor film having a columnar structure with its column axis directed in an out-of-plane direction of the substrate,
The thin film transistor is characterized in that the gate electrode faces a side end face of the polycrystalline semiconductor film constituting the channel formation region, the side end face being substantially parallel to a column axis, via the gate insulating film.
JP08465698A 1998-03-30 1998-03-30 Thin film transistor and manufacturing method thereof Expired - Fee Related JP3788021B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP08465698A JP3788021B2 (en) 1998-03-30 1998-03-30 Thin film transistor and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP08465698A JP3788021B2 (en) 1998-03-30 1998-03-30 Thin film transistor and manufacturing method thereof

Publications (3)

Publication Number Publication Date
JPH11284191A JPH11284191A (en) 1999-10-15
JPH11284191A5 true JPH11284191A5 (en) 2004-08-05
JP3788021B2 JP3788021B2 (en) 2006-06-21

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Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4759598B2 (en) * 2007-09-28 2011-08-31 キヤノン株式会社 THIN FILM TRANSISTOR, MANUFACTURING METHOD THEREOF, AND DISPLAY DEVICE USING THE SAME
KR101796909B1 (en) * 2009-10-30 2017-12-12 가부시키가이샤 한도오따이 에네루기 켄큐쇼 Non-linear element, display device, and electronic device
KR101520024B1 (en) 2009-11-28 2015-05-14 가부시키가이샤 한도오따이 에네루기 켄큐쇼 Semiconductor device and method for manufacturing the same
CN115188830A (en) * 2022-07-27 2022-10-14 武汉华星光电技术有限公司 Thin film transistor with vertical structure and electronic device
CN119604027B (en) * 2023-09-06 2025-12-12 武汉华星光电技术有限公司 Semiconductor device, display panel and chip

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2546982B2 (en) * 1983-07-01 1996-10-23 セイコー電子工業株式会社 Thin film transistor
JPS60157260A (en) * 1984-01-26 1985-08-17 Seiko Instr & Electronics Ltd Vertical type thin film transistor
JPS63293881A (en) * 1987-05-26 1988-11-30 Ricoh Co Ltd Vertical mos-type thin film transistor
JPS63296378A (en) * 1987-05-28 1988-12-02 Toppan Printing Co Ltd Vertical thin-film transistor
JPH01283879A (en) * 1988-05-11 1989-11-15 Nippon Telegr & Teleph Corp <Ntt> Thin film semiconductor device and manufacture thereof
JPH07106588A (en) * 1993-10-04 1995-04-21 Mitsubishi Electric Corp Semiconductor device and manufacturing method thereof

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