JPH11284192A - Vertical thin film transistor and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve on-current by forming a channel in consideration of a crystal structure of a polycrystalline semiconductor film,
TFT that can improve source-drain breakdown voltage
And a method for producing the same. SOLUTION: In a TFT1, a channel forming region 3 is provided.
Is composed of a polycrystalline semiconductor film 301 having a columnar structure formed by a crystallization process on an amorphous semiconductor film and having a column axis A directed in an out-of-plane direction of the substrate 8. Gate electrode 7 is formed of polycrystalline semiconductor film 3 forming channel formation region 3.
01 faces the side surface 302 substantially parallel to the column axis A via the gate insulating film 6. Above and below the channel formation region 3, LDDs are formed at portions facing the side edges of the gate electrode 7.
With the regions 203 and 403, the source-drain breakdown voltage is high even if the channel length is short. Therefore, the polycrystalline semiconductor film 401 included in the channel formation region 3 may be thin.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal drive
The present invention relates to a thin film transistor (hereinafter, referred to as a TFT) used for driving an element, driving a sensor, and the like, and a method for manufacturing the same. More specifically, the present invention relates to a vertical TFT.

[0002]

2. Description of the Related Art In an active matrix substrate of a liquid crystal display device, as shown in FIG. 4A, a data line 90 made of a conductive film such as aluminum or tantalum is formed on a transparent substrate.
In addition, a pixel area defined by the scanning lines 91 is formed, and a liquid crystal capacitor 94 (liquid crystal cell) to which an image signal is input via the pixel switching TFT 30 exists. For the data line 90, the shift register 8
4, a data side drive circuit 82 including a level shifter 85, a video line 87, and an analog switch 86 is configured. For the scanning line 91, a scanning side driving circuit 83 including a shift register 88 and a level shifter 89 is configured. Note that a storage capacitor 93 is formed between the pixel region and the preceding scanning line 91, and this storage capacitor 93
The liquid crystal capacitor 94 has a function of improving charge retention characteristics.

In the driving circuits on the data side and the scanning side, as shown in FIG. 4B, an N-type TFT 10 and a P-type TF
A complementary TFT circuit is constituted by T20.
Such a complementary TFT circuit constitutes a shift register or the like with one stage or two or more stages.

The TFTs 10 and 20 for such a driving circuit
FIG. 5 shows the same as the pixel switching TFT 30.
As shown in (A) and (B), gate insulation is provided on the surface of the island-shaped silicon film 5A constituting the first source / drain region 2A, the channel formation region 3A, and the second source / drain region 4A. A film 6A is formed, and a gate electrode 7A formed on the surface of the gate insulating film 6A faces the channel forming region 3A via the gate insulating film 6A.

When manufacturing the TFT 1A having such a structure, a polycrystalline silicon film 5A (semiconductor film) formed on a substrate 8A is used. That is, in order to increase the operation speed of the drive circuit, it is necessary that the operation speed of the TFT be high. Therefore, a polycrystalline silicon film having high mobility is formed by using a high-temperature process,
Form FT. Therefore, conventionally, it is necessary to use expensive quartz glass that can withstand a high-temperature process as the substrate 8A, and there is a problem that an inexpensive glass substrate having a low strain point cannot be used.

Therefore, a polycrystalline silicon film having high mobility can be formed on an inexpensive glass substrate having a low strain point.
A low-temperature process of forming an amorphous silicon film on a substrate, subjecting the amorphous silicon film to crystallization treatment such as laser annealing to melt and solidify the amorphous silicon film, and growing crystal grains has been studied.

[0007]

However, when the crystal grains of the silicon film are grown by such a crystallization process,
The silicon film is deposited in the film deposition direction during film formation,
The polycrystalline semiconductor film has a columnar structure in which the column axis is oriented in a direction perpendicular to A. In the channel length direction (the direction indicated by the arrow CH), the channel is a grain boundary (shown by a vertical line B in the channel forming region 3A). .). As a result, even if the crystallinity of the silicon film is increased, TF
There is a problem that the ON current of T1A is not sufficiently improved.

Therefore, it is conceivable to increase the on-current by shortening the channel length. However, when the channel length is shortened, there is a problem that the withstand voltage between the source and the drain is reduced accordingly.

[0009] In view of the above problems, an object of the present invention is to provide:
It is an object of the present invention to provide a TFT capable of improving an on-current by forming a channel in consideration of a crystal structure of a polycrystalline semiconductor film and improving a withstand voltage between a source and a drain, and a manufacturing method thereof.

[0010]

In order to solve the above-mentioned problems, the present invention provides a first region serving as one of a source / drain region, a channel forming region composed of a polycrystalline semiconductor film, and a source / drain region. A second thin film transistor is formed in this order on a substrate, and a gate electrode faces a side end surface of the polycrystalline semiconductor film via a gate insulating film. A portion facing the side edge of the gate electrode between the side edge of the crystalline semiconductor film, and a side edge of the gate electrode between the second region and the side edge of the polycrystalline semiconductor film. An LDD region into which a low-concentration impurity is introduced or a semiconductor region into which an impurity is not introduced is formed on at least one of the opposing portions. ).

In the present invention, the polycrystalline semiconductor film may include:
Generally, a columnar structure having a column axis substantially parallel to the side end surface is provided (claim 2). That is, when a channel forming region is formed by a polycrystalline semiconductor film in which an amorphous semiconductor film is melt-solidified and crystal grains are grown by crystallization treatment such as laser annealing, electron beam annealing, lamp annealing, and solid phase growth method, In the formation region, a polycrystalline semiconductor film having a columnar structure in which the column axis is oriented in the film deposition direction when the semiconductor film is formed, that is, in the out-of-plane direction of the substrate. In accordance with the present invention, in accordance with the present invention, a vertical TFT is formed by making a gate electrode face a side end surface of a polycrystalline semiconductor film parallel to a column axis. Therefore, the direction parallel to the column axis is the direction of the channel length. Therefore, the mobility of the carrier is high because the channel does not cross the grain boundary in the direction of the channel length.
Therefore, in a TFT manufactured by a low-temperature process, on-current can be improved. However, in the vertical TFT configured as described above, the thickness of the polycrystalline semiconductor film forming the channel formation region becomes the channel length. Therefore, in order to secure the source-drain withstand voltage in the vertical TFT, it is necessary to increase the thickness of the polycrystalline semiconductor film forming the channel formation region, and therefore, a long time is required for the film formation process. However, in the present invention, in a vertical TFT,
A portion facing the side end of the gate electrode between the first region and the side end surface of the polycrystalline semiconductor film, and a portion between the second region and the side end surface of the polycrystalline semiconductor film. At least one of the portions facing the side edge of the gate electrode has a low concentration of L
A vertical TFT is formed into an LDD structure or an offset gate structure by forming a DD region or a semiconductor region into which impurities are not introduced. Therefore, even if the channel length is short in the vertical TFT, that is, even if the thickness of the polycrystalline semiconductor film forming the channel formation region is small, a sufficient source / drain breakdown voltage can be ensured. The time required for forming the film is short.

In manufacturing the vertical thin film transistor having the above-described structure, a crystallization process is performed on an amorphous semiconductor film for forming the channel formation region to form a columnar structure in which a column axis is oriented in an out-of-plane direction of the substrate. After forming the polycrystalline semiconductor film, the polycrystalline semiconductor film is patterned to expose a side end surface substantially parallel to the column axis, and then the gate insulating film and the gate electrode may be sequentially formed. 5).

In the present invention, when the first region and the second region are composed of a lower semiconductor film and an upper semiconductor film formed respectively on a lower layer side and an upper layer side of the polycrystalline semiconductor film, In at least one of the upper semiconductor film and the lower semiconductor film, an LDD region into which the low-concentration impurity is introduced or an impurity is introduced into a portion facing a side end of the gate electrode. It is sufficient to form a semiconductor region that is not present (claim 3).

In manufacturing a vertical thin film transistor having such a structure, after forming the channel forming region and the respective semiconductor films for forming the upper semiconductor film in this order, the two semiconductor films are collectively assembled. It is preferable to reduce the number of patterning steps by performing patterning (claim 6).

In the present invention, when the side end surface of the polycrystalline semiconductor film is located on a formation region of a lower semiconductor film in which the first region is formed, the side end surface of the polycrystalline semiconductor film is provided. It is preferable that an insulating film slightly intervening between these films is provided between the lower semiconductor film and the lower semiconductor film (claim 4). With this configuration, after the lower semiconductor film and the insulating film are formed in this order, the polycrystalline semiconductor film for forming the channel formation region is formed on the entire surface of the substrate. When patterning the semiconductor film, the insulating film serves as an etching stopper. Therefore, over-etching of the lower semiconductor film can be prevented.

[0016]

Embodiments of the present invention will be described with reference to the drawings. In addition, as each embodiment, FIG.
TFT for driving liquid crystal display device described with reference to FIG.
However, the TFT according to the present invention can be used in various fields such as a pixel switching TFT of a liquid crystal display device, and further, for driving an EL element or a sensor.

Embodiment 1 FIGS. 1A and 1B are a sectional view and a plan view of a TFT to which the present invention is applied, respectively.

1A and 1B, a TFT 1 according to the present embodiment is a TFT for a driving circuit formed by a low-temperature process on a substrate 8 made of a glass plate as a base of a liquid crystal panel. The TFT 1 has a high-concentration first source / drain region 2, a high-concentration second source / drain region 4, a channel forming region 3 for forming a channel, and a gate insulating film 6 for the channel forming region 3. This is the same as the conventional TFT 1 in that it has a gate electrode 7 facing through the TFT.

However, in this embodiment, the first source / drain region 2, the channel forming region 3, and the second source / drain region 2
The drain region 4 includes a lower semiconductor film 201 such as a doped silicon film formed on the surface of the substrate 8, a polycrystalline semiconductor film 301 such as a polycrystalline silicon film laminated on the surface of the lower semiconductor film 201, And an upper semiconductor film 401 such as a doped silicon film laminated on the surface of the polycrystalline semiconductor film 301.

The polycrystalline semiconductor film 301 constituting the channel forming region 3 has side end surfaces 302 and 402 on the lower semiconductor film 201, similarly to the upper semiconductor film 401. Here, between the side end surface 302 of the polycrystalline semiconductor film 301 constituting the channel forming region 3 and the lower semiconductor film 201, an insulating film 9 for an etching stopper slightly interrupting between these films is formed. I have.

In the present embodiment, the polycrystalline semiconductor film 301 forming the channel forming region 3 and the upper semiconductor film 401 including the second source / drain region 4 are patterned at once as described later. Therefore, they have the same patterning shape.

A gate insulating film 6 made of a silicon oxide film or the like is formed on the surface of the upper semiconductor 401 constituting the second source / drain region 4.
Is a polycrystalline semiconductor film 30 forming the channel formation region 3
1 side end surface 302. In this embodiment, the gate electrode 7 formed on the surface of the gate insulating film 6 faces the side end surface 302 of the polycrystalline semiconductor film 301 forming the channel formation region 3 via the gate insulating film 6.

An interlayer insulating film 11 made of a silicon oxide film or the like is formed on the surface side of the gate electrode 7, and the first insulating film 11 is formed through contact holes 111 and 112 of the interlayer insulating film 11.
The first source / drain electrode 12 and the second source / drain electrode 13 are electrically connected to the source / drain region 2 and the second source / drain region 4, respectively.

In the TFT 1 configured as described above, in the present embodiment, first, the lower semiconductor film 201 on which the first source / drain regions 2 are formed has a lower portion at a portion facing the side end of the gate electrode 7. LDD with impurity concentration
A region 203 is formed. The upper semiconductor film 401 on which the second source / drain regions 4 are formed also has
An LDD region 403 into which a low-concentration impurity is introduced is formed in a portion facing the side end of the gate electrode 7. Therefore, the TFT 1 has an LDD structure while being vertical.

When a high-temperature process is used to manufacture the vertical TFT 1 configured as described above, it is necessary to use expensive quartz glass that can withstand the high-temperature process as the substrate 8. A low temperature process is employed so that a glass substrate can be used. Therefore, in the TFT 1 of the present embodiment, the channel forming region 3 is formed by forming an amorphous semiconductor film on the substrate 8 and then performing laser annealing, electron beam annealing, lamp annealing, and solid phase growth on the amorphous semiconductor film as described later. It is formed of a polycrystalline semiconductor film 301 obtained by performing a crystallization process such as the above. This polycrystalline semiconductor film 301
Has a columnar structure in which a column axis (indicated by an arrow A) is oriented in a film deposition direction during film formation, that is, in an out-of-plane direction of the substrate 8 in a process of melting and solidifying an amorphous semiconductor film to grow crystal grains. Will be. In this columnar structure, in order to indicate that the column axis A is perpendicular to the substrate 8, in FIG. 1A, a grain boundary is formed in the channel forming region 3 (polycrystalline semiconductor film 301) by a vertical line B. It is represented by

In this embodiment, in accordance with such a crystal structure, the polycrystalline semiconductor film 30 forming the channel formation region 3 is formed.
1 is perpendicular to the substrate 8,
The gate electrode 7 faces the gate electrode 02 via the gate insulating film 6. Therefore, when a gate potential is applied to the gate electrode 7, a channel is formed on the side end surface 302 of the polycrystalline semiconductor film 301 constituting the channel formation region 3, and the direction of the channel length at this time (indicated by an arrow CH) Direction) is parallel to the column axis A of the polycrystalline semiconductor film 301.
Therefore, in the direction of the channel length CH, the channel does not cross the grain boundary B, so that the carrier mobility is high. Therefore, TF manufactured by low temperature process
At T1, the on-current can be improved.

In the present embodiment, the TFT 1 has an LDD structure while being of a vertical type, so that the ON current is secured and the withstand voltage between the source and the drain is high. That is, in the vertical TFT 1, the thickness of the polycrystalline semiconductor film 301 forming the channel formation region 3 becomes the channel length as it is. Since it is necessary to increase the thickness of the polycrystalline semiconductor film 301 constituting
Although a long time is required for the film forming process, in the present embodiment, the portion of the lower semiconductor film 201 where the first source / drain region 2 is formed, which faces the side end of the gate electrode 7, and the second source / drain region 2 In the upper semiconductor film 401 where the drain region 4 is formed, low-concentration LDD regions 203 and 403 are formed at portions facing the side ends of the gate electrode 7 to ensure a high source-drain breakdown voltage. Therefore, according to the present embodiment, even if the channel length of the vertical TFT 1 is short, that is, even if the thickness of the polycrystalline semiconductor film 301 forming the channel formation region 3 is small, a sufficient source / drain breakdown voltage is ensured. The channel forming region 4
The time required for forming the film is short.

The TFT 1 having the LDD structure has a small off-leakage current, and thus is suitable for pixel switching. Therefore, the vertical TFT 1 of this embodiment is suitable for both a driving circuit and pixel switching.

An example of a method for manufacturing the TFT 1 having such a configuration will be described with reference to FIGS. 2 and 3 are process cross-sectional views illustrating a method for manufacturing the TFT 1 of the present embodiment.

First, as shown in FIG. 2A, an impurity such as phosphorus or boron is doped on the entire surface of the substrate 8 for about 10 ¹⁵ c.
After a semiconductor film such as a low-concentration doped silicon film containing about m ⁻³ to about 10 ¹⁸ cm ⁻³ is formed, it is patterned into an island shape to form an island-shaped lower semiconductor film 201. The doped semiconductor film may be formed as a polycrystalline semiconductor film or may be obtained by crystallizing an amorphous semiconductor film.

Next, a resist mask RM1 is formed to cover at least the LDD region 203 of the lower semiconductor film 201. In this state, an impurity is introduced into the lower semiconductor film 201, About 10 ¹⁸ c of impurities
A high concentration first source / drain region 2 containing about m ^-3 to about 10 ²⁰ cm ^-3 is formed. The LDD region 203 is formed from a portion of the lower semiconductor film 201 where the impurity has not been introduced.

Next, as shown in FIG. 2B, an insulating film such as a silicon oxide film or a silicon nitride film is formed on the entire surface of the substrate 8 by a sputtering method, a CVD method, a vapor deposition method, or the like.
The insulating film is patterned to leave an insulating film 9 for an etching stopper that partially overlaps the first source / drain region 2 (lower semiconductor film 201).

Next, as shown in FIG. 2C, an amorphous semiconductor film 300 having a thickness of about 100 Å to several μm is formed. If an amorphous silicon film is used as the amorphous semiconductor film 300, the plasma C
There are methods such as a VD method, an LPCVD method, an evaporation method, and a sputtering method. In the case of a plasma CVD method, a film can be formed at a temperature of 350 ° C. or lower. In the case of the LPCVD method, the deposition temperature differs depending on the source gas, and a film can be formed at a temperature of about 450 ° C. or less when disilane (Si ₂ H ₆ ) gas is used and at a temperature of about 560 ° C. or less when silane (SiH ₄ ) gas is used. It is. In the case of a vapor deposition method or a sputtering method, a film can be formed at a temperature of about 200 ° C. or less. Here, the amorphous semiconductor film 30
By adding phosphorus or boron at a low concentration as 0, channel doping may be performed to adjust the threshold voltage of the TFT 1.

Next, the amorphous semiconductor film 300 is subjected to crystallization treatment such as laser annealing, electron beam annealing, lamp annealing, or a solid phase growth method, so that the amorphous semiconductor film 300 becomes a polycrystalline semiconductor film 300B. In the laser annealing method, for example, a line beam having an excimer laser beam length of 400 mm is used, and its output intensity is, for example, 200 mJ / cm ² . The line beam is scanned such that a portion corresponding to 90% of the peak value of the laser intensity in the width direction overlaps in each region. In this crystallization process, the amorphous semiconductor film 300 is melted and solidified, and crystal grains grow to form the polycrystalline semiconductor film 300B. The polycrystalline semiconductor film 300B has a columnar crystal structure (columnar structure) in which the column axis A is oriented in a direction perpendicular to the substrate 8.

Next, as shown in FIG. 2D, an impurity such as phosphorus or boron is doped on the entire surface of the substrate 8 for about 10 ¹⁵ c.
A semiconductor film 400 such as a low-concentration doped silicon film containing about m ⁻³ to about 10 ¹⁸ cm ⁻³ is formed. as a result,
The semiconductor film 400 is in a state of being stacked on the polycrystalline semiconductor film 300B after the crystallization of the amorphous semiconductor film 300.

Next, in the semiconductor film 400, the LD
A resist mask RM2 covering a region covering the region to be the D region 403 is formed. In this state, an impurity is introduced into the semiconductor film 400 to reduce the impurity from about 10 ¹⁸ cm ⁻³ to about 10
A high concentration second source / drain region 4 containing about ²⁰ cm ^-3 is formed. Note that the LDD region 4 starts from a portion of the upper semiconductor film 401 where impurities are not introduced.
03 is formed.

Next, after removing the resist mask RM2, as shown in FIG.
M3 is formed.

Then, using the resist mask RM3,
The semiconductor film 400 and the polycrystalline semiconductor film 300B are collectively patterned, and as shown in FIG. 2F, a polycrystalline semiconductor film 301 forming the channel formation region 3, a second source / drain region 4, and an LDD The upper semiconductor film 401 including the region 403 is left. At this time, the side end surface 302 of the polycrystalline semiconductor film 301 and the upper semiconductor film 40
The patterning is performed so that the side end face 402 of the first insulating film 9 is located on the insulating film 9 for an etching stopper formed on the surface of the lower semiconductor film 201. The insulating film 9 for an etching stopper prevents the lower semiconductor film 201 from being over-etched when the upper semiconductor film 401 and the polycrystalline semiconductor film 301 are patterned. When the polycrystalline semiconductor film 301 and the polycrystalline semiconductor film 301 are formed by patterning in this manner, the end of the insulating film 9 for an etching stopper is
Is slightly interrupted between the side end surface 302 and the lower semiconductor film 201.

Next, as shown in FIG. 3A, the entire surface of the substrate 8 is formed by a plasma CVD method, a CVD method, or a sputtering method using TEOS (tetraethoxysilane), oxygen gas or the like as a source gas. Is about 600-1500
A gate insulating film 6 made of an Angstrom silicon oxide film or the like is formed.

Next, on the entire surface of the substrate 8, a doped semiconductor film, a metal film (such as tantalum, chromium, aluminum),
After forming a conductive film such as a silicide film (such as tungsten silicide or molybdenum silicide), FIG.
Is patterned as shown in FIG.
A gate electrode 7 is formed on the side end surface 302 of the semiconductor device via the gate insulating film 6.

Next, after an interlayer insulating film 11 is formed on the entire surface of the substrate 8, as shown in FIG. 1A, the interlayer insulating film 11 corresponds to the first source / drain region 2 and the second source / drain region 3. Contact holes 111 and 112 are formed at positions.

Then, a doped semiconductor film, a metal film (tantalum, chromium, aluminum, etc.)
After a conductive film such as a silicide film (such as tungsten silicide or molybdenum silicide) is formed, the first source / drain electrode 12 and the second source / drain electrode 13 are formed by patterning.

According to such a manufacturing method of the TFT 1,
Since the TFT 1 can be manufactured by a low-temperature process, an inexpensive glass substrate can be used as the substrate 8.
Further, the polycrystalline semiconductor film 3 forming the channel formation region 3
01 is patterned into an island shape,
Since the insulating film 9 for an etching stopper is formed in advance in a layer below the position corresponding to the above, the lower semiconductor film 201 constituting the first source / drain region 2 is not over-etched. Further, the channel forming region 3
And the upper semiconductor film 401 forming the second source / drain region 4 are formed by patterning at a time. Therefore, the patterning step is performed in a patterning step rather than in a separate step. However, there is an advantage that only one process is required.

[Other Embodiments] In the above embodiment, since the doped semiconductor film is formed in the steps described with reference to FIGS. 2A and 2D, the TFT 1 having the LDD structure is formed.
When a semiconductor film containing no impurities is formed in the steps described with reference to FIGS. 2A and 2D, the upper semiconductor film 201 and the lower semiconductor film 40 are formed.
1, the part facing the side end of the gate electrode 7 is an LD.
The semiconductor region does not contain impurities, not the D region. Therefore, a TFT having an offset gate structure can be manufactured. If the TFT has this offset gate structure, LD
Like the TFT having the D structure, even if the channel length is short, that is, the polycrystalline semiconductor film 301 forming the channel formation region 3
Even if the film thickness is small, a sufficient source / drain breakdown voltage can be ensured, so that the time for forming the channel formation region 3 can be reduced. In addition, a TFT having an offset gate structure has a small off-leak current, and thus is suitable for pixel switching.

It should be noted that the LDD region formed in the TFT (or the semiconductor region in which the impurity constituting the offset gate structure is not introduced) may be formed in both the first and second source / drain regions 2 and 4. However, it may be formed only on one side, for example, only on the side to be the drain region.

Further, in the above embodiment, the LDD region (or the semiconductor region into which the impurity constituting the offset gate structure is not introduced) is replaced with the lower semiconductor film 201 having the first and second source / drain regions 2 and 4. And an LDD region (or an impurity forming an offset gate structure) is not introduced by a low-concentration or impurity-implanted semiconductor film formed separately from the upper semiconductor film 401. Semiconductor region).

Further, in the above embodiment, the semiconductor film is
Although an example using a silicon film has been described, the present invention may be applied to a TFT using a semiconductor film such as germanium or silicon-germanium.

[0048]

As described above, in the vertical TFT according to the present invention, the gate electrode faces the side end surface parallel to the column axis of the polycrystalline semiconductor film obtained from the amorphous semiconductor film by the crystallization process. Therefore, the direction parallel to the column axis is the direction of the channel length. Therefore, the mobility of the carrier is high because the channel does not cross the grain boundary in the direction of the channel length. Therefore, in a TFT manufactured by a low-temperature process, on-current can be improved. Further, in the present invention, since the TFT has the LDD structure or the offset gate structure even though it is a vertical TFT, the withstand voltage between the source and the drain is high even if the channel length is short. Therefore, there is an advantage that the time required for film formation can be shortened because the polycrystalline semiconductor film forming the channel formation region can be made thin.

[Brief description of the drawings]

FIGS. 1A and 1B are a cross-sectional view and a plan view of a TFT to which the present invention is applied, respectively.

FIG. 2 is a process cross-sectional view showing a method for manufacturing the TFT shown in FIG.

3 is a process cross-sectional view showing each process performed after the process shown in FIG. 2 in the method of manufacturing the TFT shown in FIG. 1;

FIGS. 4A and 4B are a block diagram of an active matrix substrate of a liquid crystal display device and a circuit diagram showing a part of a driving circuit configured therein, respectively;

5A and 5B are a cross-sectional view and a plan view of a conventional TFT, respectively.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 TFT 2 first source / drain region 3 channel formation region 4 second source / drain region 6 gate insulating film 7 gate electrode 8 substrate 9 insulating film for etching stopper 11 interlayer insulating film 12 first source / drain electrode Reference Signs List 13 second source / drain electrode 201 lower semiconductor film 203, 403 LDD region 301 polycrystalline semiconductor film 302 side end face of polycrystalline semiconductor film 401 upper semiconductor film A column axis of polycrystalline semiconductor film B grain boundary CH channel Long direction

Claims (7)

[Claims] A first source / drain region,
A region, a channel forming region composed of a polycrystalline semiconductor film, and a second region serving as the other of the source / drain region are formed in this order on the substrate, and a gate electrode is formed on a side end surface of the polycrystalline semiconductor film by a gate insulating film. A vertical thin film transistor that faces through the first region and the side edge of the gate electrode between the first region and the side end surface of the polycrystalline semiconductor film, and the second region and the second region. At least one of the portions facing the side edge of the gate electrode between the side edge of the polycrystalline semiconductor film and the LDD region into which a low concentration impurity is introduced or the semiconductor region into which the impurity is not introduced is provided. A vertical thin film transistor, characterized in that: 2. The thin film transistor according to claim 1, wherein the polycrystalline semiconductor film has a columnar structure having a column axis substantially parallel to the side end face. 3. The semiconductor device according to claim 1, wherein the first region and the second region are formed in a lower semiconductor film and an upper semiconductor film formed on a lower layer side and an upper layer side of the polycrystalline semiconductor film, respectively. The LDD region into which the low-concentration impurity is introduced or the impurity is introduced into a portion of at least one of the upper semiconductor film and the lower semiconductor film facing a side end of the gate electrode. A vertical thin film transistor, wherein no semiconductor region is formed. 4. The method according to claim 1, wherein
The side end surface of the polycrystalline semiconductor film is located on a formation region of the lower semiconductor film in which the first region is formed, and between the side end surface of the polycrystalline semiconductor film and the lower semiconductor film. Is a vertical thin film transistor having an insulating film slightly interrupted between these films. 5. The method for manufacturing a vertical thin film transistor according to claim 2, wherein the amorphous semiconductor film for forming the channel formation region is subjected to a crystallization process so that a column axis extends in an out-of-plane direction of the substrate. After forming a polycrystalline semiconductor film having a columnar structure to be oriented, the polycrystalline semiconductor film is patterned to expose a side end surface substantially parallel to a column axis, and thereafter, the gate insulating film and the gate electrode are sequentially formed. A method for manufacturing a vertical thin film transistor. 6. The method for manufacturing a vertical thin film transistor according to claim 3, wherein the semiconductor films for forming the channel forming region and the upper semiconductor film are formed in this order, and then the two semiconductors are formed. A method for manufacturing a vertical thin film transistor, wherein a film is patterned at once. 7. The method of manufacturing a vertical thin film transistor according to claim 4, wherein the channel forming region is formed on the entire surface of the substrate after the lower semiconductor film and the insulating film are formed in this order. A method for manufacturing a vertical thin film transistor, comprising: forming a polycrystalline semiconductor film; and thereafter, patterning the polycrystalline semiconductor film using the insulating film as an etching stopper.