JPH11284196A - Method for manufacturing semiconductor device - Google Patents

Abstract

(57) [Problem] To improve the throughput and productivity of the crystallization step of an amorphous silicon film using germanium. SOLUTION: Before forming a germanium film 103,
The surface of the amorphous silicon film 103 is subjected to sputter etching using argon as a sputtering gas. After the sputter etching process, the surface of the amorphous silicon film 102 is not exposed to the atmosphere until the germanium film 103 is formed, so that the germanium film 10
3 prevents the formation of inactive germanium oxide at the interface with the amorphous silicon film 103. Therefore, the productivity of crystallization of an amorphous silicon film with germanium as a nucleus can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD [0001] The invention disclosed in the present specification is:
The present invention relates to a method for manufacturing a semiconductor device having a circuit including a thin film transistor (TFT) using a semiconductor thin film, and particularly to a method for manufacturing a crystalline semiconductor thin film formed over an insulating surface.

[0002] In this specification, all devices that can function by utilizing semiconductor characteristics are called semiconductor devices. Therefore, the semiconductor device described in the claims includes not only a single element such as a TFT, but also a semiconductor circuit and an electro-optical device including a TFT, and an electronic apparatus having the components as components.

[0003]

2. Description of the Related Art In recent years, a technique of manufacturing a thin film transistor (also referred to as a TFT) using a semiconductor thin film (having a thickness of about several tens to several hundreds of nm) formed on an insulating substrate such as glass or quartz has attracted attention. Have been. In particular, TFTs have been urgently developed as switching elements for image display devices having an active matrix circuit such as a liquid crystal display device. For example, in a liquid crystal display device, a pixel matrix circuit that individually controls pixel regions arranged in a matrix, a driving circuit that controls the pixel matrix circuit, and a logic circuit (an arithmetic circuit, a memory circuit, and the like) that processes an external data signal Attempts have been made to apply TFTs to all kinds of semiconductor circuits such as clock generators.

Recently, the mass production of TFTs using a crystalline silicon film (polysilicon film) has been started taking advantage of the fact that a TFT having an operation speed higher than that of an amorphous silicon film (amorphous silicon film) can be manufactured. I have.

The applicant of the present invention has been conducting research on a polysilicon film for a long time, and has rushed to develop a polysilicon film having a film quality closer to that of a single crystal. As a method for forming such a polysilicon film, the present applicant discloses a technique described in Japanese Patent Application Laid-Open No. 9-312260. In this publication, a metal element such as nickel is used as a catalyst element for promoting crystallization during crystallization of an amorphous silicon film, and after crystallization, a heat treatment at a temperature exceeding 700 ° C. is performed to improve the crystallinity of the polysilicon film. A method for improvement is disclosed.

However, when a polysilicon film using nickel as a crystallization catalyst is exposed to an oxidizing atmosphere and directly heat-treated, silicon oxide (SiO _x ) may locally grow abnormally. This abnormal growth of silicon oxide appears on the surface of the polysilicon film just like “worm swelling”. In the presence of such silicon oxide, T
During the FT manufacturing process, there is a problem that only silicon oxide is removed and silicon is cut.

FIG. 10 is a cross-sectional SEM photograph of a polysilicon film in which abnormal growth of silicon oxide has occurred.
It can be confirmed that silicon oxide was abnormally generated at the position indicated by the arrow, and the silicon film as the active layer was almost divided.

Therefore, in the polysilicon film formed by the technique described in the above publication, it is necessary to avoid performing a heat treatment in a state where the surface of the polysilicon film is directly in contact with the oxidizing atmosphere. For example, when a thermal oxide film is formed on the surface of a polysilicon film, it is necessary to devise a method such as covering the surface with an insulating film, which has caused the process to be complicated.

[0009]

According to the present applicant, the abnormal growth of silicon oxide which occurs when nickel is used as a crystallization catalyst is caused by intensive oxidation of nickel silicide existing in the polysilicon film. I think it is due to being. The present invention focuses on germanium having high consistency with silicon without using nickel, and prevents the above-described abnormal oxidation of silicon from occurring locally by using germanium as a catalyst.

Regarding the technology for crystallizing an amorphous silicon film using germanium as a catalyst element, Subraman
ian et al., `` 1997 Symposium on VLSI Technology Digest
ofTechnical Papers, pp. 97-98, reports that TFTs were fabricated using polysilicon films crystallized using germanium. This paper states that the process of crystallization using germanium is such that germanium becomes a nucleus at the interface between the amorphous silicon film and the germanium film by heating at low temperature, and crystallization of silicon proceeds by solid phase growth. I have.

However, germanium is relatively easily oxidized. If germanium oxide is formed at the interface with silicon, germanium oxide is inactive, so that the reaction between silicon and germanium becomes difficult, and crystallization is prevented from proceeding. The crystal growth distance of silicon using nickel reaches several tens of μm, but the crystal growth distance of germanium is only about 1 μm at most. Therefore, it is desired to eliminate as much as possible elements that hinder silicon crystal growth. Therefore, it is necessary to avoid formation of germanium oxide on the germanium film at the interface with silicon.

An object of the present invention is to solve the above-mentioned problems and to provide a technique for improving the throughput and productivity of the crystallization step of an amorphous silicon film using germanium.

[0013]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention relates to a method of manufacturing a semiconductor device having a circuit using a plurality of thin film transistors formed on an insulating surface. A) a first step of forming an amorphous silicon film on the insulating surface, 2) a second step of sputter etching the surface of the amorphous silicon film with an inert gas, and 3) a contact with the surface of the amorphous silicon film. A fourth step of forming a germanium film by heating and a fourth step of crystallizing the amorphous silicon film by a heat treatment and transforming the amorphous silicon film into a polysilicon film. Until the step, the substrate is not exposed to the atmosphere.

In the present invention, in order to prevent the formation of inactive germanium oxide at the interface between the amorphous silicon film and the germanium film, the surface of the amorphous silicon on which the germanium film is formed is sputter-etched, It is important to have a process for removing oxygen, impurities and a natural oxide film adsorbed on the surface, and not to expose the surface of the amorphous silicon film to the atmosphere until a germanium film is formed. This prevents the germanium film from being oxidized at the interface with the amorphous silicon film, and allows the crystallization of the amorphous silicon film to proceed efficiently.

[0015]

Embodiments of the present invention will be described with reference to the drawings.

[Embodiment 1] An embodiment of the present invention will be described with reference to FIG. FIG. 1 illustrates steps from crystallization of an amorphous silicon film to transformation into a polysilicon film. First, a substrate 101 having an insulating surface is prepared. As the substrate, a glass substrate, a quartz substrate, or a crystallized glass substrate can be used. When a glass substrate or a crystallized glass substrate is used, a base insulating film such as a silicon oxide film or a silicon nitride film is formed to prevent impurity diffusion, and a polysilicon film is formed on the surface of the insulating film. I just need. Further, a silicon substrate whose surface is thermally oxidized can also be used.

By forming a base insulating film such as a silicon oxide film or a silicon nitride film on the surface of the substrate, the surface can be flattened.
The effect of smoothing can be expected, and since the amorphous silicon film formed on the surface of the insulating film is not stressed, the effect of increasing the crystal growth distance of the amorphous silicon film can be expected. An insulating layer having a high effect of flattening and smoothing the substrate surface is a thermal silicon oxide film. In the present invention, when a high heat-resistant substrate such as a quartz substrate, a crystallized glass substrate, or a silicon substrate is used, the amorphous silicon film is formed so as to cover the entire surface (the surface on which the amorphous silicon film is formed) and the entire substrate. What is necessary is just to thermally oxidize.

An amorphous silicon film 102 is formed on an insulating surface of a substrate 101. Plasma CVD method
(PCVD) method, low pressure CVD (LPCVD) method, thermal CV
Method D can be used. Silane (SiH ₄ ) or disilane (Si ₂ H ₆ ) is used as a deposition gas.
The thickness of the amorphous silicon film 101 is an appropriate value for the active layer of the TFT, and may be 30 to 250 nm (typically 100 to 150 nm). (Figure 1
(A))

It should be noted that carbon, oxygen, and nitrogen mixed during the formation of the amorphous silicon film are factors that hinder the subsequent crystallization and are preferably reduced thoroughly. Specifically, the concentration of carbon and nitrogen in the amorphous silicon film 102 is less than 5 × 10 ¹⁸ atoms / cm ³ (typically,
× 10 ¹⁷ atoms / cm ³ or less) and the oxygen concentration is 1.5 ×
Less than 10 ¹⁹ atoms / cm ³ (typically 1 × 10 ¹⁸ atoms / cm 3
³ or less).

According to the experience of the present applicant, it has been found that when the concentration of carbon, oxygen and nitrogen exceeds the above-mentioned concentration range, the characteristics of the TFT rapidly deteriorate. This is probably because crystallization of silicon is hindered, and a polysilicon film having sufficient crystallinity cannot be obtained. Therefore, it is important to keep the density within the above range. Further, the above-mentioned impurity is TF
The concentration does not exceed the above-mentioned concentration range unless added intentionally in the process of preparing T.

Next, a germanium film 103 is formed on the surface of the amorphous silicon film 102. The thickness of the germanium film 103 is 1 to 50 nm, preferably 1 to 10 nm.
And it is sufficient. (FIG. 1 (B))

Before the germanium film 103 is formed, the surface of the amorphous silicon film 102 is sputter-etched with an inert gas to remove a natural oxide film and impurities formed on the surface. Typically, argon (Ar) is used as the inert gas. The pressure at the time of etching is 10 ⁻³ to 10 ⁻¹ Pa, and the temperature is room temperature to 450 ° C. The output of the RF power supply for using the substrate 101 as a cathode is 30 to 300 W.

After the sputter etching, a germanium film 103 is formed without exposing the surface of the amorphous silicon film 102 to the atmosphere. Therefore, in order to minimize the possibility of containing an oxidizing substance such as oxygen in the atmosphere in which the substrate 101 exists until the germanium film 103 is formed, an inert atmosphere such as nitrogen or argon is used under reduced pressure. The method for forming the germanium film 103 is such that the surface of the amorphous silicon film 102 is not exposed to the air when the substrate is transferred from a processing chamber for sputter etching to a processing chamber for forming a germanium film. Any film formation method can be used. Typically, a sputtering method can be used as described later, but another method such as a CVD method can be used as long as the conditions are satisfied.

After the germanium film 103 is formed, the amorphous silicon film 102 is crystallized by heat treatment to be transformed into a polysilicon film 104. By the heat treatment, crystal nuclei of silicon are generated at the interface between the amorphous silicon film 102 and the germanium film 103 with germanium as a nucleus. Crystal grains grow from this crystal nucleus and are transformed into the polysilicon film 104. (Fig. 1 (C))

Amorphous silicon film 1 in crystallization step
02 has a heating temperature of 450 to 650 ° C. (preferably 500 to 650 ° C.).
To 550 ° C.). The reason why the upper limit is set to 600 ° C. is to allow only crystal growth with germanium as a nucleus. If the temperature exceeds 600 ° C., the germanium film 10
In addition to the interface with No. 3, many natural nuclei in the amorphous silicon film 102 are generated. This is because crystal growth with germanium as a nucleus and crystal growth from a natural nucleus proceed simultaneously, and the crystallinity is disturbed. In the crystallization step, any of furnace annealing, lamp annealing, and laser annealing may be used, as long as the amorphous silicon film 102 can be heated.

The heating time is 8 to 20 hours when furnace annealing is used, and RT for irradiating a xenon lamp is used.
When the method A is used, the irradiation time of the xenon lamp may be set to several seconds to several minutes.

After the crystallization step is completed, the germanium film 10
3 is removed and the polysilicon film 104 is patterned to form an active layer of the TFT. Thereafter, the TFT may be completed according to a known method of manufacturing a top gate type TFT, for example, the manufacturing method described in Example 1 or Example 2.

In the manufacturing process of the TFT, a heat treatment is performed in a state where the active layer is in contact with an oxidizing atmosphere, such as a step of forming a gate insulating film with a thermal oxide film, a step of forming and removing the thermal oxide film to make the active layer thin. However, according to the present invention, since the nickel element does not exist in the polysilicon film, local abnormal growth of silicon oxide can be prevented even if the polysilicon film is brought into direct contact with an oxidizing atmosphere.

In the present invention, after the sputter etching process, the surface of the amorphous silicon film 102 is not exposed to the air atmosphere until the germanium film 103 is formed, so that the germanium film 103 is at the interface with the amorphous silicon film 103. Since the oxidation can be prevented, the productivity of the crystallization step using germanium as a nucleus can be improved.

Here, the surface of the amorphous silicon film 102 is not exposed to the air atmosphere during the formation of the germanium film 103 after the sputter etching process. It is preferable to prevent the germanium film 103 from coming into contact with an oxidizing substance such as oxygen by keeping the 101 from being exposed to the air atmosphere. The atmosphere in the crystallization step is an inert atmosphere such as nitrogen or a hydrogen atmosphere.

As described above, in order to prevent the substrate from being exposed to the atmosphere from the sputter etching process to the crystallization process, the same apparatus is used for the processes from the sputter etching process, the germanium film forming process and the crystallization process. Easy to implement within. For example, a multi-task type sputtering apparatus having a plurality of processing chambers 14 to 17 as shown in FIG. 4 may be used. A sputter etching process may be performed in the etching chamber 16, a germanium film may be formed in the sputtering chamber 14, and a crystallization step may be performed in a heating chamber 17 provided with a heating unit.

By preventing the airtightness of the sputtering apparatus from being broken, it is easy to prevent the substrate 101 from being exposed to the atmosphere. In addition, the sputter etching process, the germanium film forming process, and the crystallization process can be performed successively, so that the throughput can be improved. Further, in order to perform these steps, the substrate is loaded after reducing the degree of vacuum in each processing chamber to 10 ⁻⁴ to 10 ⁻⁶ Pa to reduce the oxygen supply source such as oxygen as much as possible. Is preferred.

The sputter apparatus is not limited to a multi-task type sputter apparatus as long as the substrate 101 is not exposed to the atmosphere, and may be an in-line type apparatus in which chambers are linearly arranged.

Embodiment 2 This embodiment will be described with reference to FIG. This embodiment is a modification of the first embodiment,
In the first embodiment, the germanium film 1 is in contact with the entire surface of the amorphous silicon film 102 as shown in FIG.
Although 03 was formed, amorphous silicon can be laterally grown by forming a germanium film in partial contact with the surface of the amorphous silicon film.

First, on a substrate 201 having an insulating surface, an amorphous silicon film is patterned into the shape of an active layer of a TFT to form island regions 202 and 203. (FIG. 5 (A))

Next, a mask insulating film 204 having openings 202a to 202d is formed. As the mask insulating film, a silicon oxide film can be used. In the mask insulating film 204, openings 202a to 202d are formed on regions 202a and 203a to be source regions of the island regions 202 and 203 and regions 202b and 203b to be drain regions.
Are formed. (FIG. 5 (B))

Next, in the openings 202a to 202d, the exposed regions 202a and 203a and the surfaces of the regions 202b and 203b to be drains are sputter-etched using Ar gas. Then, the substrate 201 is not exposed to the atmosphere, and then the germanium film 20 is removed.
4 is formed. (FIG. 5 (C))

Then, in an inert atmosphere or a hydrogen atmosphere,
Heating is performed at a temperature of 50 to 600 ° C. to crystallize the island regions 202 and 203 made of an amorphous silicon film, thereby obtaining active layers 211 and 212 made of a polysilicon film. The germanium film 205 has the regions 202a, 202b, 203a,
Since it is selectively in contact with the amorphous silicon film at 203b, crystal growth proceeds in the lateral direction (direction parallel to the film surface) as shown by the arrow. Such crystal growth is called lateral growth (lateral growth). (FIG. 5 (D))

In the case of this embodiment, the regions 202a and 203a serving as the source region and the region 2 serving as the drain region
Since the crystal growth proceeds from 02b and 203b as starting points, regions 202c and 20 where channel formation regions are formed are formed.
In 3c, the tip of the growth collides and a grain boundary is formed, and the crystal growth stops. When germanium was used as a nucleus for crystallization, the distance of lateral growth was about 1 μm at the maximum by heat treatment at 600 ° C. for 8 hours.

Therefore, from the viewpoint of at least the requirement to crystallize the channel formation region (that is, the requirement from the electrical characteristics of the TFT) and the throughput and productivity,
The distance L1 between the regions 202a and 202b in the channel length direction,
And the distance between the regions 203a and 203b in the channel length direction
L2 (that is, regions 202c and 203c where channels are formed)
(L1, L2) in the channel length direction is preferably 2 μm or less, and more preferably 1 μm or less (of course, zero is not included) in consideration of the lateral growth distance.

[Embodiment 3] This embodiment will be described with reference to FIG. This embodiment is a modification of the mask insulating film of the second embodiment. 7, the same reference numerals as those in FIG. 5 denote the same components. In the second embodiment, one island-shaped region 202
202a serving as a source region in order to crystallize
The germanium film 203 is in contact with both the drain region 202b and the region 202b. In the present embodiment, the germanium film is in contact with the island region in either one of the regions 202a or 202b.

Therefore, the mask insulating film 304 of the present embodiment is
Is a region 20 to be a source region of the island regions 202 and 203
Openings 304a and 304b are provided on 2a and 203a. (FIG. 7 (A))

Next, a germanium film 305 is formed on the mask insulating film 304. The germanium film 305 is formed in the regions 202a and 2a serving as source regions of the island regions 202 and 203.
Contact only at 03a. (FIG. 7 (B))

In this state, heat treatment is performed to grow laterally, and the TFT active layer 311 made of a polysilicon film is formed.
312 are obtained. Hereinafter, a TFT may be manufactured by a known manufacturing method described in Embodiments 1 and 2. (FIG. 7 (C))

Here, as shown by the arrow, the island-shaped region 20 is formed.
Since lateral growth at 2 and 203 proceeds in one direction,
Unlike in the second embodiment, the growth front does not collide with the regions 202c and 203c where the channel formation region is formed, and no grain boundary is formed. Therefore, T with excellent carrier mobility
FT can be obtained.

As described above, the lateral growth distance is limited from the viewpoint of productivity. In the present embodiment, since the region serving as the starting point for crystal growth is one place per active layer, the above-mentioned channel is not formed. Regions 202c and 203 to be formed
The lengths L1 and L2 of c in the channel length direction are preferably 1 μm or less, more preferably 0.5 μm or less (of course, zero is not included).

In the second and third embodiments, the amorphous silicon film is patterned into the shape of the active layer of the TFT. However, the silicon film may be patterned after the amorphous silicon film is transformed into a polysilicon film.

[0048]

Embodiments of the present invention will be described below in detail with reference to FIGS. Note that the semiconductor device of the present invention is not limited to the configuration of the active matrix substrate or the CMOS circuit shown in the embodiment.

Embodiment 1 This embodiment will be described with reference to FIGS. In this embodiment, a method for manufacturing an active matrix substrate of a liquid crystal display device as a semiconductor circuit of the present invention is described, and an N-channel TFT serving as a switching element of an active matrix circuit and an active matrix circuit are driven on the same substrate. Driver circuit CM
A method for manufacturing an OSTFT will be described.

An amorphous silicon film 102 having a thickness of 50 nm is formed on a quartz substrate 101 by a low pressure CVD method. (Fig. 1 (A))

Next, the surface of the amorphous silicon film 102 is sputter-etched with argon. afterwards,
A germanium film 104 is formed in contact with the entire surface of the amorphous silicon film 102 by a germanium film 103 sputtering method. The deposition conditions of the germanium film were as follows: germanium was used as the target, argon was used as the sputtering gas, the deposition temperature was room temperature, the ultimate pressure was 4 × 10 ⁻⁴ Pa or less,
The current is 0.4 A. (FIG. 1 (B))

Next, the amorphous silicon film 102 is crystallized and transformed into a polysilicon film 104. (Fig. 1 (C))

In this embodiment, the processes from the sputter etching process to the crystallization process are continuously performed by a multi-task type sputtering apparatus. FIG. 4 shows a schematic configuration diagram of a sputtering apparatus. FIG. 4A is a top view, and FIG. 4B is a cross-sectional configuration diagram taken along a broken line XX ′.

Reference numeral 11 denotes a common chamber, 12 and 13 denote load lock chambers, 14 and 15 denote sputtering chambers, 16 denotes an etching chamber, and 17 denotes a heating chamber. Each of the chambers 12 to 17 is connected to the common chamber 11 via a gate valve, so that airtightness can be maintained for each of the chambers 11 to 17. Each room 11
Exhaust system (not shown) for reducing pressure every 17
And a gas supply system (not shown) for supplying a gas for controlling the atmosphere or a sputtering gas. The evacuation system of the sputtering chambers 14 and 15, the etching chamber 16 and the heating chamber 17 is provided with a cryopump in order to achieve an ultimate vacuum of 10 ⁻⁶ Pa.

The processing substrate 10 is placed in the common chamber 11
7 is provided with a robot arm 31 for printing. The substrate holding portion of the robot arm 31 is three-dimensionally movable as shown by the arrow. The robot arm 31 is of a face-down type in which the main surface (element formation surface) of the processing substrate 10 is conveyed downward, so that dust is prevented from adhering to the main surface.

The load lock chambers 12 and 13 store the processing substrate 10
This is a room for carrying in and out of the equipment. The processing substrate 10 is stored in the substrate transport cassettes 32 and 33, and is carried in and out of the apparatus.

The sputtering chambers 14 and 15 have substantially the same structure, and the configuration of the sputtering chamber 14 will be described with reference to FIG. In the sputtering chamber 14, the target support 4
1, a target 42, a shutter 43, and a face-down type substrate holder 44 are provided.
The substrate holder 44 is designed to support a few millimeters of the edge of the processing substrate 10 so that contamination of the substrate 10 is minimized. The target 42 is supplied with DC power from a DC power supply (not shown). The specifications of the gas supply system and the like are determined depending on the material to be formed in the sputtering chambers 14 and 15.

In this embodiment, the etching chamber 16 has substantially the same structure as the sputtering chambers 14 and 15, but an RF power supply is connected instead of a DC power supply, and an RF voltage is supplied to the substrate 10. Thus, a negative self-bias voltage is applied.

The heating chamber 17 is a chamber for the crystallization step, and has a configuration capable of performing an RTA process as a heating means from the viewpoint of throughput. Face-down type substrate holder 51
And a xenon lamp 5 for heating both sides of the substrate 10.
2, 53 are provided. The xenon lamp 53 serves as a main lamp for heating the main surface of the substrate.

In the present embodiment, the specification of the heating chamber 17 is a chamber for RTA processing in consideration of throughput, but may be a chamber that can be heated by furnace annealing provided with an electric furnace.

The method of using the sputtering apparatus shown in FIG. 4 in this embodiment will be described below. Amorphous silicon film 10
The substrate 101 on which the film 2 is formed is transferred from the load lock chamber 12 into the sputtering apparatus. After the load lock chamber 12 is depressurized, a nitrogen atmosphere is set. The common chamber 11, the sputtering chambers 14, 15, and the etching chamber 16 are also decompressed, and the ultimate pressure is 10 ⁻⁶ Pa.

The gate valve 22 is opened and the robot arm 3
1 moves the substrate 10 to the etching chamber 16. In order to avoid mixing of the atmosphere, the two gate valves 22
27 are controlled not to open simultaneously. The same applies to the following. The substrate is fixed to a substrate holder in the etching chamber 16 and sputter etching is performed with an argon gas while applying an RF voltage to the substrate. The impurities and the natural oxide film on the surface of the amorphous silicon film 102 are removed by the etching.

Next, the substrate is moved to the sputtering chamber 14 and a germanium film 103 is formed. Then, the substrate is moved to the heating chamber 17. The heating chamber 17 is set in a nitrogen atmosphere, and the substrate is heated by the xenon lamps 52 and 53 to crystallize the amorphous silicon film 102. When the crystallization step is completed, the substrate is moved into the cassette 33 in the load lock chamber 13 and is unloaded from the sputtering device. Then, the germanium film 103 remaining on the polysilicon film 104 is removed with a sulfuric acid / peroxide solution (H ₂ SO ₄ : H ₂ O ₂ = 1: 1).

Before the crystallization step, in order to suppress oxidation of the germanium film as much as possible, a germanium film is formed in the sputtering chamber 14 and then a silicon oxide film is formed on the germanium surface in the sputtering chamber 15. It is also effective to cover the germanium surface. In this case,
Even when the crystallization step is performed outside the sputtering apparatus of FIG. 4, a decrease in crystallization can be suppressed.

A process of manufacturing an active matrix substrate using the obtained polysilicon film 104 will be described below with reference to FIGS. Note that in this embodiment, C
Driver circuit composed of MOS circuit and N-channel type TF
An active matrix type liquid crystal display device (AMLCD) in which a pixel matrix circuit manufactured by T (N-channel type TFT) is integrally formed is taken as an example.

A polysilicon film 10 is formed on a glass substrate 101.
4 is formed and patterned to form an active layer 11 of the TFT.
1 to 113 are formed. Active layers 111 and 112 are CMO
The active layer 113 is used for a pixel matrix circuit, and the active layer 113 is used for a TFT constituting an S circuit. (Fig. 2 (A))

Next, a plasma CVD method (or a reduced pressure heat CV
D method), a silicon oxide film 114 is formed to a thickness of 120 nm. In addition, a silicon oxynitride film (SiO
_x N represented by _y) or silicon nitride film can be used. Further, these may be freely combined to form a laminated structure.

Next, a gate electrode 115 made of a polysilicon film exhibiting N-type conductivity is formed on the silicon oxide film 114.
To 117 are formed. The thickness of the gate electrodes 115 to 117 may be selected in the range of 200 to 300 nm. (Figure 2
(B))

After the gate electrodes 115 to 117 are formed,
By a dry etching process using the gate electrodes 115 to 117 as a mask, a silicon oxide film is left only under the gate electrode (and the gate wiring). Of course, the portions remaining under the gate electrodes 115 to 117 are portions that actually function as gate insulating films.

Next, the region to be a P-channel type TFT is hidden by a resist mask 119, and an impurity for imparting N-type (phosphorus in this embodiment) is added by a plasma doping method. The low concentration impurity regions 120, 121 formed at this time
Is partly formed into an LDD (Lightly Doped Drain) region later, so that phosphorus is added at a concentration of 1 × 10 ^{17 to} 5 × 10 ¹⁸ atoms / cm ³ . (Fig. 2 (C))

Next, after the resist mask 119 is removed, a region to be an N-channel TFT is formed in the resist mask 1.
Then, an impurity imparting a P-type (boron in this embodiment) is added by a plasma doping method. At this time, similarly to the case of phosphorus, the low concentration impurity region 123 is formed. (FIG. 2 (D))

When the state shown in FIG. 2D is obtained,
After removing the resist mask 122, sidewalls 124 to 126 are formed by using an etch-back method. In this embodiment, the side walls 124 to 126 are formed of a silicon nitride film.

After the sidewalls 124 to 126 are formed in this manner, the region to be a P-channel TFT is hidden again by the resist mask 127, and phosphorus is added. At this time, the dose is set higher than that of phosphorus.

The source region 128, the drain region 129, the low-concentration impurity region (LDD region) 130 of the N-channel TFT constituting the CMOS circuit by the step of adding phosphorus,
A channel forming region 131 is defined. Further, the source region 1 of the N-channel TFT constituting the pixel matrix circuit
32, drain region 133, low concentration impurity region (LDD
Region 134 and a channel forming region 135 are defined.
(FIG. 3 (A))

Next, after removing the resist mask 134, a region to be an N-channel TFT is hidden by the resist mask 136, and boron is added at a dose higher than that of phosphorus. The source region 137, drain region 138, low-concentration impurity region (LDD region) 139, and channel formation region 140 of the P-channel TFT forming the CMOS circuit are defined by the boron addition process. (FIG. 3 (B))

As described above, after the step of adding impurities to the active layers 111 to 113 is completed, heat treatment is performed by furnace annealing, laser annealing, or lamp annealing to activate the added impurities. At this time, damage to the active layer caused by the addition of the impurity is also recovered.

The channel forming regions 131, 135,
140 is an intrinsic or substantially intrinsic region where no impurity element is added. Here, “substantially intrinsic” means that the impurity concentration for imparting N-type or P-type is equal to or lower than the spin density of the channel formation region, or that the impurity concentration is 1 × 10 ¹⁴ to 1 × 10 ¹⁷ atoms / cm 2. ^{Indicates that} the range is ³ .

Next, a silicon nitride film having a thickness of 25 nm and 90
A first interlayer insulating film 141 made of a laminated film of a silicon oxide film having a thickness of 0 nm is formed. And Ti / Al / Ti
The source electrodes 142 to 144 and the drain electrodes 145 and 146, each of which is formed of a laminated film having a thickness of 100/500/100 nm in this order, are formed.

Next, a silicon nitride film 23 having a thickness of 50 nm is formed.
7, 20 nm thick silicon oxide film (not shown), 1 μm
A second interlayer insulating film having a stacked structure of a thick organic resin film 148 is formed. Note that as the organic resin film 148, polyimide, acrylic, polyamide, or the like can be used. In this case, the silicon oxide film having a thickness of 20 nm functions as an etching stopper when the organic resin film 148 is dry-etched.

After the formation of the second interlayer insulating film, an opening is provided by etching the organic resin film 148 in a region where a storage capacitor is to be formed later. At this time, only the silicon nitride film 147 is left at the bottom of the opening or the silicon nitride film 147 is left.
And a silicon oxide film (not shown).

Then, a titanium film having a thickness of 300 nm is formed, and a black mask 149 is formed by patterning. The black mask 149 is formed on a portion requiring light shielding, such as a TFT and a wiring portion, on the pixel matrix circuit.

At this time, in the above-mentioned opening, the drain electrode 146 of the pixel matrix circuit and the black mask 149 are in close proximity with the silicon nitride film 237 (or a stacked film of the silicon nitride film and the silicon oxide film) interposed therebetween. .

In this embodiment, the black mask 149 is held at a fixed potential, and the auxiliary capacitance 150 is formed using the drain electrode 146 as a lower electrode and the black mask 239 as an upper electrode. In this case, since the dielectric is very thin and has a high relative permittivity, a large capacitance can be secured.

After the formation of the black mask 149 and the storage capacitor 150 in this way, an organic resin film having a thickness of 1 μm is formed again to form the third interlayer insulating film 151. Then, a contact hole is formed to form a transparent conductive film (typically, ITO).
Is formed to a thickness of 120 nm.

Finally, heat treatment is performed at 350 ° C. for about 2 hours in a hydrogen atmosphere to hydrogenate the entire device. Thus, an active matrix substrate as shown in FIG. 3C is completed. Thereafter, an active matrix type liquid crystal display device is completed by sandwiching a liquid crystal layer between itself and a counter substrate by a known cell assembly process.

Embodiment 2 This embodiment will be described with reference to FIGS. This embodiment is a modified example of the first embodiment, in which an amorphous silicon film is laterally grown by forming a germanium film so as to partially contact the surface of the amorphous silicon film.

First, an amorphous silicon film is patterned into the shape of an active layer of a TFT on a substrate 201 having an insulating surface to form island regions 202 and 203. (FIG. 5 (A))

Next, a mask insulating film 204 having openings 202a to 202d is formed. A mask insulating film made of a silicon oxide film was formed. In the mask insulating film 204, a region 202 serving as a source region of the island regions 202 and 203
a, 203a and a region 202b to be a drain region;
Openings 202a to 202d are respectively formed on 03b. (FIG. 5 (B))

Next, as in the first embodiment, the steps from the sputter etching step to the crystallization step are performed in the sputtering apparatus shown in FIG. First, in the etching chamber 16, the openings 202a to 202d are opened with argon gas.
Then, the exposed regions 202a and 203a and the surfaces of the regions 202b and 203b to be drains are sputter-etched. Then, the substrate 201 is moved to the sputtering chamber 14, and a germanium film 204 is formed by a sputtering method under the same conditions as in the first embodiment. (FIG. 5 (C))

Then, an RTA process is performed in the heating chamber 17 to form island regions 202, 2 made of an amorphous silicon film.
03 is crystallized to form an active layer 211 made of a polysilicon film.
And 212 are obtained. The germanium film 205 is in the region 202
a, 202b, 203a, and 203b selectively contact the amorphous silicon film.
The regions 202c and 203c in which twelve channels are formed are formed by laterally grown regions. The lateral growth region has a very high degree of uniformity of crystal grain orientation.
Electrical characteristics such as carrier mobility of T can be improved. ((FIG. 5 (D))

Then, the germanium film 203 remaining on the active layers 211 and 212 is coated with an aqueous sulfuric acid solution (H ₂ SO ₄ :
After removal by H ₂ O ₂ = 1: 1), an insulating film 213 constituting a gate insulating film was formed next. With a plasma CVD apparatus, a silicon nitride oxide film having a thickness of 120 nm was formed using SiH ₄ and N ₂ O as source gases. The film formation conditions were a pressure of 0.3 torr, a substrate temperature of 400 ° C., and an RF output of 10
0 W, source gas flow rate was ₄ sccm for SiH _{4 and} 400 for N ₂ O.
It will be sccm. (FIG. 5E)

An aluminum film (adding 0.18% by weight of Sc) constituting a gate electrode was formed on the insulating film 213 to a thickness of 400 nm by a sputtering apparatus. Then, the aluminum film surface was anodized to form an anodic oxide film (not shown). In this anodizing step, in an ethylene glycol solution containing 3% by weight of tartaric acid, an aluminum film is used as an anode, platinum is used as a cathode, and 10 V is applied between the electrodes.
Was applied. The anodic oxide film formed in this step is about 1 nm in order to improve the adhesion of a photoresist to be formed later. After the anodizing step, a photoresist mask (not shown) for patterning is formed, and the aluminum film is patterned by wet etching to form a pattern 21 made of aluminum.
4, 215 are obtained. (FIG. 6 (A))

Next, the anodic oxidation step is performed again, and the pattern 2
Anodized films 216 and 217 are formed on the side surfaces of the substrates 14 and 215. In this anodic oxidation step, a 3% by weight oxalic acid solution is used as an electric field solution, and the voltage between the anode and the cathode is set to 8V.
And In this anodic oxidation step, since a photoresist mask (not shown) is present, the exposed side surfaces of the patterns 214 and 215 are selectively oxidized to form porous anodic oxide films 216 and 217. .

After removing the photoresist mask, the above-described anodic oxidation step using the ethylene glycol solution containing 3% by weight tartaric acid as an electrolytic solution is again performed, and barrier-type anodic oxide films 218 and 219 having dense film quality are obtained. To form The patterns 214 and 215 that have not been anodized in the three anodizing steps constitute the gate electrodes 220 and 221. In this anodic process, the surface of the patterns 214 and 215 is oxidized due to the infiltration of the electrolytic solution into the porous anodic oxide film, and the configuration in which the gate electrodes 220 and 221 are covered with the anodic oxide films 218 and 219 is obtained. Was. (FIG. 6
(B))

Next, using the anodic oxide films 216 and 217 and the gate electrodes 220 and 221 as a mask, the insulating film 213 made of a silicon nitride oxide film was patterned. The patterned insulating film functions as the gate insulating films 222 and 223. (FIG. 6 (C))

Next, the porous anodic oxide films 216 and 217 were removed by wet etching using an acid obtained by mixing phosphoric acid, acetic acid and nitric acid. Then, impurities are introduced into the active layers 211 and 212 in order to form source / drain regions. First, phosphorus (P) for imparting N-type conductivity was introduced in two doping steps by an ion doping apparatus. The doping gas in the two doping process using PH ₃ diluted to 5% with hydrogen (H _2). The first doping condition was an acceleration voltage of 90 kV, an RF output of 5 W, and a set dose of 1.2 × 10 ¹³ cm ³ .
The second doping condition was acceleration voltage 10 kV, RF output 2
0 W and the set dose amount was 5 × 10 ¹⁴ cm ³ .

Next, the active layer 2 to be an N-channel type TFT is formed.
11 was coated with a photoresist, and boron (B) for imparting a P-type conductivity to the remaining active layer 212 was introduced by two ion doping steps. In the two doping steps, B ₂ H ₆ diluted to 5% with hydrogen (H ₂ ) was used as a doping gas. The first doping condition was an acceleration voltage of 70 kV, an RF output of 5 W, and a set dose of 2 × 10 ¹⁴
cm ³ . The second doping condition is acceleration voltage 10
kV, RF output 20W, set dose is 1.3 × 10 ¹⁴ c
It was m ^3.

Through the above steps, the N-channel TFT
In the active layer 211, the region 228 on which the gate electrode 220 and the anodic oxide film 218 are present becomes a channel formation region without addition of phosphorus ions even in two doping steps. In addition, 2 in which the gate insulating film 222 does not exist
Phosphorus ions are added to the two regions 224 and 225 in both dopings to form a source region and a drain region.
Since the remaining two regions 226 and 227 have a low acceleration voltage in the second doping step, the gate insulating film 222
Function as a mask, the source / drain region 2
The phosphorous concentration is lower than 24 and 225, which results in a low concentration impurity region.

By the boron ion doping process,
The active layer 212 constituting the P-channel type TFT has the source / drain region 23 which has been doped with phosphorus and is N-type.
The conductivity types of 0, 231 and the low-concentration impurity regions 232, 233 are inverted to P-type. Similarly to the phosphorus ions, the gate insulating film 223, the gate electrode 221, and the anodic oxide film 219 function as a mask.
The boron concentration of 33 is in the source / drain regions 230, 2
It is lower than 31. The region 234 is defined as a channel formation region to which phosphorus and boron are not added.
(FIG. 6 (D))

Next, after activating the impurities (phosphorus and boron) introduced into the active layers 211 and 212, the interlayer insulating film 2 is formed.
35 was formed. As the interlayer insulating film 235, a two-layer insulating film of a silicon nitride film and a silicon oxide film is formed. First, in a plasma CVD apparatus, the substrate temperature was set to 325 ° C., the pressure was set to 0.7 torr, and the RF output was set to 300 W.
_{Using 4} (flow rate 5 sccm), NH ₃ (flow rate 38 sccm), and N ₂ (flow rate 87 sccm), a silicon nitride film is formed to a thickness of 25 nm. Next, a substrate temperature of 300 ° C., a pressure of 1.05 torr,
RF output 200 W, source gas TEOS (flow rate 35 sc
cm) and O ₂ (flow rate 500 sccm), and a silicon oxide film is formed to a thickness of 900 nm.

Next, a contact hole was opened in the interlayer insulating film 235. Then, as a conductive film forming source / drain electrodes, a stacked film including a titanium (Ti) film having a thickness of 50 nm and an aluminum (Al) film having a thickness of 400 nm was continuously formed by a sputtering apparatus. Note that 2% by weight of silicon (Si) was added to the aluminum film. And titanium film /
The stacked film made of the aluminum film was patterned to form a source electrode 236 and drain electrodes 237 and 239, respectively. Here, a CMOS TFT is formed by an N-channel TFT and a P-channel TFT.

[Embodiment 3] This embodiment will be described with reference to FIG. In the first and second embodiments, the germanium film is formed after the amorphous silicon film is formed. In this embodiment, an example in which the germanium film is formed first is shown. here,
In order to prevent the germanium film from being oxidized, the germanium film and the amorphous silicon film are multitasking type plasma CVD apparatuses having a plurality of CVD processing chambers (the sputtering chamber in FIG. 4 is replaced by a CVD chamber having a plasma generating means). Is formed).

First, the quartz substrate 401 is moved to one CVD chamber of a CVD apparatus, and a germanium film 402 is formed. Germane (GeH ₄ ) may be used as a source gas. Germane is easily decomposed at a low temperature of 450 ° C.
(FIG. 8A)

Next, the substrate 401 is moved to another CVD chamber, and an amorphous silicon film 403 is formed on the entire surface of the germanium film 402. Silane or disilane may be used as a source gas. (FIG. 8 (B))

Then, the apparatus is moved to the heating chamber in the apparatus, and RT
The amorphous silicon film 403 is crystallized and transformed into a polysilicon film 404 with germanium as a nucleus by A or furnace annealing. (FIG. 8 (C))

Then, the substrate is taken out of the CVD apparatus,
The active layer 405 of the TFT is formed by patterning the polysilicon film 404. Also, the germanium film 403 underlying the active layer 405 is patterned into an island-like germanium region having the same shape as the active layer 405 for the reliability of the TFT.
Separate for each TFT. Hereinafter, the TFT may be completed according to a known method for manufacturing a top gate type TFT as shown in Embodiments 1 and 2.

In this embodiment, since the germanium film 402 and the amorphous silicon film 403 are formed in the same apparatus without breaking the airtightness, the oxidation of the germanium film 402 at the interface with the amorphous silicon film 403 is suppressed. Therefore, crystallization can be performed efficiently.

Embodiment 4 In this embodiment, Embodiments 1 to
FIG. 9 shows an example of an electronic apparatus (applied product) on which the electro-optical device and the semiconductor circuit indicated by 3 are mounted. Note that an electronic device is defined as a product equipped with a semiconductor circuit and / or an electro-optical device.

The electronic apparatus to which the present invention can be applied includes a video camera, an electronic still camera, a projector, a head-mounted display, a car navigation, a personal computer, a portable information terminal (mobile computer, mobile phone, PHS, etc.).

FIG. 9A shows a mobile phone, and a main body 200.
1, audio output unit 2002, audio input unit 2003, display device 2004, operation switch 2005, antenna 2006
It consists of. The present invention can be applied to the audio output unit 2002, the audio output unit 2003, the display device 2004, and the like.

FIG. 9B shows a video camera,
101, display device 2102, audio input unit 2103, operation switch 2104, battery 2105, image receiving unit 210
6. The present invention can be applied to the display device 2102, the sound input unit 2103, the image receiving unit 2106, and the like.

FIG. 9C shows a mobile computer (mobile computer), which includes a main body 2201 and a camera section 2.
202, an image receiving unit 2203, operation switches 2204, and a display device 2205. The present invention is a camera unit 220.
2. Applicable to the image receiving unit 2203, the display device 2205, and the like.

FIG. 9D shows a head-mounted display, which includes a main body 2301, a display device 2302, and a band 2
303. The present invention can be applied to the display device 2302.

FIG. 9E shows a rear type projector, in which a main body 2401, a light source 2402, a display device 2403,
Polarizing beam splitter 2404, reflector 240
5, 2406 and a screen 2407. The invention can be applied to the display device 2403.

FIG. 9F shows a front type projector, which includes a main body 2501, a light source 2502, and a display device 250.
3. It comprises an optical system 2504 and a screen 2505. The invention can be applied to the display device 2503.

As described above, the applicable range of the present invention is extremely wide, and can be applied to electronic devices in all fields. Further, the present invention can be applied to all products requiring an electro-optical device or a semiconductor circuit.

[0117]

According to the present invention, by using germanium as a nucleus for crystallization, a polysilicon film having high crystallinity can be obtained by a crystallization process that does not cause a problem of abnormal growth of silicon oxide. Oxidation is suppressed, so that the crystallization step can be performed efficiently.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view for explaining a crystallization step of a polysilicon film according to the present invention.

FIG. 2 is a diagram illustrating a manufacturing process of an active matrix substrate of the present invention.

FIG. 3 is a diagram illustrating a manufacturing process of an active matrix substrate of the present invention.

FIG. 4 is a schematic configuration diagram of a sputtering apparatus used for a crystallization step of the present invention.

FIG. 5 is a cross-sectional view for explaining a polysilicon film crystallization step of the present invention.

FIG. 6 is a cross-sectional view illustrating a manufacturing process of a TFT of the present invention.

FIG. 7 is a cross-sectional view for explaining a polysilicon film crystallization step of the present invention.

FIG. 8 is a cross-sectional view for explaining a polysilicon film crystallization step of the present invention.

FIG. 9 illustrates an electronic device to which the semiconductor device of the present invention is applied.

FIG. 10 is an SEM photograph showing abnormal growth of silicon oxide.

[Explanation of symbols]

 Reference Signs List 101 substrate 101 amorphous silicon film 103 germanium film 104 polysilicon film

Claims (10)

[Claims] 1. A method for manufacturing a semiconductor device having a circuit using a plurality of thin film transistors formed on an insulating surface, comprising: a first step of forming an amorphous silicon film on an insulating surface of a substrate; A second step of sputter etching the surface of the amorphous silicon film, a third step of forming a germanium film in contact with the surface of the amorphous silicon film, and crystallizing the amorphous silicon film by a heat treatment. And a fourth step of transforming the amorphous silicon film into a polysilicon film, wherein after the second step, the amorphous silicon film surface is not exposed to the atmosphere until the germanium film is formed in the third step. A method for manufacturing a semiconductor device, comprising: 2. A method for manufacturing a semiconductor device having a circuit using a plurality of thin film transistors formed on an insulating surface, comprising: a first step of forming an amorphous silicon film on an insulating surface of a substrate; A second step of sputter etching the surface of the amorphous silicon film, a third step of forming a germanium film in contact with the surface of the amorphous silicon film, and crystallizing the amorphous silicon film by a heat treatment. A fourth step of transforming the substrate to a polysilicon film, wherein the substrate is not exposed to the atmosphere from the second step to the fourth step. 3. The method according to claim 1, wherein the germanium film is formed by a sputtering method in the third step. 4. A method for manufacturing a semiconductor device having a circuit using a plurality of thin film transistors formed on an insulating surface, comprising: a first step of forming an amorphous silicon film on an insulating surface of a substrate; A second step of forming a mask insulating film having an opening in contact with the film; and a third step of sputter etching the surface of the amorphous silicon film exposed at the opening using an inert gas. A fourth step of forming a germanium film in contact with the surface of the amorphous silicon film in the opening, and a fifth step of crystallizing the amorphous silicon film by heat treatment and transforming the amorphous silicon film into a polysilicon film; And after the second step, until the germanium film is formed in the fourth step, The method for manufacturing a semiconductor device characterized by not expose the molar Fast silicon film surface to the air atmosphere. 5. A method for manufacturing a semiconductor device having a circuit using a plurality of thin film transistors formed on an insulating surface, comprising: a first step of forming an amorphous silicon film on an insulating surface of a substrate; A second step of forming a mask insulating film having an opening in contact with the film; and a third step of sputter etching the surface of the amorphous silicon film exposed at the opening using an inert gas. A fourth step of forming a germanium film in contact with the surface of the amorphous silicon film in the opening, and a fifth step of crystallizing the amorphous silicon film by heat treatment and transforming the amorphous silicon film into a polysilicon film; Wherein the substrate is not exposed to an air atmosphere from the second step to the fifth step. A method for manufacturing the body of the device. 6. The semiconductor device according to claim 4, wherein the opening is formed in the mask insulating film over a region to be a source region and a drain region of the thin film transistor. Production method. 7. The semiconductor device according to claim 4, wherein the opening is formed in the mask insulating film over a region to be a source region or a drain region of the thin film transistor. Production method. 8. The method according to claim 4, further comprising, before the second step, patterning the amorphous silicon film into a shape of an active layer of the thin film transistor. A method for manufacturing a semiconductor device. 9. The method according to claim 4, further comprising, after the fifth step, a step of patterning the polysilicon film to form an active layer of the thin film transistor. A method for manufacturing a semiconductor device. 10. The method for manufacturing a semiconductor device according to claim 4, wherein the germanium film is formed by a sputtering method in the fourth step according to any one of claims 4 to 9.