JPH11288977A - Multiple chip mixed type semiconductor device - Google Patents

Abstract

(57) [Summary] [PROBLEMS] To reduce the size and wiring length of an LSI having a plurality of different functions without arranging the process and the design environment, and the like, in a planar manner without spending time and cost. Into one package so that the realization is realized. SOLUTION: A semiconductor chip 1 (logic LSI) on which integrated circuits having different functions are mounted and a semiconductor chip 2 (D
A memory chip such as a RAM is connected by a metal bump via a metal bump, here a metal ball 7 made of a gold alloy, so that the connection electrode 4 and the connection electrode 6 made of an aluminum alloy face each other. 11 are configured.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-chip mixed type semiconductor device in which a plurality of semiconductor chips are mixed and packaged.

[0002]

2. Description of the Related Art In recent years, the application range of large-scale integrated circuits (LSIs) has rapidly expanded, and L
The quantity of SI is also expanding rapidly. Usually, LSI
It is mounted on a board (or board) incorporated in each application product, a plurality of LSIs are used on the same board, and are electrically connected by wiring on the board.

However, as the integration of LSIs has increased and the number of LSIs mounted on a substrate has increased, the LS
Even if the miniaturization of I itself is promoted, the area of the whole substrate will eventually increase, and the wiring length will also increase.

[0004] A technique for reducing the total area of a substrate on which a large number of LSIs are mounted and reducing the wiring length between a plurality of LSIs is a so-called embedded technique. The embedding technique is a technique for forming a plurality of LSIs having different functions in the same chip. For example, a dynamic random access memory (DRAM) and an LSI other than a DRAM such as a logic LSI are formed on the same substrate by the same process,
The one-chip LSI is called an embedded DRAM, and an LSI that incorporates a microcomputer, a DRAM, a read-only memory (ROM), and the like and functions as a system with one chip is a system LSI. It is called.

However, in order to realize the embedded technology, it is necessary to manufacture heterogeneous functional parts which are usually manufactured in different wafer processes by the same process. Process development is required. When a new process is developed, it is necessary to prepare a design-related environment, such as building a library based on the new process. Therefore, when a new embedding technology is started, costs and time are required for developing a new process and preparing a design environment, which causes problems such as an increase in manufacturing costs and a delay in introduction to the market.

As a technique for reducing the total area of a substrate on which a plurality of LSIs are mounted and reducing the wiring length between the plurality of LSIs,
Before the embedding technology was devised, the multi-chip module (MCM) technology has been widely put into practical use. In this MCM technology, a plurality of bare chips are mounted on one substrate, and one package is provided for each substrate.

In the MCM technology, the LSI used
Can be manufactured separately, and unlike embedded technology, there is no need to mix and match processes and develop new processes. Does not occur.

However, in this MCM technique, since a plurality of bare chips are arranged in a plane, it causes an increase in the total area. In this case, although it is more advantageous than packaging for each chip, the size reduction effect is reduced as compared with the embedded technology.

An example of the invention for reducing the inductance of a plurality of semiconductor chips mounted on a lead frame is disclosed in Japanese Patent Application Laid-Open No. Hei 6-120415.
No. 6,086,045.

[0010]

As described above, the embedding technique and the MCM technique each have advantages and disadvantages, and a semiconductor device having only the advantages of both, ie, a plurality of L
In addition to reducing the total area of the SI and shortening the wiring length of multiple LSIs, semiconductor devices that do not cause problems such as crowded processes, increased costs associated with process development, and delays in market introduction. It is in the current state of development.

Accordingly, the present invention has been made to solve such a problem, and an LSI having a plurality of different functions can be used without spending time and money for process development and design environment maintenance. It is an object of the present invention to provide a multiple-chip mixed-type semiconductor device that can be integrated into one package so as to realize a reduction in size and a reduction in wiring length as compared with a case of planar arrangement.

[0012]

According to the present invention, there is provided a multi-chip mixed type semiconductor device, comprising: a first semiconductor chip having a first integrated circuit and a first connection electrode; At least one second semiconductor chip provided with two connection electrodes, and a metal bump disposed between a first connection electrode of the first semiconductor chip and a second connection electrode of the second semiconductor chip. And connecting the first semiconductor chip and the second semiconductor chip, and at least one between the first connection electrode and the metal bump or between the second connection electrode and the metal bump, 1st or 2nd
Are connected via a layer formed of a material for improving the affinity between the connection electrode and the surface material of the metal bump.

In one embodiment of the present invention, at least one surface of the first connection electrode and the second connection electrode is formed of a material having a high affinity for a surface material of the metal bump.

In one embodiment of the present invention, the first semiconductor chip has an external connection electrode for connecting to an external terminal.

In one embodiment of the present invention, the back surface of the first semiconductor chip is fixed on one type of fixing means selected from a printed circuit board, a tape substrate, a ceramics substrate, and a lead frame. The external connection electrodes of the semiconductor chip and the fixing means are connected by bonding wires.

In one embodiment of the present invention, another metal bump is provided on the external connection electrode of the first semiconductor chip.

In one embodiment of the present invention, the gap between the first semiconductor chip and the second semiconductor chip is formed of an insulating resin, an insulating tape, a resin mixed with insulating particles, and an insulating particle. Embedded with one selected from tapes mixed with.

In one embodiment of the present invention, part or all of the first semiconductor chip and the second semiconductor chip are covered with a mold insulating resin.

In one embodiment of the present invention, a part or the whole of the first semiconductor chip and the second semiconductor chip is covered with a mold insulating resin, and the external connection of the first semiconductor chip is performed. Part of the other metal bump provided on the electrode is exposed from the surface of the mold insulating resin.

In one embodiment of the present invention, the metal bump and / or the other metal bump have a melting point of 30.
It is made of a metal or alloy at 0 ° C. or higher, and at least one of the first and second connection electrodes is thermocompression-bonded to the external connection electrode.

In one embodiment of the present invention, the metal bumps and / or the other metal bumps include gold, a gold alloy,
It is a stud bump made of one selected from copper, copper alloy, tin and tin alloy.

In one embodiment of the present invention, the metal bump and / or the other metal bump have a diameter of 0.8 mm.
The following metal balls are connected to the first and second connection electrodes and / or
Alternatively, it is formed by bonding to the external connection electrode.

In one embodiment of the present invention, the metal bump and / or the other metal bump have a diameter of 20 μm or less.
It is a 250 μm metal ball.

In one embodiment of the present invention, at least one metal film is formed on the surface of the first and second connection electrodes and / or the external connection electrodes. Connected to the metal bump.

In one embodiment of the present invention, the first semiconductor chip is a logic chip, and the second semiconductor chip is a memory chip.

In one embodiment of the present invention, the first and second semiconductor chips are memory chips having different configurations and functions.

In one embodiment of the present invention, the first and second semiconductor chips are supported by inner leads and fixed to a lead frame or a TAB tape.
The inner leads are sandwiched and connected to the respective metal bumps connecting the first and second semiconductor chips.

One embodiment of the present invention further comprises at least one third semiconductor chip each having a third integrated circuit and a third connection electrode, wherein the second semiconductor chip and the third semiconductor chip are provided. The semiconductor chip and the back surface are bonded and fixed to each other.

According to the semiconductor device of the present invention,
A first semiconductor chip provided with a first integrated circuit and a first connection electrode, and at least one second semiconductor chip each provided with a second integrated circuit and a second connection electrode; The first semiconductor chip and the second semiconductor chip form at least one type of metal bump having affinity with the material of the first and second connection electrodes at each of the first and second connection electrodes. And are connected by the metal bump.

According to the semiconductor device of the present invention,
A first semiconductor chip provided with a first integrated circuit and a first connection electrode, and at least one second semiconductor chip each provided with a second integrated circuit and a second connection electrode; A first semiconductor chip and the second semiconductor chip each having at least one kind of metal conductor having an affinity with a material of the first and second connection electrodes at each of the first and second connection electrodes; And are connected by the metal conductor.

[0031]

According to the present invention, a multiple-chip mixed type semiconductor device includes first and at least one second semiconductor chips each having an independent integrated circuit formed therein (here, each of the second semiconductor chips includes a first semiconductor chip). The integrated circuit may be the same or different.) In addition, at least one second semiconductor chip is stacked on the first semiconductor chip. Therefore, the occupied plane area is significantly reduced as compared with a case where a plurality of chips are arranged in a plane on a substrate, for example. Here, the first and second semiconductor chips are positioned so that connection electrodes provided at predetermined positions on the respective surfaces face each other and are connected by metal bumps. At this time, at least one between the first connection electrode and the metal bump or between the second connection electrode and the metal bump is interposed via a layer formed of a material that improves the affinity between the connection electrode and the surface material of the metal bump. Connected.

This layer can be realized by, for example, forming a film by depositing a metal having a high affinity with the surface material of the metal bump on the surface of the connection electrode. In addition, by selecting a metal having a high affinity for the surface material of the connection electrode on the metal bump, or by forming a film by depositing a metal having a high affinity for the surface material of the connection electrode on the surface of the metal bump, etc. Can obtain the same effect.

As described above, since the materials for the connection electrodes and the metal bumps are selected, when the first and second semiconductor chips are connected by the metal bumps, the connection is easily and reliably performed, and various functions are provided. Each semiconductor chip can be made into one chip, and further miniaturization can be easily realized.

[0034]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Some preferred embodiments to which the present invention is applied will be described below in detail with reference to the drawings.

(First Embodiment) First, a first embodiment will be described. FIG. 1 is a cross-sectional view illustrating a main part of the semiconductor device according to the first embodiment. This semiconductor device
As shown in FIG. 1A, a semiconductor chip 1 and a semiconductor chip 2 are formed as a laminated chip 11 with their surfaces facing each other.

The semiconductor chip 1 has a size of 9 mm × 9 m.
m, which is a logic LSI having a logic circuit 3 formed on the surface thereof, and having a connection electrode 4 for connecting to the semiconductor chip 2. The connection electrodes 4 are arranged in parallel at predetermined intervals along two opposing sides of the semiconductor chip 1. Further, on the surface of the semiconductor chip 1, an external connection electrode 5 for connection to the outside is formed outside the connection electrode 4. These connection electrodes 4 and external connection electrodes 5
Are both formed using an aluminum alloy as a material.

The size of the semiconductor chip 2 is 9 mm × 9 m.
m, which is a memory LSI having a memory circuit 8 formed on its surface, for example, a DRAM, and has a connection electrode 6 for connecting to the semiconductor chip 1 at a position corresponding to the connection electrode 4 of the semiconductor chip 1. . Similarly to the connection electrode 4, the connection electrode 6 is formed using an aluminum alloy as a material. FIG. 1 shows how a plurality of connection electrodes 6 are formed.
(B). An insulating passivation film (not shown) is formed on the surface of the semiconductor chips 1 and 2 except for the electrodes 4, 5 and 6.

Then, the semiconductor chip 1 and the semiconductor chip 2
Are connected via a metal bump, here a metal ball 7, so that the connection electrode 4 and the connection electrode 6 face each other.
To form a laminated chip 11. The metal ball 7 has a diameter of about 80 μm and a purity of 95%.
Made of a gold alloy. Gold (alloy) is known to have excellent affinity with aluminum (alloy), and good bonding can be obtained.

Here, the connection between the connection electrodes 4 and 6 and the metal ball 7 is performed by thermocompression bonding. In this case, after the metal ball 7 is first joined to the connection electrode 4 of the semiconductor chip 1,
The semiconductor balls 1 and 2 are aligned and the metal balls 7 are joined to the connection electrodes 6. At the time of bonding to the semiconductor chip 1, the back side of the suction array plate in which a hole corresponding to the position of the connection electrode 4 has been previously formed is evacuated to vacuum, and the metal ball 7 is sucked and held in the hole. After joining, they are joined together. At this time, the joining temperature was set to 300 ° C.
The pressure at which the metal balls 7 are bonded to the connection electrodes 4 of the semiconductor chip 1 is 10 g per metal ball 7, and the pressure at which the metal balls 7 are bonded to the connection electrode 6 of the semiconductor chip 2 is 40 g. Here, the metal ball 7 is first joined to the connection electrode 4, but may be joined first to the connection electrode 6 of the semiconductor chip 2.

When the semiconductor chips 1 and 2 are joined, a gap of about 40 μm is formed between them. This gap may be filled with one selected from an insulating resin, an insulating tape, a resin mixed with insulating particles, and a tape mixed with insulating particles.

Here, a predetermined probe is connected to the external connection electrode 5 of the semiconductor chip 1 in the manufactured laminated chip 11 to electrically inspect the connection quality of each adjacent pair of the connection electrodes 6. As a result, no connection failure was observed for any of the electrodes, and it was found that the connection was in an extremely good state.

Although an aluminum alloy was used as a material for the connection electrode and a gold alloy having an excellent affinity for the material was used as the material for the metal ball, the present invention is not limited to this combination. For example, the material of the connection electrode is aluminum (alloy)
In this case, the material of the metal ball is preferably copper (alloy), palladium (alloy), platinum (alloy), or aluminum (alloy) in addition to gold (alloy). Further, the material of the connection electrode may be copper (alloy), and in this case, the material of the metal ball is gold (alloy), copper (alloy), aluminum (alloy), palladium (alloy), platinum (alloy), solder (A tin alloy, a lead alloy, an indium alloy, etc.) are suitable. Furthermore,
The material of the connection electrode may be gold (alloy). In this case, the material of the metal ball is gold (alloy), copper (alloy), aluminum (alloy), platinum (alloy), solder (tin alloy, lead alloy, Indium alloys and the like are preferred. Further, the material of the connection electrode may be palladium (alloy). In this case, the material of the metal ball is gold (alloy), copper (alloy), aluminum (alloy), palladium (alloy), platinum (alloy),
Solder (tin alloy, lead alloy, indium alloy, etc.) is suitable. Further, the material of the connection electrode may be nickel (alloy), and in this case, the material of the metal ball is gold (alloy), copper (alloy), aluminum (alloy), palladium (alloy), platinum (alloy), solder (A tin alloy, a lead alloy, an indium alloy, etc.) are suitable. Further, the material of the connection electrode may be solder (tin alloy, lead alloy, indium alloy, etc.),
In this case, the material of the metal ball is gold (alloy), copper (alloy), aluminum (alloy), palladium (alloy), platinum (alloy), solder (tin alloy, lead alloy, indium alloy, etc.), nickel (alloy) ) Are preferred.

By selecting the above combination, highly reliable bonding between the connection electrodes can be achieved. Different materials may be selected for the connection electrodes. Further, for example, since aluminum (alloy) and solder have poor wettability, a palladium alloy having good wettability with solder is applied to the surface of the connection electrode by a physical vapor deposition method or the like to form a base film for improving wettability. May be formed.

Further, when it is difficult to join the connection electrode and the metal ball, or when it is desired to further improve the joining property, the two can be connected via an anisotropic conductive film, a conductive paste, or the like. It is.

Furthermore, by bonding an optimal metal to only the surface of the metal ball in combination with the connection electrode, it is possible to further improve the bonding property with the connection electrode.

The combination of the integrated circuits mounted on the semiconductor chips 1 and 2 is not limited to the above case, but may be, for example, different memory LSIs. Examples of the memory LSI include an SRAM and a flash memory in addition to the DRAM. When an SRAM and a DRAM are combined, for example, a data processing LSI that requires a memory
May be used in combination. In this case, SRAM is used for data that is frequently used and processed at high speed while frequently changing storage contents, and data that needs to be stored and stored in a large capacity rather than high speed should be stored in DRAM. Becomes possible.

When the SRAM and the flash memory are combined, for example, it is conceivable that the SRAM and the flash memory are used in combination with a signal processing LSI for processing signals at high speed according to a certain program. In this case, if the program is stored in the flash memory, the same program processing can be performed because the program is not erased even when the power is turned off. An SRAM may be used to temporarily store the signal being processed during that time.

Further, in FIG. 1, an integrated circuit provided on the semiconductor chips 1 and 2, here, the logic circuit 3 and the memory circuit 8
Is formed at a portion except immediately below the connection electrodes 4 and 5, but this is because a metal ball 7 made of a gold alloy is used. For example, if a metal ball made of solder is used,
Since thermocompression bonding is not required, an integrated circuit can be formed directly below the connection electrodes 4 and 5.

In the present embodiment, the number of the semiconductor chips 2 mounted on the semiconductor chip 1 is not limited to one.
As shown in FIG. 1C, two semiconductor chips 2 (may be formed with different integrated circuits) on a large semiconductor chip 1 may be provided side by side.

Then, as shown in FIG.
1 is mounted on the substrate 12. Bonding pads 13 are provided on the surface of the substrate 12. As the substrate 12, a ceramics substrate, an insulating tape substrate, a lead frame, or the like can be considered. In this case, the back surface of the semiconductor chip 1 is fixed to the surface of the substrate 12 with an adhesive or the like, and the semiconductor chip 1
The external connection electrode 5 and the bonding pad 13 are connected by a wire bonding method using a gold wire 14.
Then, as shown in FIG.
By molding the entire surface of the composite chip 11 and the entire surface except for a part of the substrate 12, the semiconductor device of the present embodiment is obtained. Here, S in the insulating resin 15 for molding is used.
The filler as iO ₂ particles having a small diameter of 20 μm or less is used, and the gap between the semiconductor chips 1 is about 40 μm as described above. In this case, it is necessary to embed an insulating tape or the like in the gap. Is not enough.).

As described above, the semiconductor device of the first embodiment includes the semiconductor chips 1 and 2 on which independent integrated circuits are formed, and the semiconductor chip 2 is stacked on the semiconductor chip 1. It is configured. Therefore,
The occupied plane area is remarkably reduced as compared with a case where a plurality of chips are arranged in a plane on a substrate, for example. here,
The semiconductor chips 1 and 2 are connected via metal bumps, for example, metal balls 7 having an affinity for the connection electrode material so that the connection electrodes 4 and 6 provided at predetermined positions on the respective surfaces face each other. Both are connected. Therefore,
The wiring length between the semiconductor chips 1 and 2 is so short as to be almost negligible, so that each semiconductor chip having various functions can be made into one chip, and further miniaturization can be easily realized.

Therefore, according to the semiconductor device of the first embodiment, an LSI having a plurality of different functions is arranged in a planar manner without spending time and money for process development and design environment maintenance. It is also possible to make one package so that the size and the wiring length can be reduced.

Hereinafter, some modifications of the semiconductor device according to the first embodiment will be described. Note that components and the like corresponding to the semiconductor device of the first embodiment are denoted by the same reference numerals and description thereof is omitted.

-Modification 1- First, a semiconductor device of Modification 1 will be described. In this semiconductor device, a composite chip 11 is configured as in the first embodiment, but the resin sealing method of the composite chip 11 and the like are different. In this semiconductor device, as shown in FIG. 4A, the dimensions of the semiconductor chips 1 and 2 of the composite chip 11 are the first.
Slightly different from that of the embodiment, the semiconductor chip 1
mm × 12 mm, and the semiconductor chip 2 has a size of 5 mm × 5 mm.

The connection electrodes 4 and the external connection electrodes 5 formed on the semiconductor chip 1 are each made of an aluminum alloy as in the first embodiment, but each of the connection electrodes 4 and 5 is directed outward from the chip surface. Chrome (C
r), a base film (not shown) for improving wettability is formed in the order of Cu (copper) and Au (gold). The Au surface of the connection electrode 4 is joined to the metal ball 7 made of a gold alloy, while the connection electrode 6 made of an aluminum alloy of the semiconductor chip 2 is joined to the metal ball 7.

Further, the external connection electrode 5 has a metal ball 7
A metal ball 16 made of a solder having a larger diameter is joined. Here, the metal ball 7 has a diameter of 60 μm, and the metal ball 16 has a diameter of 500 μm. The metal ball 7 is bonded to the connection electrodes 4 and 6 by thermocompression as described above, and the metal ball 16 is first fixed on the external connection electrode 5 by using the adhesive force of the flux, and then the semiconductor chip 1 is soldered. Is heated to 183 ° C. or more, which is the melting point of the above, and the metal balls 16 are joined to the external connection electrodes 5 by reflow.

Then, the space between the semiconductor chips 1 and 2 is filled and, as shown in FIG. 4A, the metal ball 16 is covered with an epoxy-based insulating resin 15 so that the tip portion is exposed. Here, the metal balls 16 exposed from the surface of the insulating resin 15 function as bumps for external connection. In addition, by exposing the back surface of the semiconductor chip 2, heat radiation can be improved.

In the first modification, the semiconductor chip 1
Alternatively, the present invention can be applied to a case where a substrate on which an integrated circuit is not formed is used. Also, various materials as described in the first embodiment may be used for the material of each metal ball.

According to the semiconductor device of the first modification, in addition to the functions and effects of the semiconductor device of the first embodiment described above, the composite chip 11 sealed with the insulating resin 15 is attached to, for example, an external substrate. Can be connected by the exposed metal balls 16, which can greatly contribute to further shortening of the wiring length and further downsizing of the entire device.

As shown in FIG. 4B, an external connection electrode 5 is formed on the back surface of the semiconductor chip 1 via a via hole formed in the semiconductor chip 1, and a metal ball is provided on the external connection electrode 5. 16 may be joined.

Modification 2 Next, a semiconductor device of Modification 2 will be described. In this semiconductor device, a composite chip 11 is configured as in the first embodiment, but the substrate on which the composite chip 11 is mounted is different. As shown in FIG. 5, the semiconductor device is formed by a lead-on-chip (LOC) method or a TAB tape. The external connection electrodes 5 of the semiconductor chip 1 and the inner leads 18 of the lead frame or the TAB tape are used. Are joined by stud bumps 19 made of, for example, solder. Here, the inner leads 18 are fixed by an insulating tape 17 made of polyimide or the like to regulate the position.

As shown in FIG. 6, it is also preferable that the bonding is performed using metal balls 20 instead of the stud bumps 19.

According to the semiconductor device of the second modification, in addition to the functions and effects of the semiconductor device of the first embodiment described above, the semiconductor device having the LOC structure can be used to increase the size of the semiconductor device into a relatively small package. A high-density mounting can be achieved by storing chips.

-Modification 3- Next, a semiconductor device of Modification 3 will be described. This semiconductor device has a composite chip 11 similar to the first embodiment, but differs in that a further different semiconductor chip is mounted. In this semiconductor device, as shown in FIG. 7, in a composite chip 11 in which semiconductor chips 1 and 2 are joined, a semiconductor chip 31 is provided on a semiconductor chip 2 so as to be fixed to each other on the back surfaces.

The semiconductor chip 31 includes the semiconductor chips 1 and 2
Similarly to the above, an LSI having a logic circuit or an integrated circuit 21 as a memory circuit formed on the surface thereof, and a bonding pad 22 made of an aluminum alloy for connection to the outside is formed. On the surface of the semiconductor chip 1, bonding pads 23 for connecting to the external connection electrodes 22 of the semiconductor chip 31 are provided.

Then, the semiconductor chip 31 and the semiconductor chip 2 are adhered and fixed on the back surfaces thereof with a predetermined die paste.
And the bonding pad 23 of the semiconductor chip 1 are connected by a wire bonding method using the gold wire 14.

The present invention can be applied to a case where a substrate on which an integrated circuit is not formed is used instead of the semiconductor chip 1. Further, various materials as described in the first embodiment may also be used for the material of the metal ball.

According to the semiconductor device of the third modification, in addition to the functions and effects of the semiconductor device of the first embodiment, even if the semiconductor chip 31 is further laminated on the composite chip 11, It is possible to achieve high integration without impairing the integration.

(Second Embodiment) Next, a second embodiment of the present invention will be described. The semiconductor device of the second embodiment has a composite chip 11 substantially similar to that of the first embodiment, but the bonding of the semiconductor chips 1 and 2 is slightly different. The same components as those in the first embodiment are denoted by the same reference numerals, and description thereof is omitted. FIG. 8 is a cross-sectional view illustrating a main part of the semiconductor device according to the second embodiment. Note that the size of the semiconductor chip 1 is 10 mm × 10 mm as in the first embodiment, and the size of the semiconductor chip 2 is 7 mm × 7 mm.

A metal ball 7 made of a gold alloy having a diameter of about 60 μm is joined to a connection electrode 6 made of an aluminum alloy of the semiconductor chip 2. The surface of the connection electrode 4 made of an aluminum alloy of the semiconductor chip 1 is subjected to a surface treatment in the order of a titanium (Ti) alloy and palladium (Pd), and a metal made of solder having a diameter of about 60 μm is formed on the outermost layer of palladium. The ball 32 is fusion-bonded. Then, the metal ball 7 and the metal ball 32 are aligned with each other.
32 are joined.

The materials of the two kinds of metal balls to be joined are not limited to the gold alloy and the solder, but may be any combination having an excellent affinity, for example, as exemplified in the first embodiment. Other metals (alloys) may be used.

Then, as shown in FIG.
1 is mounted on, for example, a lead frame having a LOC structure or a TAB tape. In this case, the inner leads 18 of the lead frame or TAB tape and the external connection electrodes 5 of the semiconductor chip 1 are joined by metal balls 33 made of a gold alloy. In addition, as a material of the metal ball 33, copper (alloy), solder, or the like may be used instead of the gold alloy, and further, a stud bump or a plating bump may be used instead of the metal ball.

According to the semiconductor device of the second embodiment, in addition to the functions and effects of the semiconductor device of the first embodiment, the restrictions on the material of the connection electrodes provided on the semiconductor chips 1 and 2 are relaxed. Thus, the selection range can be expanded. In addition, by using two types of metal balls for bonding, the separation distance (gap) between the semiconductor chips 1 and 2 becomes slightly larger within a range that does not affect the wiring length. Even if it occurs, the occurrence of a short circuit or the like is avoided. Therefore, it further contributes to the improvement of product reliability.

-Modification- Here, a modification of the semiconductor device of the second embodiment will be described. This semiconductor device has a composite chip 11 similar to the first embodiment, but has a lead frame or T
The mounting method on the AB tape is different. Note that components and the like corresponding to the semiconductor device of the second embodiment are denoted by the same reference numerals and description thereof is omitted.

In the semiconductor device according to this modification, the manufactured composite chip 11 is not mounted on a lead frame, but is connected to the inner leads 18 at the same time when the composite chip 11 is formed. That is, in this semiconductor device, as shown in FIG. 10, the metal balls 41 on the connection electrodes 4 of the semiconductor chip 1 and the connection electrodes 6 of the semiconductor chip 2
The upper metal ball 42 is fusion-bonded via the inner lead 18 so as to sandwich the inner lead 18. In addition, as a material of the metal balls 41 and 42,
It is possible to use a gold alloy, a solder, or various metals (alloys) described in the first embodiment.

According to the semiconductor device of this modification, the functions and effects of the semiconductor devices of the first and second embodiments described above are obtained.
In addition to the effects, it is not necessary to provide external connection electrodes on the semiconductor chip 1, so that the occupied area of the semiconductor chip 1 can be reduced, for example, the size of the semiconductor chip 2 can be reduced. Therefore, it is possible to contribute to further miniaturization of the semiconductor device.

[0077]

According to the present invention, it is possible to reduce the size and wiring length of an LSI having a plurality of different functions without arranging a flat surface without spending the cost and time for process development and design environment maintenance. Can be integrated into one package so as to realize the shortening of the time.

[Brief description of the drawings]

FIG. 1 is a schematic diagram showing a main configuration of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a schematic cross-sectional view showing a state where a composite chip is mounted on a substrate in the semiconductor device according to the first embodiment of the present invention.

FIG. 3 is a schematic cross-sectional view showing a state in which a composite chip mounted on a substrate is packaged with a mold resin in the semiconductor device according to the first embodiment of the present invention.

FIG. 4 is a schematic cross-sectional view illustrating a main configuration of a semiconductor device of Modification 1 according to the first embodiment of the present invention.

FIG. 5 is a schematic cross-sectional view illustrating a main configuration of a semiconductor device of Modification 2 according to the first embodiment of the present invention.

FIG. 6 is a schematic sectional view showing a main configuration of another example of the semiconductor device of Modification 2 according to the first embodiment of the present invention.

FIG. 7 is a schematic cross-sectional view illustrating a main configuration of a semiconductor device of Modification 3 according to the first embodiment of the present invention.

FIG. 8 is a schematic sectional view showing a main configuration of the semiconductor device according to the first embodiment of the present invention.

FIG. 9 is a schematic cross-sectional view showing a state where a composite chip is mounted on a substrate in the semiconductor device according to the second embodiment of the present invention.

FIG. 10 is a schematic cross-sectional view illustrating a main configuration of a semiconductor device according to a modification according to the second embodiment of the present invention.

[Explanation of symbols]

 1, 2, 31 semiconductor chip 3 logic circuit 4, 6 connection terminal 5 external connection terminal 7, 16, 20, 32, 33, 41, 42 metal ball 8 memory circuit 11 laminated chip 12, 17 substrate 13, 22, 23 bonding Pad 14 gold wire 15 insulating resin 17 insulating tape 18 inner lead 19 stud bump 21 integrated circuit

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁶ Identification symbol FI H01L 25/065 H01L 25/08 B 25/07 25/18 (72) Inventor Kohei Tatsumi 3-35-1 Ida, Nakahara-ku, Kawasaki-shi Nippon Steel Corporation Technology Development Division (72) Inventor Yuichiro Fujiwara 2-6-3 Otemachi, Chiyoda-ku, Tokyo Nippon Steel Corporation (72) Inventor Kenji Shimokawa 3-35 Ida, Nakahara-ku, Kawasaki-shi -1 Nippon Steel Corporation Technology Development Division (72) Inventor Yoji Kawakami 1580 Yamamoto, Tateyama-shi, Chiba Prefecture Nippon Steel Semiconductor Corporation (72) Inventor Butler Douglas 80919 Colorado Springs, Colorado USA Suit 109 Wrist Drive 4815 Inside United Memories Inc.

Claims (19)

[Claims] 1. A first semiconductor chip having a first integrated circuit and a first connection electrode, and at least one second integrated circuit having a same or different second integrated circuit and a second connection electrode, respectively. A metal bump is arranged between a first connection electrode of the first semiconductor chip and a second connection electrode of the second semiconductor chip, and the first semiconductor chip and the second And at least one between the first connection electrode and the metal bump or between the second connection electrode and the metal bump is connected to the first or second connection electrode and the metal bump. Characterized in that they are connected via a layer formed of a material for improving the affinity with the surface material of the semiconductor device. 2. The method according to claim 1, wherein at least one surface of the first connection electrode and the second connection electrode is formed of a material having a high affinity with a surface material of the metal bump. 2. A multiple chip mixed type semiconductor device according to claim 1. 3. The semiconductor device according to claim 1, wherein the first semiconductor chip has an external connection electrode for connecting to an external terminal. 4. The back surface of the first semiconductor chip is fixed on one kind of fixing means selected from a printed board, a tape board, a ceramics board, and a lead frame.
4. The multiple chip mixed type semiconductor device according to claim 3, wherein the external connection electrode of the semiconductor chip is connected to the fixing means by a bonding wire. 5. The multiple chip mixed type semiconductor device according to claim 3, wherein another metal bump is provided on the external connection electrode of the first semiconductor chip. 6. A gap between the first semiconductor chip and the second semiconductor chip is selected from an insulating resin, an insulating tape, a resin mixed with insulating particles, and a tape mixed with insulating particles. The multi-chip mixed type semiconductor device according to any one of claims 1 to 5, wherein the semiconductor device is embedded with one of the types. 7. The semiconductor device according to claim 1, wherein a part or all of the first semiconductor chip and the second semiconductor chip are covered with a mold insulating resin. Semiconductor device with multiple chips. 8. The semiconductor device according to claim 8, wherein a part or all of the first semiconductor chip and the second semiconductor chip are covered with a mold insulating resin, and the first semiconductor chip and the second semiconductor chip are provided on the external connection electrodes of the first semiconductor chip. 7. The multiple chip mixed type semiconductor device according to claim 5, wherein a part of another metal bump is exposed from a surface of the mold insulating resin. 9. The metal bump and / or the other metal bump is made of a metal or an alloy having a melting point of 300 ° C. or more, and at least one of the first and second connection electrodes is in thermal contact with the external connection electrode. The multi-chip mixed type semiconductor device according to any one of claims 1 to 8, wherein the semiconductor device is bonded by pressure bonding. 10. The metal bump and / or the other metal bump is a stud bump made of one selected from gold, gold alloy, copper, copper alloy, tin and tin alloy. Item 9. A multi-chip hybrid type semiconductor device according to any one of Items 1 to 8. 11. The metal bump and / or the other metal bump is formed by joining a metal ball having a diameter of 0.8 mm or less to the first and second connection electrodes and / or the external connection electrode. The multi-chip mixed type semiconductor device according to any one of claims 1 to 10, wherein: 12. The multi-chip mixed semiconductor according to claim 1, wherein the metal bump and / or the other metal bump is a metal ball having a diameter of 20 μm to 250 μm. apparatus. 13. The first and second connection electrodes and / or the external connection electrodes each have at least one metal film formed on a surface thereof, and are connected to the metal bumps via the metal film. 13. The method according to claim 1, wherein
The multi-chip mixed type semiconductor device according to any one of the above items. 14. The multi-chip mixed type according to claim 1, wherein the first semiconductor chip is a logic chip, and the second semiconductor chip is a memory chip. Semiconductor device. 15. The multi-chip mixed-type semiconductor device according to claim 1, wherein said first and second semiconductor chips are memory chips having different functions. 16. The semiconductor device according to claim 16, wherein the first and second semiconductor chips are supported by inner leads to form a lead frame or a TA.
16. The semiconductor device according to claim 1, wherein the inner leads are fixed to a B tape, and the inner leads are sandwiched and connected by the metal bumps connecting the first and second semiconductor chips. 13. The semiconductor device according to item 9. 17. The semiconductor device according to claim 17, further comprising at least one third semiconductor chip each including a third integrated circuit and a third connection electrode, wherein the second semiconductor chip and the third semiconductor chip have opposite back surfaces. The semiconductor device according to any one of claims 1 to 4, and 9 to 16, wherein the semiconductor device is bonded and fixed. 18. A first semiconductor chip having a first integrated circuit and a first connection electrode, and at least one second integrated circuit and a second semiconductor circuit each having a same or different second integrated circuit and a second connection electrode. Wherein the first semiconductor chip and the second semiconductor chip have an affinity with a material of the first and second connection electrodes at each of the first and second connection electrodes. A multi-chip mixed-type semiconductor device characterized by being opposed via at least one type of metal bump and connected by the metal bump. 19. A first semiconductor chip provided with a first integrated circuit and a first connection electrode, and at least one second integrated circuit provided with the same or different second integrated circuit and a second connection electrode, respectively. Wherein the first semiconductor chip and the second semiconductor chip have an affinity with a material of the first and second connection electrodes at each of the first and second connection electrodes. A multi-chip mixed-type semiconductor device characterized by being opposed to each other via at least one kind of metal conductor and connected by the metal conductor.