JPH11289086A - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JPH11289086A JPH11289086A JP15174398A JP15174398A JPH11289086A JP H11289086 A JPH11289086 A JP H11289086A JP 15174398 A JP15174398 A JP 15174398A JP 15174398 A JP15174398 A JP 15174398A JP H11289086 A JPH11289086 A JP H11289086A
- Authority
- JP
- Japan
- Prior art keywords
- region
- conductivity type
- concentration
- drain
- diffusion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 33
- 239000012535 impurity Substances 0.000 claims abstract description 26
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 230000005669 field effect Effects 0.000 claims abstract description 13
- 238000009792 diffusion process Methods 0.000 claims description 35
- 210000000746 body region Anatomy 0.000 claims description 26
- 238000000034 method Methods 0.000 abstract description 30
- 230000015556 catabolic process Effects 0.000 description 8
- 238000002513 implantation Methods 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 238000005468 ion implantation Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 230000003071 parasitic effect Effects 0.000 description 3
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
Landscapes
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、ソース・ドレイン
間耐圧が１５Ｖ以下の低耐圧の横形２重拡散絶縁ゲート
電界効果型トランジスタ（以下ＬＤＭＯＳと称す）及
び、このＬＤＭＯＳを含む半導体集積回路装置に関す
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a low withstand voltage lateral double diffusion insulated gate field effect transistor (hereinafter referred to as LDMOS) having a source-drain withstand voltage of 15 V or less, and a semiconductor integrated circuit device including this LDMOS. .
【０００２】[0002]
【従来の技術】Ｂｉｐｏｌａｒ−ＣＭＯＳ−ＤＭＯＳ
（以下ＢｉＣＤＭＯＳと称す）を混載した半導体集積回
路において、ＤＭＯＳはアンペアレベルの大電流を流す
出力ドライバー回路に主に用いられる。つまり、ＤＭＯ
Ｓの特性としては他の素子に比べ、高駆動能力が求めら
れる。特に、出力回路として相補型のインバータを用い
る場合には、ＮチャネルとＰチャネルの２つの異なった
導電型の高駆動能力を持つＤＭＯＳトランジスタが必要
とされる。同一半導体基板上に２つの異なった導電型の
ＤＭＯＳトランジスタを同時に集積化するには、一般的
にエピタキシャル層を用いたｐｎ接合による素子分離プ
ロセスを採用することで可能となる。2. Description of the Related Art Bipolar-CMOS-DMOS
In a semiconductor integrated circuit (hereinafter referred to as "BiCDMOS"), a DMOS is mainly used for an output driver circuit for flowing a large amperage level current. In other words, DMO
As for the characteristics of S, high driving capability is required as compared with other elements. In particular, when a complementary inverter is used as an output circuit, two different conductivity type DMOS transistors of N-channel and P-channel having high driving capability are required. Simultaneous integration of two DMOS transistors of different conductivity types on the same semiconductor substrate can be achieved generally by employing an element isolation process using a pn junction using an epitaxial layer.
【０００３】図２は従来の、ＮチャネルＬＤＭＯＳとＰ
チャネルＬＤＭＯＳとを同一基板上に同時に形成した１
例の模式断面図である。図のように、一般的にはＰ型半
導体基板１上にＮ型エピタキシャル層２を形成し、この
Ｎ型エピタキシャル層２内に素子を形成する。１０１は
ＮチャネルのＬＤＭＯＳであり、これはＮ型ソース領域
４を含む領域にＰ型低濃度拡散領域５を熱拡散で形成
し、これをＬＤＭＯＳのボディ領域とすることによっ
て、ゲート電極１０下のソース領域とＰ型低濃度領域の
横方向の拡散量の差がチャネル長となるＭＯＳトランジ
スタとなる。このＮチャネルＬＤＭＯＳの外周は、分離
層としてＰ型ウェル層１１とＰ型埋込み層１２とで囲ん
でいる。ここで、Ｐ型ウェル層はＰ型埋込み層に達する
までの深さに拡散して形成される。FIG. 2 shows a conventional N-channel LDMOS and P-channel LDMOS.
Channel LDMOS and 1 formed simultaneously on the same substrate
It is a schematic cross section of an example. As shown in the figure, generally, an N-type epitaxial layer 2 is formed on a P-type semiconductor substrate 1, and an element is formed in the N-type epitaxial layer 2. Reference numeral 101 denotes an N-channel LDMOS, which is formed by forming a P-type low-concentration diffusion region 5 in a region including an N-type source region 4 by thermal diffusion, and using this as an LDMOS body region. The difference in the lateral diffusion amount between the source region and the P-type low-concentration region is a MOS transistor having a channel length. The outer periphery of the N-channel LDMOS is surrounded by a P-type well layer 11 and a P-type buried layer 12 as isolation layers. Here, the P-type well layer is formed by diffusing to a depth that reaches the P-type buried layer.
【０００４】１０２はＰチャネルのＬＤＭＯＳであり、
Ｐ型ウェル層を形成し、その内部に素子を形成する。こ
の場合はＮチャネルのＬＤＭＯＳとは逆に、Ｐ型ソース
領域７を含む領域にＮ型低濃度拡散領域８を熱拡散で形
成し、これをＬＤＭＯＳのボディ領域とし、ゲート電極
１０下のソース領域とＮ型低濃度領域の横方向の拡散量
の差をチャネル長とするＭＯＳトランジスタとしてい
る。ＰチャネルのＬＤＭＯＳの場合は、プロセス条件や
求める素子の性能により異なるが、縦方向や横方向の耐
圧の低下や寄生素子によるリークを防ぐために、ここで
は素子の周囲及び底面を、Ｎ型シンカー及びＮ型埋込み
層で囲んでいる。[0004] 102 is a P-channel LDMOS,
A P-type well layer is formed, and an element is formed therein. In this case, contrary to the N-channel LDMOS, an N-type low-concentration diffusion region 8 is formed in the region including the P-type source region 7 by thermal diffusion, and this is used as the LDMOS body region. The MOS transistor has a channel length that is the difference between the lateral diffusion amount of the N-type low-concentration region. In the case of a P-channel LDMOS, it depends on the process conditions and the performance of the element to be obtained. It is surrounded by an N-type buried layer.
【０００５】ゲート電極は、上記のどの素子も多結晶シ
リコンで形成し、ソース領域及びボディ領域を形成する
ための低濃度拡散領域の不純物注入は、このゲート電極
をマスクとして、ｓｅｌｆ−ａｌｉｇｎでイオン注入法
により図３のように注入する。この時フォトレジスト１
８はドレイン領域に不純物が注入されないようにマスク
するために、ゲート電極の半ばまで覆うようにする。つ
まり、ゲート電極上のフォトレジスト端はソース・ドレ
イン領域のどちらの側にもかからないようにするため
に、ゲート電極のソース領域端からドレイン端までの長
さは十分大きくしておき、フォトレジスト端はその中央
に位置するように設定するとよい。フォトレジストやゲ
ート電極のパターニング時のプロセスばらつきを考慮す
ると、ゲート電極の長さの最小値は１．８μｍ前後であ
る。The gate electrode is formed of polycrystalline silicon in any of the above-mentioned elements, and the impurity implantation of the low concentration diffusion region for forming the source region and the body region is performed by self-align using the gate electrode as a mask. Injection is performed by an injection method as shown in FIG. At this time, photoresist 1
Numeral 8 covers half of the gate electrode in order to mask the impurity from being implanted into the drain region. In other words, the length of the gate electrode from the source region end to the drain end should be sufficiently large so that the photoresist end on the gate electrode does not extend to either side of the source / drain region. Is set to be located at the center thereof. Considering the process variation at the time of patterning the photoresist and the gate electrode, the minimum value of the length of the gate electrode is about 1.8 μm.
【０００６】ドレイン領域については、特にソース・ド
レイン間耐圧が１５Ｖ以下のような、低耐圧の場合、ド
レイン領域もソース領域と同時にゲート電極をマスクと
してｓｅｌｆーａｌｉｇｎにより形成する。以上の工程
により、ＮチャネルＬＤＭＯＳでは、ゲート酸化膜下は
チャネルが形成されるボディ領域と、低濃度ドレインと
なるエピタキシャル領域との２つの領域とからなり、高
濃度ソース領域及び高濃度ドレイン領域は、ボディ領域
側とエピタキシャル領域側に、それぞれゲート電極を中
心として左右に配置される。ＰチャネルＬＤＭＯＳの場
合は、先に述べた低濃度ドレインとなる領域はＰ型ウェ
ル層となり、図２に示すようになる。In the case of a low withstand voltage such as a source-drain withstand voltage of 15 V or less, the drain region is formed simultaneously with the source region by self-align using the gate electrode as a mask. By the above steps, in the N-channel LDMOS, below the gate oxide film, there are two regions: a body region in which a channel is formed, and an epitaxial region serving as a low-concentration drain. , On the body region side and the epitaxial region side, respectively, with the gate electrode as the center. In the case of a P-channel LDMOS, the above-mentioned region to be a low-concentration drain becomes a P-type well layer, as shown in FIG.
【０００７】このゲート電極下の、低濃度ドレインとな
る領域は、高駆動能力を目指す場合、ソース・ドレイン
間耐圧が許容できる限り短い方が望ましい。なぜなら、
この部分はトランジスタ動作中はドレイン寄生抵抗とな
り、トランジスタ動作時の非飽和条件下で駆動電流を低
下させるからである。低濃度ドレインの領域を短くする
ためにはゲート電極のソース端からドレイン端までの長
さを短くすればよい。但しこの長さを短くすると、同時
にソース・ドレイン間耐圧も低下するので、必要とする
耐圧を満たす範囲で短く設定する必要がある。In order to achieve high driving capability, it is desirable that the region under the gate electrode to be a low-concentration drain has as short a source-drain breakdown voltage as possible. Because
This is because the portion becomes a drain parasitic resistance during the operation of the transistor and reduces the drive current under the non-saturation condition during the operation of the transistor. In order to shorten the low-concentration drain region, the length of the gate electrode from the source end to the drain end may be reduced. However, when this length is shortened, the withstand voltage between the source and the drain also decreases, so it is necessary to set the length as short as possible so as to satisfy the required withstand voltage.
【０００８】[0008]
【発明が解決しようとする課題】しかし、従来の方法で
は下記の課題があった。低耐圧ＬＤＭＯＳにおいて、駆
動電流を増加させるために、ゲート電極の長さを短くし
てドレイン寄生抵抗を低減させる場合、ソース・ドレイ
ン間耐圧に余裕があっても、先に述べたようにＬＤＭＯ
Ｓのボディ形成のためのマスク工程時のプロセスばらつ
きの制約により、この長さを１．８μｍ以下にすること
はできない。However, the conventional method has the following problems. In a low-breakdown-voltage LDMOS, if the drain parasitic resistance is reduced by shortening the length of the gate electrode in order to increase the drive current, even if the withstand voltage between the source and the drain has a margin, the LDMO
This length cannot be reduced to 1.8 μm or less due to the limitation of process variation in the mask process for forming the S body.
【０００９】そこで、この発明の目的は、従来のこのよ
うな課題を解決するために、ＬＤＭＯＳのボディ形成の
ためのマスク工程時のプロセスばらつきに左右されずに
駆動電流を増加させることにある。An object of the present invention is to increase the drive current without being affected by process variations in a mask process for forming an LDMOS body in order to solve such a conventional problem.
【００１０】[0010]
【課題を解決するための手段】上記課題を解決するため
に、この発明は、第１導電型の半導体基板と、第1導電型
の半導体基板に互いに間隔を置いて設けられた第１導電
型で高濃度のソース領域及びドレイン領域と、この高濃
度ソース領域を含み高濃度ソース領域を囲む領域に形成
された第２導電型のボディ領域と、高濃度ドレイン領域
を含み高濃度ドレイン領域を囲む領域に形成された第１
導電型の拡散領域と、ソース領域及びドレイン領域との
間の第１導電型の半導体基板及び第２導電型のボディ領
域及び第１導電型の拡散領域の上にゲート絶縁膜を介し
て設けられたゲート電極とを有することを特徴とする、
２重拡散絶縁ゲート電界効果型トランジスタとした。In order to solve the above-mentioned problems, the present invention provides a semiconductor substrate of a first conductivity type and a first conductivity type semiconductor substrate provided on a semiconductor substrate of the first conductivity type at a distance from each other. And a high-concentration source region and a drain region, a second conductivity type body region formed in a region including the high-concentration source region and surrounding the high-concentration source region, and surrounding the high-concentration drain region including the high-concentration drain region The first formed in the region
A first conductive type semiconductor substrate, a second conductive type body region, and a first conductive type diffusion region between a conductive type diffusion region and a source region and a drain region are provided via a gate insulating film. Characterized by having a gate electrode with
A double diffusion insulated gate field effect transistor was used.
【００１１】また、第１導電型の半導体基板と、第１導
電型の半導体基板上に形成された第2導電型のエピタキ
シャル層と、第2導電型のエピタキシャル層に互いに間
隔を置いて設けられた第２導電型で高濃度のソース領域
及びドレイン領域と、エピタキシャル領域内で高濃度ソ
ース領域を含み高濃度ソース領域を囲む領域に形成され
た第１導電型のボディ領域と、高濃度ドレイン領域を含
み高濃度ドレイン領域を囲む領域に形成された第２導電
型の拡散領域とを有する２重拡散縁ゲート電界効果型ト
ランジスタ及び第１導電型の半導体基板上に形成された
第２導電型のエピタキシャル層内であって、第２導電型
のエピタキシャル層の主表面から形成された第１導電型
のウェル層と、ウェル層内に互いに間隔を置いて設けら
れた第１導電型で高濃度のソース領域及びドレイン領域
と、ウェル層内で高濃度ソース領域を含み高濃度ソース
領域を囲む領域に形成された第２導電型のボディ領域
と、高濃度ドレイン領域を含み高濃度ドレイン領域を囲
む領域に形成された第１導電型の拡散領域とを有する２
重拡散縁ゲート電界効果型トランジスタとを含む半導体
集積回路装置とした。A first conductive type semiconductor substrate, a second conductive type epitaxial layer formed on the first conductive type semiconductor substrate, and a second conductive type epitaxial layer are provided at an interval from each other. A second conductivity type high concentration source and drain region, a first conductivity type body region formed in a region including the high concentration source region and surrounding the high concentration source region in the epitaxial region, and a high concentration drain region And a double diffusion edge gate field effect transistor having a second conductivity type diffusion region formed in a region surrounding the high concentration drain region and a second conductivity type formed on a first conductivity type semiconductor substrate. A first conductivity type well layer formed in the epitaxial layer from the main surface of the second conductivity type epitaxial layer; and a first conductivity type high layer provided at a distance from the well layer in the well layer. A second conductivity type body region formed in a region including the high-concentration source region and surrounding the high-concentration source region in the well layer, and a high-concentration drain region including the high-concentration drain region. And a diffusion region of the first conductivity type formed in the surrounding region.
A semiconductor integrated circuit device including a heavy diffusion edge gate field effect transistor.
【００１２】また先の構造で、第１導電型のボディ領域
及び第1導電型の拡散領域が同じ不純物濃度と主表面か
らの領域深さをもち、同時に第２導電型のボディ領域及
び第２導電型の拡散領域が同じ不純物濃度と主表面から
の領域深さをもつことを特徴とする半導体集積回路装置
とした。また、先の構造は、２重拡散縁ゲート電界効果
型トランジスタのゲート電極の長さが、１．６μｍから
２μｍである半導体集積回路装置とした。In the above structure, the body region of the first conductivity type and the diffusion region of the first conductivity type have the same impurity concentration and the region depth from the main surface, and at the same time, the body region and the second conductivity type of the second conductivity type. A semiconductor integrated circuit device is characterized in that the diffusion regions of the conductivity type have the same impurity concentration and the region depth from the main surface. The above structure is a semiconductor integrated circuit device in which the length of the gate electrode of the double diffusion edge gate field effect transistor is 1.6 μm to 2 μm.
【００１３】[0013]
【発明の実施の形態】以下に、この発明の実施例を図面
に基づいて説明する。図１は本発明のＬＤＭＯＳの断面
図である。本発明では、ゲート電極１０の長さを従来よ
り短くしないで、ドレイン領域側からドレインと同じ導
電型の不純物２３をゲート電極をマスクとして、ｓｅｌ
ｆ−ａｌｉｇｎでイオン注入している。この不純物注入
量は、半導体基板濃度よりも高くなるように設定する。
これにより従来よりも低濃度ドレインによる寄生抵抗が
小さくでき、駆動能力を高くすることができる。Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a sectional view of an LDMOS of the present invention. In the present invention, the length of the gate electrode 10 is not shortened than before, and the impurity 23 having the same conductivity type as that of the drain is used as a mask from the drain region side using the gate electrode as a mask.
Ion implantation is performed by f-align. This impurity implantation amount is set to be higher than the semiconductor substrate concentration.
As a result, the parasitic resistance due to the low-concentration drain can be reduced as compared with the related art, and the driving capability can be increased.
【００１４】このドレイン側から注入する不純物は、ゲ
ート電極をマスクとしてｓｅｌｆ−ａｌｉｇｎで形成す
るため、マスクずれによる影響が無く、特性の安定した
ＬＤＭＯＳを得ることができる。さらに、ゲート電極の
長さは従来と同じであるので、従来例で説明したボディ
領域形成時のフォトプロセスばらつきの影響はない。こ
の方法によりドレイン側の不純物濃度が増加するのでソ
ース・ドレイン間耐圧が低下することは考慮する必要が
ある。本発明は、これまでは耐圧に余裕があってもゲー
ト電極の長さをプロセスばらつきの制約により縮小でき
なかった場合に適用することで、純粋に耐圧と駆動電流
のバランスで注入不純物量等を決定することができ、電
気的特性を限界まで追求した高性能を実現できることに
なる。この方法は、Ｎチャネル、Ｐチャネルのどちらの
ＬＤＭＯＳに対しても適用できる。この低濃度拡散領域
２３のイオン注入量としては、１×１０13／ｃｍ2から
１×１０15／ｃｍ2の範囲で設定するとよい。Since the impurity to be implanted from the drain side is formed by self-alignment using the gate electrode as a mask, an LDMOS with stable characteristics can be obtained without being affected by mask shift. Further, since the length of the gate electrode is the same as that of the related art, there is no influence of the variation in the photo process when the body region is formed as described in the related art. It is necessary to consider that the impurity concentration on the drain side is increased by this method, so that the withstand voltage between the source and the drain is reduced. The present invention is applied to the case where the length of the gate electrode could not be reduced due to the process variation restriction even if the breakdown voltage has a margin, so that the amount of the implanted impurity and the like can be purely controlled by the balance between the breakdown voltage and the driving current. This makes it possible to realize high performance in which electric characteristics are pursued to the limit. This method can be applied to both N-channel and P-channel LDMOS. The ion implantation amount of the low concentration diffusion region 23 may be set in the range of 1 × 10 13 / cm 2 to 1 × 10 15 / cm 2 .
【００１５】図４はＢｉＣＤプロセスの製造工程を経て
作製されるＮチャネル及びＰチャネルのＬＤＭＯＳを同
時に集積化した場合の模式断面図である。このような両
導電型のＬＤＭＯＳの同時集積化の場合は、一方の導電
型のＬＤＭＯＳ形成時に高濃度ドレイン領域から注入す
る本発明の不純物について、別の導電型のボディ領域に
用いられる低濃度不純物を同時に使うことができる。例
えば、ＮチャネルＬＤＭＯＳの場合は高濃度ドレイン領
域側から、ＰチャネルＬＤＭＯＳのボディ領域に用いら
れるＮ型低濃度不純物を、ＰチャネルＬＤＭＯＳのボデ
ィ領域の不純物注入と同時に行い、ＰチャネルＬＤＭＯ
Ｓの場合は高濃度ドレイン領域側から、ＮチャネルＬＤ
ＭＯＳのボディ領域に用いられるＰ型低濃度不純物を、
ＮチャネルＬＤＭＯＳのボディ領域の不純物注入と同時
に行う。これにより、従来に対してマスク工程の増加が
無いので、純粋に電気特性のみを向上させることができ
るという長所がある。FIG. 4 is a schematic cross-sectional view in the case where N-channel and P-channel LDMOSs manufactured through the BiCD process are simultaneously integrated. In the case of such simultaneous integration of the LDMOSs of both conductivity types, the impurity of the present invention implanted from the high-concentration drain region when forming the LDMOS of one conductivity type is replaced by the low-concentration impurity used in the body region of another conductivity type. Can be used at the same time. For example, in the case of an N-channel LDMOS, an N-type low-concentration impurity used for the body region of the P-channel LDMOS is simultaneously implanted from the high-concentration drain region side with the impurity implantation of the body region of the P-channel LDMOS.
In the case of S, the N channel LD starts from the high concentration drain region side.
P-type low concentration impurities used for the body region of the MOS are
This is performed simultaneously with the impurity implantation into the body region of the N-channel LDMOS. Accordingly, there is an advantage that only the electrical characteristics can be purely improved since there is no increase in the number of mask processes as compared with the related art.
【００１６】その場合の製造プロセスを、本発明特有な
工程のみ具体的に図５（ａ）〜（ｄ）を用いて説明す
る。まず、ＮチャネルＬＤＭＯＳのボディ形成の工程に
おいて、図５（ａ）のようにマスク工程を１回用いて、
Ｐ型低濃度不純物としてボロンをソース領域からイオン
注入法により注入するが、このときこの不純物を同時に
ＰチャネルＬＤＭＯＳのドレイン領域にも注入する。次
に図５（ｂ）のように、ＰチャネルＬＤＭＯＳのボディ
領域形成のために、Ｎ型低濃度不純物としてリンを、Ｐ
チャネルＬＤＭＯＳのソース領域と、ＮチャネルＬＤＭ
ＯＳのドレイン領域に注入する。次に図５（ｃ）のよう
に、注入した不純物を熱拡散で拡散させる。そして図５
（ｄ）のように、通常の方法で、マスク工程を2回用
い、高濃度不純物をソース・ドレインに注入する。以上
の方法により、工程の増加無く、低濃度ドレイン領域の
濃度を増加させることができる。The manufacturing process in that case will be specifically described with reference to FIGS. 5 (a) to 5 (d) only for the steps unique to the present invention. First, in the process of forming the body of the N-channel LDMOS, a mask process is used once as shown in FIG.
As a P-type low-concentration impurity, boron is implanted from the source region by ion implantation. At this time, this impurity is also implanted into the drain region of the P-channel LDMOS. Next, as shown in FIG. 5B, in order to form the body region of the P-channel LDMOS, phosphorus is used as an N-type low-concentration impurity,
Source region of channel LDMOS and N-channel LDM
It is implanted into the drain region of the OS. Next, as shown in FIG. 5C, the implanted impurities are diffused by thermal diffusion. And FIG.
As shown in (d), a high concentration impurity is implanted into the source / drain by using a mask process twice by an ordinary method. According to the above method, the concentration of the low-concentration drain region can be increased without increasing the number of steps.
【００１７】次に実際の特性の例について説明する。図
６は、従来のＮチャネルＬＤＭＯＳのソース・ドレイン
間耐圧のゲート電極長さ依存性であるが、耐圧の仕様を
１５Ｖとした場合、ゲート電極の長さは１．０μｍ近く
まで短縮できる。しかし、先に述べたボディ領域形成時
のフォトプロセスのばらつきを考慮すると、ゲート電極
の長さは１．６μｍから２．０μｍ、平均的には１．８
μｍは必要である。このサイズを採用すると、耐圧仕様
に対しては十分余裕がある。ここで、ゲート電極長を
１．８μｍで、図７のプロセス条件を用いて本発明を採
用し、ドレイン領域からＮ型低濃度不純物を注入する。
この場合でも、ソース・ドレイン間耐圧は１５Ｖ以上の
ものが得られる。Next, an example of actual characteristics will be described. FIG. 6 shows the dependency of the source-drain breakdown voltage of the conventional N-channel LDMOS on the gate electrode length. When the breakdown voltage specification is set to 15 V, the length of the gate electrode can be reduced to nearly 1.0 μm. However, in consideration of the above-described variation in the photo process at the time of forming the body region, the length of the gate electrode is from 1.6 μm to 2.0 μm, and is 1.8 on average.
μm is required. If this size is adopted, there is enough room for the pressure resistance specification. Here, the present invention is adopted with the gate electrode length of 1.8 μm and the process conditions of FIG. 7, and an N-type low concentration impurity is implanted from the drain region.
Even in this case, a source-drain breakdown voltage of 15 V or more can be obtained.
【００１８】図７は、ゲート電極長を１．８μｍとした
場合の、ゲート電圧に対するドレイン電流の関係を、従
来の場合と、本発明の場合とで比較した特性グラフであ
る。この特性で分かるように、本発明は耐圧仕様を満た
しながら、駆動能力を約２０％増加させることができ
る。同様に、ＰチャネルＬＤＭＯＳも図７のプロセス条
件で、耐圧仕様を満たしながら、約２０％の駆動能力の
増加を得ることができる。FIG. 7 is a characteristic graph comparing the relationship between the gate voltage and the drain current when the gate electrode length is 1.8 μm in the conventional case and the present invention. As can be seen from these characteristics, the present invention can increase the driving capability by about 20% while satisfying the withstand voltage specification. Similarly, the P-channel LDMOS can achieve an increase in driving capability of about 20% under the process conditions of FIG. 7 while satisfying the breakdown voltage specification.
【００１９】図７のプロセス条件は、異なった２つの導
電型のＬＤＭＯＳを１つの半導体基板上に同時集積化す
る場合の条件である。このためこの条件で、従来に対し
て工程増無く、上記の特性を得ることができることが分
かる。The process conditions shown in FIG. 7 are conditions when two differently conducting LDMOSs are simultaneously integrated on one semiconductor substrate. Therefore, it can be seen that under these conditions, the above characteristics can be obtained without increasing the number of steps as compared with the conventional case.
【００２０】[0020]
【発明の効果】本発明によれば、低耐圧のＬＤＭＯＳに
おいて、プロセスばらつきの影響を受けることなく、安
定的に駆動能力の増加を実現させることができる。According to the present invention, it is possible to stably increase the driving capability of a low breakdown voltage LDMOS without being affected by process variations.
【図1】図１は、本発明の、ＬＤＭＯＳの模式断面図であ
る。FIG. 1 is a schematic cross-sectional view of an LDMOS of the present invention.
【図2】図２は、従来の、ＬＤＭＯＳを用いた半導体集
積回路の模式断面図である。FIG. 2 is a schematic cross-sectional view of a conventional semiconductor integrated circuit using LDMOS.
【図3】図３は、ＬＤＭＯＳ製作における１工程の模式
断面図である。FIG. 3 is a schematic cross-sectional view of one process in LDMOS fabrication.
【図４】図４は、本発明の、ＬＤＭＯＳを用いた半導体
集積回路の模式断面図である。FIG. 4 is a schematic cross-sectional view of a semiconductor integrated circuit using LDMOS of the present invention.
【図５】図５は、本発明の、ＬＤＭＯＳを用いた半導体
集積回路の製造方法の１部を示した工程断面図である。FIG. 5 is a process sectional view showing a part of a method of manufacturing a semiconductor integrated circuit using LDMOS according to the present invention.
【図６】図６は、従来の、ＮチャネルＬＤＭＯＳにおけ
る、ゲート電極長とソース・ドレイン間耐圧との関係を
表すグラフである。FIG. 6 is a graph showing a relationship between a gate electrode length and a withstand voltage between a source and a drain in a conventional N-channel LDMOS.
【図７】図７は、従来と本発明の、ＮチャネルＬＤＭＯ
Ｓにおける、ゲート電圧と単位チャネル幅あたりのドレ
イン電流との関係を表すグラフである。FIG. 7 shows an N-channel LDMO according to the related art and the present invention.
4 is a graph showing a relationship between a gate voltage and a drain current per unit channel width in S.
１ Ｐ型半導体基板 ２ Ｎ型エピタキシャル層 ３ Ｎ型ドレイン領域 ４ Ｎ型ソース領域 ５ Ｐ型低濃度拡散領域 ６ Ｐ型ドレイン領域 ７ Ｐ型ソース領域 ８ Ｎ型低濃度拡散領域 ９ ゲート絶縁膜 １０ ゲート電極 １１ Ｐ型ウェル層 １２ Ｐ型埋込み層 １３ Ｎ型埋込み層 １４ Ｎ型シンカー １５ Ｎ型拡散領域 １６ Ｎ型埋込み層 １７ Ｎ型シンカー １８ フォトレジスト １９ 第1導電型の半導体基板 ２０ 第1導電型の高濃度ドレイン領域 ２１ 第1導電型の高濃度ソース領域 ２２ 第2導電型のボディ領域 ２３ 第１導電型の低濃度拡散領域 １０１ Ｎチャネル２重拡散絶ゲート電界効果型トラン
ジスタ １０２ Ｐチャネル２重拡散絶ゲート電界効果型トラン
ジスタReference Signs List 1 P-type semiconductor substrate 2 N-type epitaxial layer 3 N-type drain region 4 N-type source region 5 P-type low-concentration diffusion region 6 P-type drain region 7 P-type source region 8 N-type low-concentration diffusion region 9 Gate insulating film 10 Gate Electrode 11 P-type well layer 12 P-type buried layer 13 N-type buried layer 14 N-type sinker 15 N-type diffusion region 16 N-type buried layer 17 N-type sinker 18 Photoresist 19 First conductivity type semiconductor substrate 20 First conductivity type High-concentration drain region 21 first-conductivity-type high-concentration source region 22 second-conductivity-type body region 23 first-conductivity-type low-concentration diffusion region 101 N-channel double-diffused gate field-effect transistor 102 P-channel double Diffusion gate field effect transistor
【手続補正書】[Procedure amendment]
【提出日】平成１０年６月９日[Submission date] June 9, 1998
【手続補正１】[Procedure amendment 1]
【補正対象書類名】図面[Document name to be amended] Drawing
【補正対象項目名】図７[Correction target item name] Fig. 7
【補正方法】変更[Correction method] Change
【補正内容】[Correction contents]
【図７】 FIG. 7
Claims (4)
電型の半導体基板に互いに間隔を置いて設けられた第１
導電型で高濃度のソース領域及びドレイン領域と、前記
高濃度のソース領域を含み前記高濃度のソース領域を囲
む領域に形成された第２導電型のボディ領域と、前記高
濃度のドレイン領域を含み前記高濃度のドレイン領域を
囲む領域に形成された第１導電型の拡散領域と、前記高
濃度のソース領域及びドレイン領域との間の前記第１導
電型の半導体基板及び前記第２導電型のボディ領域及び
前記第１導電型の拡散領域の上にゲート絶縁膜を介して
設けられたゲート電極とを有することを特徴とする、２
重拡散絶縁ゲート電界効果型トランジスタA first conductive type semiconductor substrate; and a first conductive type semiconductor substrate provided at a distance from the first conductive type semiconductor substrate.
A conductive type high-concentration source region and a drain region; a second conductive type body region formed in a region including the high-concentration source region and surrounding the high-concentration source region; and the high-concentration drain region. A semiconductor substrate of the first conductivity type and a second conductivity type between a diffusion region of a first conductivity type formed in a region surrounding the high-concentration drain region and the high-concentration source and drain regions; And a gate electrode provided on the diffusion region of the first conductivity type via a gate insulating film.
Heavy diffusion insulated gate field effect transistor
電型の半導体基板上に形成された第2導電型のエピタキ
シャル層と、前記第2導電型の前記エピタキシャル層に
互いに間隔を置いて設けられた第２導電型で高濃度のソ
ース領域及びドレイン領域と、前記エピタキシャル領域
内で前記高濃度のソース領域を含み前記高濃度のソース
領域を囲む領域に形成された第１導電型のボディ領域
と、前記高濃度のドレイン領域を含み前記高濃度のドレ
イン領域を囲む領域に形成された第２導電型の拡散領域
とを有する２重拡散縁ゲート電界効果型トランジスタ及
び前記第１導電型の半導体基板上に形成された第２導電
型のエピタキシャル層内であって、前記第２導電型のエ
ピタキシャル層の主表面から形成された第１導電型のウ
ェル層と、前記ウェル層内に互いに間隔を置いて設けら
れた第１導電型で高濃度のソース領域及びドレイン領域
と、前記ウェル層内で前記高濃度のソース領域を含み前
記高濃度のソース領域を囲む領域に形成された第２導電
型のボディ領域と、前記ウェル層内で前記高濃度のドレ
イン領域を含み前記高濃度のドレイン領域を囲む領域に
形成された第１導電型の拡散領域とを有する２重拡散縁
ゲート電界効果型トランジスタとを含む半導体集積回路
装置。2. A semiconductor substrate of a first conductivity type, an epitaxial layer of a second conductivity type formed on the semiconductor substrate of the first conductivity type, and a distance between the epitaxial layer of the second conductivity type. A second conductivity type high-concentration source region and a high-concentration source region and a first conductivity type formed in a region including the high-concentration source region and surrounding the high-concentration source region in the epitaxial region. A double diffusion edge gate field effect transistor having a body region and a second conductivity type diffusion region formed in a region including the high concentration drain region and surrounding the high concentration drain region, and the first conductivity type A well layer of a first conductivity type formed in a second conductivity type epitaxial layer formed on a semiconductor substrate according to (1), and formed from a main surface of the second conductivity type epitaxial layer; A first conductive type high concentration source region and a drain region provided at intervals from each other, and a region including the high concentration source region and surrounding the high concentration source region in the well layer. A double diffusion edge gate having a body region of the second conductivity type and a diffusion region of the first conductivity type formed in the well layer and including the high-concentration drain region and surrounding the high-concentration drain region A semiconductor integrated circuit device including a field effect transistor.
1導電型の拡散領域が同じ不純物濃度と主表面からの領
域深さをもち、同時に前記第２導電型のボディ領域及び
前記第２導電型の拡散領域が同じ不純物濃度と主表面か
らの領域深さをもつことを特徴とする請求項２記載の半
導体集積回路装置。3. The first conductivity type body region and the first conductivity type body region.
The diffusion region of one conductivity type has the same impurity concentration and the region depth from the main surface, and at the same time, the body region of the second conductivity type and the diffusion region of the second conductivity type have the same impurity concentration and the region depth from the main surface. 3. The semiconductor integrated circuit device according to claim 2, wherein
ジスタのゲート電極の、前記高濃度のソース領域からド
レイン領域へ向かう方向の長さが、１．６μｍから２μ
ｍであることを特徴とする請求項３記載の半導体集積回
路装置。4. The gate electrode of the double diffusion edge gate field effect transistor has a length in a direction from the high concentration source region to the drain region of 1.6 μm to 2 μm.
4. The semiconductor integrated circuit device according to claim 3, wherein m is m.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15174398A JPH11289086A (en) | 1997-12-24 | 1998-06-01 | Semiconductor integrated circuit device |
| US09/320,111 US6236084B1 (en) | 1998-06-01 | 1999-05-26 | Semiconductor integrated circuit device having double diffusion insulated gate field effect transistor |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP35554097A JP3429654B2 (en) | 1997-12-24 | 1997-12-24 | Method for manufacturing semiconductor integrated circuit device |
| JP9-355540 | 1997-12-24 | ||
| JP15174398A JPH11289086A (en) | 1997-12-24 | 1998-06-01 | Semiconductor integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH11289086A true JPH11289086A (en) | 1999-10-19 |
Family
ID=26480891
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15174398A Pending JPH11289086A (en) | 1997-12-24 | 1998-06-01 | Semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH11289086A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2003067660A1 (en) * | 2002-02-07 | 2003-08-14 | Sony Corporation | Semiconductor device and its manufacturing method |
| JP2014143363A (en) * | 2013-01-25 | 2014-08-07 | Rohm Co Ltd | N-channel double-diffusion mos transistor and semiconductor composite element |
-
1998
- 1998-06-01 JP JP15174398A patent/JPH11289086A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2003067660A1 (en) * | 2002-02-07 | 2003-08-14 | Sony Corporation | Semiconductor device and its manufacturing method |
| US6903424B2 (en) | 2002-02-07 | 2005-06-07 | Sony Corporation | Semiconductor device and its manufacturing method |
| US7009259B2 (en) | 2002-02-07 | 2006-03-07 | Sony Corporation | Semiconductor device and method of fabricating same |
| US7015551B2 (en) | 2002-02-07 | 2006-03-21 | Sony Corporation | Semiconductor device and method of fabricating same |
| JP2014143363A (en) * | 2013-01-25 | 2014-08-07 | Rohm Co Ltd | N-channel double-diffusion mos transistor and semiconductor composite element |
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