JPH11296309A - Playback device - Google Patents

Abstract

(57) [Summary] [Problem] To speed up transfer processing by reducing the processing load on a system control unit. [Solution] When a cache processing means as hardware receives a data transfer request from an external host device, A cache hit determination is performed to determine whether all or a part of the data requested to be transferred is stored in the cache memory means and is transferable. For transferable data, a transfer instruction from the system control means is issued. Execute the transfer output to the host device without waiting. The system control unit receives a data transfer request from an external host device, and the cache processing unit determines that a cache hit determines that some or all of the data requested to be transferred cannot be transferred from the cache memory unit. When it is determined that the data is not transferable, at least the buffering operation is performed, and in response to the data being transferable by the buffering operation, the execution control of the transfer output of the data to the host device is performed. To do.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reproducing apparatus capable of performing a reproducing operation corresponding to a recording medium such as an optical disk in response to an instruction from a host computer or the like, and more particularly to a cache processing at the time of reproducing data. is there.

[0002]

2. Description of the Related Art CD (Compact Disc) type discs as optical disc recording media and DVD (Digital Versatile Disc / Digital) suitable for multimedia applications.
Discs called VideoDisc) have been developed. In a reproducing apparatus corresponding to these optical discs, data is read by irradiating a track on the disc with laser light and detecting the reflected light.

For example, in a reproducing apparatus that performs a disk reproducing operation in response to a read command (data transfer request) from a host computer and transmits the reproduced data to the host computer, data transfer is rapidly performed in response to the read command. It is required to do. The read command usually includes data as a read command,
It is composed of a start position as a transfer request data section and a data length from the start position. That is, the host computer specifies a playback command and a section to be played back.

When a read command is issued, the reproducing apparatus basically performs a seek (access) operation of the optical head and reads data in order to read the requested data. Then, the read data is transferred to the host computer. In such a reproducing apparatus, a so-called cache memory is mounted, and data is output through the cache memory.

[0005] The reproducing apparatus reads the data of the data sector requested by the host computer from the disk, stores the data in the cache memory (buffering), and transfers the data from the cache memory to the host computer. An operation of reading data of a sector following the data sector and storing the data in the cache memory is also performed. This is a so-called prefetch operation.
The next time a data request is made from the host computer, if the requested data is stored in the cache memory (if a cache hit occurs), the data transfer to the host computer is performed without performing disk access. This means that the access time can be apparently reduced. That is, when a data transfer request for successive sectors is continuously issued from the host computer (so-called sequential read).
The pre-read operation to the cache memory is a very effective method in terms of quick data transfer.

[0006] Buffering to the cache memory is usually performed using the cache memory in a ring memory form. That is, LB is stored in the cache memory.
A (Logical Block Address: logical address of a data sector on the disk) stores continuous data, thereby realizing an effect of shortening the time until the transfer is completed in response to a data transfer request as a sequential read. ing.

[0007]

As for the shortening of the transfer process, of course, the reduction of the disk access speed itself (reduction of the time required for seeking, reading data, and decoding from the disk) has been advanced. By doing so, research has been conducted to complete the transfer as quickly as possible even if there is no cache hit. However, in a control unit (for example, a CPU (firmware)) that controls the reproduction operation on the reproduction device side including the cache processing, the processing load is relatively increased as the access speed is reduced.

As a process of the CPU when a data transfer request is made from the host computer, basically, it is first determined whether or not the requested data has a cache hit. If all the requested data hit the cache, the data stored in the cache memory is transferred to the host computer, and the processing ends. However, if a part or all of the requested data does not result in a cache hit (cache miss), the cache-missed data is read from the disk, buffered, and when the buffering is completed, the data is transferred to the host. The process of transferring the data to the computer is performed.

When a cache miss occurs, data is read from the disk in this way, and if the disk access speed is improved, quick transfer should be possible even in such a case. . However, CPU
Controls a series of processes such as cache search, disk reading, buffering, transfer, etc., and is very busy, and naturally the CPU cannot proceed beyond the processing speed, No matter how much the disk access speed is increased, the processing speed of the CPU becomes a bottleneck, command overhead becomes apparent, and the transfer process cannot be sped up.

[0010] Further, it is not preferable that the number of parameters to be managed when performing a cache hit determination increases, because the cache management process becomes complicated and the processing load on the CPU further increases. Therefore, in order to adopt a parameter configuration as simple as possible, a certain limit is imposed on buffering and transfer processing to the cache. For example, by specifying that decoding error data should not be buffered or that data not permitted by copyright protection-related data should be invalidated in the cache memory, decoding error and copyright It is not necessary to provide a parameter such as disapproval by the user. Furthermore, if a different data format is detected during buffering, for example, a method of managing the address whose format has changed, or a restriction that only the same format format is buffered, may be used to perform parameter management. It was simplified. Like these,
Due to various restrictions on cache processing and transfer processing, the system cannot be flexibly handled.

[0011]

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has been made in particular in order to reduce the processing load on a system control unit (firmware) of a reproducing apparatus, thereby realizing a rapid transfer process. And a playback device that enables flexible processing.

For this reason, when a data transfer request is received from an external host device, whether all or a part of the data requested to be transferred is stored in the cache memory means and can be transferred as a playback device. There is provided a cache processing means capable of performing a cache hit determination as to whether or not the transfer is possible and executing transfer output to the host device without waiting for a transfer instruction from the system control means. As the system control means, there is a data transfer request from an external host device, and part or all of the data requested to be transferred cannot be transferred from the cache memory means by the cache hit determination by the cache processing means. When it is determined that the data is not transferable, at least the buffering operation is performed, and in response to the data being transferable by the buffering operation, the execution control of the transfer output of the data to the host device is performed. To do. That is,
Regarding the data having a cache hit, for example, the cache processing means as hardware can automatically execute the transfer without the system control means (firmware) giving a transfer instruction. This eliminates the need for the system control means to control cache hit determination and transfer of cache hit data, thereby reducing the processing load.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A reproducing apparatus using an optical disk as a recording medium will be described below as an embodiment of the present invention.
The optical disc loaded in the reproducing apparatus of this example is, for example,
CD-type discs such as CD-ROM and DVD (DI
A disk called "GITAL VERSATILE DISC / DIGITAL VIDEO DISC" can be considered. Of course, the present invention can be applied to a disc reproducing apparatus corresponding to other types of optical discs. The description will be made in the following order. 1. 1. Configuration of playback device Various parameters 3. 3. Management form using cache management parameters Processing when transfer request occurs5. Modified example

1. Configuration of Reproducing Apparatus FIG. 1 is a block diagram of a main part of the reproducing apparatus of the present embodiment. This playback device performs a data playback operation in response to a request from the connected host computer 100.

The disk 90 is mounted on the turntable 7, and is rotated at a constant linear velocity (CLV) or a constant angular velocity (CAV) by the spindle motor 1 during a reproducing operation. The pickup 1 reads data recorded on the disk 90 in the form of embossed pits or phase change pits. In the pickup 1, a laser diode 4 serving as a laser light source, a photodetector 5 for detecting reflected light, an objective lens 2 serving as an output end of the laser light, and a laser beam are irradiated on the disk recording surface via the objective lens 2. Further, an optical system for guiding the reflected light to the photodetector 5 is formed. The objective lens 2 is held by a biaxial mechanism 3 so as to be movable in a tracking direction and a focus direction.
The entire pickup 1 can be moved in the disk radial direction by a thread mechanism 8.

The reflected light information from the disk 90 is detected by the photodetector 5, converted into an electric signal corresponding to the amount of received light, and supplied to the RF amplifier 9. The RF amplifier 9 includes a current-voltage conversion circuit, a matrix operation / amplification circuit, and the like corresponding to output currents from a plurality of light receiving elements as the photodetector 5, and generates necessary signals by matrix operation processing. For example, it generates an RF signal as reproduction data, a focus error signal FE for servo control, a tracking error signal TE, and the like. The reproduction RF signal output from the RF amplifier 9 is supplied to a binarization circuit 11, and the focus error signal FE and the tracking error signal TE are supplied to a servo processor 14.

The reproduced RF signal obtained by the RF amplifier 9 is 2
By being binarized by the value conversion circuit 11, it is converted into a so-called EFM signal (8-14 modulated signal; in the case of CD) or an EFM + signal (8-16 modulated signal; in the case of DVD), and supplied to the decoder 12. The decoder 12 performs EFM demodulation, error correction processing, and the like.
The information read from the disk 90 is reproduced by performing M decoding, MPEG decoding and the like.

The data decoded by the decoder 12 is accumulated in the cache memory 20 by the operation of the buffer manager 21 which performs read / write processing of the cache memory 20. A so-called buffering operation is performed. As the playback output from the playback device, the data buffered in the cache memory 20 is transferred and output. The transfer and output of data from the cache memory 20 is performed under the control of the system controller 10 (control as firmware). In the case of the present example, the data is provided as a cache processing unit as hardware. Buffer manager 21
However, the transfer output can be executed without waiting for an instruction from the system controller 10. This example is characterized by such an operation, and will be described later in detail.

The interface unit 13 is connected to an external host computer and communicates reproduction data and read commands with the host computer. That is, the reproduction data stored in the cache memory 20 is transferred and output to the host computer 100 via the interface unit 13. A read command and other signals from the host computer 100 are supplied to the system controller 10 via the interface unit 13.

From the focus error signal FE and the tracking error signal TE from the RF amplifier 9 and the spindle error signal SPE from the decoder 12 or the system controller 10, the servo processor 14 performs various servo drives of focus, tracking, thread and spindle. A signal is generated to execute a servo operation. That is, the focus error signal FE and the tracking error signal T
A focus drive signal and a tracking drive signal are generated according to E and supplied to the two-axis driver 16. The two-axis driver 16 drives the focus coil and the tracking coil of the two-axis mechanism 3 in the pickup 1. As a result, a tracking servo loop and a focus servo loop are formed by the pickup 1, the RF amplifier 9, the servo processor 14, the two-axis driver 16, and the two-axis mechanism 3.

The servo processor 14 sends a spindle error signal SP to the spindle motor driver 17.
The spindle drive signal generated according to E is supplied. The spindle motor driver 17 applies, for example, a three-phase drive signal to the spindle motor 6 according to the spindle drive signal, and executes the CLV rotation of the spindle motor 6. Further, the servo processor 14 generates a spindle drive signal in response to a spindle kick / brake control signal from the system controller 10, and causes the spindle motor driver 17 to execute operations such as starting or stopping the spindle motor 6.

The servo processor 14 generates a thread drive signal based on, for example, a thread error signal obtained as a low-frequency component of the tracking error signal TE or an access execution control from the system controller 10 and supplies the thread drive signal to the thread driver 15. . The thread driver 15 responds to the thread drive signal by the thread mechanism 8.
Drive. Although not shown in the thread mechanism 8, a main shaft for holding the pickup 1, a thread motor,
The pickup 1 has a required sliding movement by having a mechanism such as a transmission gear and driving the sled motor 8 by the sled driver 15 according to the sled drive signal.

The laser diode 4 in the pickup 1 is driven by a laser driver 18 to emit laser light. The system controller 10 sets the control value of the laser power in the auto power control circuit 19 when executing the reproducing operation on the disc 90, and the auto power control circuit 19 performs the laser output according to the set laser power value. The laser driver 18 is controlled so as to be operated.

When the apparatus is capable of performing a recording operation, a signal modulated according to recording data is applied to the laser driver 18. For example, when recording is performed on a recordable type disc 90, the recording data supplied from the host computer to the interface unit 13 is added with an error correction code by an encoder (not shown),
After processing such as EFM + modulation is performed, the data is supplied to the laser driver 18. Then, the laser driver 18 causes the laser diode 4 to perform a laser emission operation according to the recording data, so that data recording on the disk 90 is performed.

The above-described various operations such as servo, decoding, and encoding are controlled by a system controller 10 formed by a microcomputer.
For example, as a series of reproduction operation control, the system controller 10 issues a command to the servo processor 14 as an operation for reading a requested data section in response to a read command from the host computer 100, and transfers the read data with the read command. The access operation of the pickup 1 targeting the start position of the requested data section is executed. After the access is completed, the data reading is performed, the decoder 12 and the cache memory 20 perform necessary processing, and the reproduced data (the requested data) is transmitted from the interface unit 13 to the host computer 100.
Is controlled to be transferred.

A read command from the host computer 100, that is, a transfer request, includes a transfer request start address, which is the first address of a requested data section, and a requested data length (hereinafter, referred to as a length) from the first address. ). For example, a transfer request with a transfer request start address = N and a length = 3 is:
It means a data transfer request of three sectors of LBA “N” to LBA “N + 2”.

2. Various Parameters Subsequently, parameters (cache management parameters) used for managing the cache memory and parameters (search condition setting parameters) used for a search operation for determining a cache hit state in the cache memory in this example will be described. These parameters are all set and managed by the system controller 10 (firmware).

First, as the cache management parameters,
As shown in FIG. 2, the standard LBA (BLBAMIN), the standard LBA pointer (BLBAMINPT), the number of valid sectors (SCTVALID), and the number of stored sectors (SCTOL)
D) are set.

The reference LBA (BLBAMIN) is set when buffering in the cache memory 20 is started, and is the value of the address (LBA) of the starting sector of the buffering operation. The standard LBA pointer (BLBAMINPT) becomes a value indicating the area address of the cache memory 20 in which the sector indicated by the standard LBA is stored by starting the buffering.
For example, for the sake of explanation, as shown in FIG.
Is provided with ten areas each of which can store one sector as buffer areas # 0 to # 9.
The value of the area “#x” is obtained.

The number of effective sectors (SCTVALID) is
The value indicates the number of valid sectors in which the address (LBA) continues in ascending order from the standard LBA. As described above, at the time of buffering, data for which the error check is OK in the decoder 12 is stored in the cache memory 20. At this time (that is, when a decoder interrupt occurs), the value as the number of effective sectors is set. Will be incremented. In the case of a CD, a decoder interrupt is generated in units of one sector, and the value as the number of effective sectors is incremented by one in synchronization with that. In the case of a DVD, one ECC block is formed in units of 16 sectors. And therefore 1
Since a decoder interrupt occurs in units of 6 sectors, the value as the number of effective sectors is incremented by 16.

The number of stored sectors (SCCTLD) is a value indicating the number of valid sectors in which the address (LBA) continues in descending order from the standard LBA. Alternatively, it can also be referred to as the number of fixed sectors to be secured as a margin during buffering. This is set when the parameters are updated, that is, when the buffering is started and the above parameters are being reproduced. That is, at the start of buffering, the value indicates the number of valid data among the data buffered in the past.

Next, search condition setting parameters are shown in FIG. As search condition setting parameters, search LBA (T
GTADR), the number of search sectors (TGTSCT), the search format (SRCHFMT), the transfer format (XFRFMT), and the transfer phase (CDMTRM) are prepared. These parameters are set by the system controller 10 to make the buffer manager 21 determine the cache hit status when a transfer request is made from the host computer 100.

The search LBA (TGTADR) is set to the first address for performing a cache search. That is,
The start address corresponds to the transfer request start address supplied from the host computer 100. The number of search sectors (TGTSCT) is set to the number of sectors from the first address for performing a cache search. That is, the value of the length supplied from the host computer 100 together with the transfer request start address is set as the value of the number of search sectors.

The search format (SRCHFMT) is
It indicates the format of the data to be cache searched. Specifically, Mode1, Mode
2 / Form1, Mode2 / Form2. The transfer format (XFRFMT) defines a transfer format when the buffer manager 21 automatically performs data transfer to the host computer 100 (without an instruction from the system controller 10) due to a cache hit. The transfer phase (CDMTRM)
As a result of the cache search, when all hits occur (when all the sectors requested to be transferred by the host computer 100 hit the cache), the data transfer phase is designated, that is, Transfer to Transfer or Transfer to Stat.
Specify e.

In actual operation, various parameters other than the parameters shown in FIGS. 2 and 3 are used. For example, a search instruction to the buffer manager 21,
Necessary parameters are also set and used for operations such as a search end notification from the buffer manager 21 and a notification of the number of cache hit sectors, but these will not be described.

3. FIG. 4 illustrates a management mode of the cache memory 20 based on the cache management parameters described above. As described above, the cache memory 20 has the area # as the buffer area.
0 to # 9 are provided, and buffering for a maximum of 10 sectors can be performed. Now, the sector of the LBA in the cache memory 20 is buffered, and as a new buffering, areas # 1 to # 3 are used as shown in FIG.
It is assumed that buffering of BA11 to LBA13 has been performed.

When this buffering is started, the standard LBA = LBA11 and the standard LBA pointer =
It will be set to # 1. Further, the number of effective sectors is incremented in accordance with the buffering of the sectors after the LBA 11, so that the number of effective sectors = 3 when the buffering up to the LBA 13 is performed. . Also, the current buffering is not sequential data with the data (~ LBA50) previously buffered, and the past buffering data is not validated, so that the current buffering start time And the number of storage sectors = 0.

When buffering for three sectors LBA11 to LBA13 is performed in this way, LBA11 to LBA13 stored in areas # 1 to # 3 are indicated as valid sectors by the value of each parameter. Will be. For example, when the cache hit situation is searched at a later point in time, the sector validated by each parameter is to be searched.

Subsequently, at some point, as shown in FIG.
It is assumed that buffering of sectors LBA14 to LBA18 has been performed in areas # 4 to # 8. When this buffering is started, the standard LBA = LBA1
4. The standard LBA pointer is set to # 4. In addition, the number of effective sectors is incremented in accordance with the buffering of the sectors after the LBA 14, so that the number of effective sectors = 5 when the buffering up to the LBA 18 is performed. . Also, this buffering is performed for the data (LBA11 to LBA1) previously buffered.
From 3), it is sequential data, and it is preferable to make these past buffered data valid.
Therefore, the number of stored sectors is set to 3 at the start of buffering.

When buffering for five sectors LBA14 to LBA18 is performed in this way, LBA11 to LBA18 stored in areas # 1 to # 8 are indicated as valid sectors according to the value of each parameter. Will be. That is, the number of valid sectors is the sum of the number of valid sectors and the number of storage sectors, and the LBA and storage location of each of those sectors are the standard LBA and the standard LBA.
It can be calculated from each value of the pointer.

Actually, in order to cope with the Granularity Test, one or more sectors of the past buffering data (data managed by the number of storage sectors) are secured. Then, when buffering, the sum of the number of effective sectors and the number of saved sectors can secure the specified number,
The amount of cache data to be updated is determined.

4. Processing when Transfer Request Occurs Hereinafter, the operation of the playback device when a transfer request is made from the host computer 100, that is, the operation of the system controller 10 and the buffer manager 21, will be described.
FIGS. 5 to 8 show processing of the system controller 10 and the buffer manager 21. The buffering operation examples and transfer operation examples of FIGS. 9 to 12 will be described together with this flowchart. The processing of the system controller 10 is shown in the step F100, and the processing of the buffer manager 21 is shown in the step F200.

When a transfer request is issued from the host computer 100, the system controller 10
As 101, a transfer request receiving process is performed. That is, the transfer request start address and length are fetched. Subsequently, in step F102, various parameters for searching for a cache hit status are set in accordance with the transfer request.

First, the value of the transfer request start address is set as the value of the search LBA (TGTADR). The length value is set as the value of the number of search sectors (TGTSEC). Furthermore, the search format (SRCHF
MT), transfer format (XFRFMT), and transfer phase (CDMTRM) are set according to the situation. After setting the above search condition setting parameters, the buffer manager 21 is instructed to perform a cache search, that is, a search for a cache hit status.

The buffer manager 21 proceeds to step F20.
In step 1, each search condition setting parameter is confirmed according to the cache search instruction, and the cache search is executed in step F202. This cache search is performed using a search LBA (TGTAD) as a search condition setting parameter.
R), the number of search sectors (TGTSEC), and the search format (SRCHFMT), and cache management parameters managed by the system controller 10, that is, standard LBA (BLBAMIN), standard LBA
Pointer (BLBAMINPT), number of valid sectors (S
CTVALID) and the number of storage sectors (SCTOLD).

Here, the cache hit determination condition is (BLBAMIN) − (SCTOLD) ≦ (requested LBA) ≦ (BLBAMI)
N) + (SCTVALID) -1. The requested LBA is the LBA of each sector requested to be transferred from the host computer 100, that is, the transfer request start address (= the number of search sectors (TGTSE)
C)) and length (number of search sectors (TGTSEC))
Are the respective LBAs of each sector indicated by. For example, if the transfer request start address = LBA1 and the length = 3, the request LBA referred to in the above determination condition
Means that LBA1, LBA2, and LBA3 correspond to each other, and it is determined whether or not each of the requested LBAs satisfies the above-described determination condition.

The first term as the above-mentioned determination condition, that is, “standard LBA (BLBAMIN) −the number of stored sectors (SCTOLD)” is
This indicates the minimum LBA of the sector in the cache memory 20 recognized as valid by the system controller 10. As described above, the number of stored sectors is the number of effective sectors arranged in descending order from the standard LBA.
(BLBAMIN) = LBA10, number of saved sectors (SCTOLD)
= 3, the LBA depends on the number of stored sectors.
9, LBA8, LBA7 will be treated as valid, so the first term is now LBA10-3 = LBA7
This is the effective minimum LBA.

The third condition as the above-mentioned judgment condition, that is, “standard LBA (BLBAMIN) + the number of valid sectors (SCTVALID) +
"1" indicates the maximum LBA of a sector in the cache memory 20 recognized as valid by the system controller 10. In other words, it is the last LBA that has been prefetched continuously from the LBA that started buffering. “−1” is an operation for subtracting the reference LBA (BLBAMIN) itself. For example, standard LBA (BLBAMIN) = LBA
10. If the number of valid sectors (SCTVALID) = 5,
By this, LBA10, LBA11, LBA12, L
BA13 and LBA14 will be represented as effective sectors, and the third term is LBA10 + 5-1 =
LBA 14 indicates the effective maximum LBA.

Based on such a determination condition, it is determined whether or not each sector (requested LBA) requested to be transferred has a cache hit. Assuming that the minimum LBA as the first term = LBA7 and the maximum LBA as the third term = LBA14 as described above,
Further, as described above, the request LBA is LBA1, LBA2,
Assuming that each of LBA3 is, this LBA1,
Neither LBA2 nor LBA3 satisfies the above determination conditions. That is, no cache hit occurs (cache miss).

On the other hand, the request LBA is LBA10, LBA1
1 and LBA 12, each of them satisfies the above-described determination condition, that is, all cache hits (all hits). Further, assuming that the requested LBAs are LBA14 and LBA15, a cache hit has occurred for LBA14, but no cache hit has occurred for LBA15, that is, a partial cache hit has occurred (partial hit).

In the cache search in step F202, for example, a cache hit is determined for the sector requested to be transferred as described above. When the cache search is completed, the process proceeds from step F203 to F204, where the buffer manager 21 sets the number of hit sectors as a predetermined parameter and notifies the system controller 10 of the search completion.

Since the cache search itself is performed by the buffer manager 21, the system controller 10 waits for a search end notification after step F102, and for example, executes another process during that time. Is possible. In other words, the processing load is reduced. When the search end notification is confirmed, the process proceeds from step F103 to F104, and the number of hit sectors is confirmed. Then, based on the result of the cache search that can be confirmed from the number of hit sectors, step F1
At 05, the process branches. That is, the process branches depending on whether a cache miss, partial hit, or all hit occurs. The buffer manager 21 also branches the process in step F205 according to the result of the cache search.
That is, the process branches depending on whether a cache miss, partial hit, or all hit occurs.

FIG. 6 shows the processing of the system controller 10 and the buffer manager 21 when a cache miss occurs as a result of the cache search. In this case, all sectors requested to be transferred are read from the disk 90 and buffered in the cache memory 20.
The process of performing the transfer output in accordance with the completion of the buffering is executed.

First, at step F106, the system controller 10 performs a buffering process for the sector requested to be transferred. That is, with the start of buffering, the standard LBA as the cache management parameter, the standard LBA
Initialize the pointer, the number of valid sectors, and the number of saved sectors. Then, it controls the read operation from the disk 90 and the decode operation, and starts the buffering of the decoded data in the cache memory 20.

When the buffering of the requested sector is completed, the process proceeds from step F107 to F108, and instructs the buffer manager 21 to transfer the buffered request sector to the host computer 100. The buffer manager 21 performs transfer output of the requested sector in step F206 according to the transfer instruction,
When the transfer is completed, the process proceeds from step F207 to F208, and reports the completion of the transfer to the system controller 10.
That is, such a transfer operation is performed by the system controller 10.
This is a normal transfer operation based on the above control.

Upon receiving the transfer completion report, the system controller 10 proceeds from step F109 to F110, and determines whether or not the requested transfer output of all the sectors has been completed. For example, when the number of transfer request sectors from the host computer 100 is large, the transfer may be performed in a plurality of times. In this case, the process returns to step F107 again, and the transfer output of the remaining sectors is executed.

When the transfer output of all the requested sectors is completed, the process proceeds to step F111 to perform a termination process for the transfer request, end a series of processes when the transfer request occurs, and wait for the next transfer request. Then, when the next transfer request occurs, the processing from FIG. 5 is started again.

The above process is a process in the case of a cache miss. Examples of buffering and transfer operations in such a case will be described with reference to FIGS. FIG. 9 shows a case where the cache memory 20 is in the initial state, and the area #
No sector data is stored in 0 to # 9. At this time, the system controller 10 holds the standard LBA, the standard LBA pointer, the number of valid sectors, and the number of saved sectors as cache management parameters as initial values.

For example, in such a case, if a transfer request start address = LBA16 and length = 2 are generated as a transfer request from the host computer 100, a cache miss naturally occurs, so that the process proceeds to the process of FIG. In F106, buffering after LBA16 is performed. That is, as shown in FIG. 10, at the start of buffering, the standard LBA = LBA16,
The standard LBA pointer is set to # 0, the number of valid sectors is set to 0, and the number of stored sectors is set to 0, and the number of valid sectors is incremented in accordance with buffering execution (decoder interrupt) of each sector. In this case, the sectors requested to be transferred are LBA16, LBA
Although 17 sectors are provided, if so-called prefetch buffering is performed for a maximum of 4 sectors, as shown in the figure, up to sector LBA 21 is buffered. Therefore, when the LBA 21 is secured as the prefetch buffering, the number of effective sectors = 6.

The transfer control after step F107 can be executed when the sectors LBA16 and LBA17 are buffered. And sector L
When BA16 and LBA17 are buffered,
As described above, the transfer instruction of the LBA 16 and the LBA 17 is issued, and the transfer output to the host computer 100 is executed. When this is completed, the end process of step F118 is performed, and the process shifts to the standby state.

When a transfer request occurs, the processing of FIG. 5 is performed.
FIG. 7 illustrates a process performed when a cache hit by No. 1 results in a partial hit. In this case, some sectors requested to be transferred can be read from the cache memory 20 and transferred and output as they are (cache hit transfer). Therefore, in this example, the processing load on the system controller 10 is reduced by the buffer manager 21 automatically performing the cache hit transfer. First, as step F209 shown in FIG. 7, the buffer manager 21 executes transfer output of a sector in which a cache hit has occurred. Then, when the transfer is completed, step F2
The process proceeds from step 10 to F211 and notifies the system controller 10 that transfer of the hit sector has been completed.

On the other hand, when the system controller 10 shifts to the partial hit processing, it performs buffering processing for securing the remaining sectors that did not have a cache hit as step F112. That is, the standard LBA, the standard LBA pointer, the number of valid sectors, and the number of storage sectors are updated and set as cache management parameters at the start of buffering. And disk 9
In addition to controlling the read operation from 0 and the decode operation, the cache memory 2 stores the decoded data, that is, the sector data that did not hit the cache here.
Start buffering to zero.

While controlling the execution of buffering in this manner, the buffer manager 21
Waiting for a hit sector transfer completion report from the server, and if there is a hit sector transfer completion report, step F114
Proceed to. Then, in response to the completion of the buffering of the remaining request sectors that have not been transferred, step F114 is performed.
To F115, and the requested sector buffered to the buffer manager 21 (remaining sector)
Is transferred to the host computer 100. The buffer manager 21 responds to the transfer instruction in step F21.
In step S2, the transfer output of the requested sector is performed. When the transfer is completed, the process proceeds from step F213 to step F214 to report the transfer completion to the system controller 10.

Upon receiving the transfer completion report, the system controller 10 proceeds from step F116 to F117, and determines whether or not the requested transfer output of all sectors has been completed. Step F if any sectors have not been transferred yet
Returning to 114, the transfer processing according to the buffering is continued. If it is determined in step F117 that the transfer output of all the requested sectors has been completed, the process proceeds to step F1.
Then, the process proceeds to step S18, where a termination process for the transfer request is performed, a series of processes when the transfer request occurs, and the next transfer request is waited for.

That is, in the case of a partial hit, the hit sector in this way is
1 automatically performs the transfer output, and the system controller 10 controls the buffering and the transfer output only for the sector for which no cache hit has occurred. An example of the buffering and transfer operation in such a case will be described with reference to FIG. The cache memory 20
At the time of the storage state as shown in FIG. 10, the transfer request start address = LBA21, length =
Assume that 2 has occurred. In this case, step F2 in FIG.
When the cache search of No. 02 is performed, the required sector LBA 21 hits the cache, but the other required sector LBA 22 does not hit the cache, as can be seen from the above determination conditions.

Therefore, the buffer manager 21 automatically transfers the cache-hit sector LBA 21 to the host computer 100 as the process of step F209 in FIG. On the other hand, in the buffering process from step F112, the system controller 10 executes the buffering (including the prefetch buffering) after the LBA 22, as shown in FIG. At the start of buffering, the standard LBA = LBA22, the standard LBA pointer = # 6, the number of valid sectors = 0, the number of stored sectors = 6, and the number of valid sectors according to the buffering execution (decoder interrupt) of each sector. Is incremented. For example, when buffering up to the LBA 24 is performed, the number of effective sectors = 3.

The sector that could not be automatically transferred by the buffer manager 21 is the LBA 22. First, when the automatic transfer of the LBA 21 by the buffer manager 21 has been completed and the LBA 22 has been buffered, the transfer control in step F115 is possible. Becomes That is, at this time, a transfer instruction for the sector LBA 22 is issued, and the transfer output to the host computer 100 is executed. This LB
When the transfer of A22 is completed, the end process of step F118 is performed, and the process shifts to the standby state.

When a transfer request is generated, the buffer manager 2
The process in the case where the result of the cache search by No. 1 is all hits will be described with reference to FIG. in this case,
All sectors requested to be transferred can be read from the cache memory 20 and transferred and output as they are (cache hit transfer). Therefore, also in this case, the processing load on the system controller 10 is reduced by the buffer manager 21 automatically performing the cache hit transfer. First, as step F215 shown in FIG. 8, the buffer manager 21 executes transfer output of the sector that has hit the cache. At this time, a transfer phase process is also performed along with the transfer of the cache hit sector (ATAPI
Protocol auto configuration). This will be described later. When the transfer is completed, the process proceeds from step F216 to step F217, and the system controller 10 is notified that the transfer of the hit sector has been completed.

On the other hand, the system controller 10 does not need buffering or the like in the case of the all-hit processing.
It is sufficient to wait for the hit sector transfer completion report from the buffer manager 21 in step F119. During that time, other processing can be performed, for example, processing such as advancing prefetch buffering may be performed. Then, if there is a hit sector transfer completion report, it means that the transfer of all the requested sectors has been completed. Therefore, the process proceeds to step F120 to perform a termination process for the transfer request, and perform a series of processes when a transfer request occurs. And wait for the next transfer request.

That is, in the case of an all hit, the buffer manager 21 automatically transfers and outputs data for all sectors as described above, and the system controller 10
Need not perform buffering and transfer output control.

An example of the transfer operation in such a case will be described with reference to FIG. It is assumed that, when the cache memory 20 is in the storage state as shown in FIG. 11, a transfer request start address = LBA 23 and a length = 2 are generated from the host computer 100 as shown in FIG. In this case, when the cache search in step F202 of FIG. 5 is performed, as can be seen from the above-described determination conditions,
Both of the request sectors LBA23 and LBA24 have a cache hit.

Therefore, the buffer manager 21 automatically transfers the cache hit sectors LBA 23 and LBA 24 to the host computer 100 as the process of step F215 in FIG. Thus, the transfer according to the request from the host computer 100 is completed.

In the case of automatic transfer with all hits, it is necessary to set a transfer phase as shown in step F215. For example, when the data length requested from the host computer 100 is long, it is necessary to perform the transfer in a plurality of times. Then, the cache search in step F202 is also executed for each divided transfer. In consideration of such circumstances, if the result of the cache search is all hits, the system controller 10 terminates the command as it is (Transfer to State) or issues a search request as a divided search (Transfer to Transfer). ) Must be transmitted to the buffer manager 21 in advance. That is, if this is not known, the automatic transfer cannot be completed. Therefore, the system controller 11 sets the transfer phase as one of the search condition setting parameters in step F102, and in the case of all hits, sets the transfer to transfer or the transfer to stat.
Whether or not e is to be transmitted to the buffer manager 21 in advance.

As described above, in the present embodiment, when a data transfer request is issued from the host computer 100, the buffer manager 21 determines a cache hit, and for data that can be hit transferred, the system controller 10
The transfer output is executed without waiting for the transfer instruction. For this reason, the system controller 10 (firmware) does not need to control cache hit determination and transfer of cache hit data, and the processing load is significantly reduced. As a result, it is possible to avoid the emergence of command overhead for the system control means, thereby achieving an effect of realizing a quick data transfer output. In particular, if the prefetch buffering process is also performed by using the extra time generated by the reduction of the processing load, the probability of cache hit transfer can be increased, and more efficient transfer operation can be realized.

The cache management parameters and the search condition setting parameters are set or updated by the system controller 10 in accordance with the execution control of the buffering operation. The buffer manager 21 refers to the cache management parameters and the search condition setting parameters. By doing so, the cache hit can be determined. Therefore, it is not necessary for the buffer manager 21 to perform parameter processing for cache management, and the configuration is not complicated. Furthermore, the number of preservation sectors SCTOLD
With this setting, data buffered in the past can be effectively used for cache hit transfer.

In this example, a search format (SRCHFMT) is set as one of the search condition setting parameters set in step F102. Thereby, it is also possible to add a format condition as a search target, and it is possible to perform more flexible transfer processing.

5. Modification Example As a modification example of this example, the conditions for automatically transferring the cache hit (the conditions for determining the cache hit) are as follows.
It is also conceivable to consider the error correction result (or error detection result) by the decoder 12. That is, error correction O
It is set whether only the K (or error detection OK) data sector is to be subjected to the cache hit transfer or the error correction NG (or error detection NG) data sector is also included in the cache hit transfer. . In some cases, it may be more convenient not to stop a series of sequences (data-like sequence or processing sequence) by transferring the error sector to the host computer 100. For example, this is a case where the host computer 100 executes a transfer operation from the playback device to perform processing such as a rate check. Therefore, in such a case, if the error sector can be transferred, more flexible measures can be realized.

As a condition for the cache hit transfer, it is conceivable to consider the success or failure of mutual authentication for copyright protection. For example, in the case of DVD, there is a process called Authentication, and there is a processing system that can transfer copyright-protected data to the MPEG board only when mutual authentication between the playback device and the MPEG board is successful. Therefore, as an application of the above example, it is conceivable to determine whether or not the data sector is to be subjected to the cache hit transfer based on the information on whether or not the Authentication has been established. For example, the storage status of the cache memory 20 is a cache hit.
If the cation is not satisfied, it is not recognized as a cache hit (automatic transfer is not performed). By doing so, it is possible to deal with the copyright situation.

In the above example, the data sector having a cache hit is stored in the buffer manager 21.
Always performs automatic transfer, but the system controller 11 determines whether or not to perform such automatic transfer.
May be set in advance. That is, the automatic transfer by the buffer manager 21 as described above is executed only in the automatic transfer execution mode, and when the automatic transfer execution mode is not set, the control of the system controller 10 is performed on the data sector having a cache hit. The transfer is performed by the following.

[0080]

As described above, according to the present invention, when the cache processing means (for example, the buffer manager 21) as a hardware receives a data transfer request from an external host device, it becomes a target of the transfer request. A cache hit determination is performed to determine whether all or a part of the stored data is transferable and stored in the cache memory unit, and the transferable data is transferred to the host device without waiting for a transfer instruction from the system control unit. Execute the transfer output of The system control unit (for example, the system controller 10) receives a data transfer request from an external host device and determines whether or not a part of or all of the data requested to be transferred by the cache hit determination in the cache processing unit. When it is determined that the data cannot be transferred from the cache memory means, at least the buffering operation for the data that cannot be transferred is executed and controlled, and the data is transferred to the host device in response to the data being transferable by the buffering operation. The execution control of the transfer output is performed. For this reason, the system control means (firmware) does not need to control cache hit determination and transfer of cache hit data, and the processing load is significantly reduced. As a result, it is possible to avoid the emergence of command overhead for the system control means, thereby achieving an effect of realizing a quick data transfer output. In addition, since the processing load is reduced, the system control unit can also perform a prefetch buffering process or the like by using a standby time or the like, thereby increasing the probability of a cache hit transfer (that is, increasing the speed of the average transfer process). Higher).

The management parameter of the data storage status in the cache memory means is set or updated by the system control means in accordance with the execution control of the buffering operation, and there is a data transfer request from an external host device. At this time, the search parameter indicating the transfer request target is set by the system control means,
Since the management of the cache memory is not complicated, the consistency with the old system can be improved, and the cache processing unit can determine the cache hit by referring to the management parameter and the search parameter. In addition, there is no need for the cache processing means to perform parameter management, and the configuration does not become complicated. In addition, if the management parameters include a parameter that can determine the data that is valid at the time point referred to by the cache processing unit among the data stored in the cache memory unit, the past The buffered data can also be used effectively for cache hit transfer.

Further, the cache processing means can add a data format type, an error state at the time of decoding, information for copyright protection, and the like as a determination condition when determining a cache hit. A system capable of performing a flexible transfer operation according to various circumstances can be constructed. Further, the cache processing means determines that all of the data requested to be transferred can be transferred by the cache hit determination, and can determine the transfer protocol when executing the transfer output to the host device. By doing so, processing can be completed with good consistency with the system control means.

[Brief description of the drawings]

FIG. 1 is a block diagram of a playback device according to an embodiment of the present invention.

FIG. 2 is an explanatory diagram of cache processing parameters according to the embodiment;

FIG. 3 is an explanatory diagram of search condition setting parameters according to the embodiment;

FIG. 4 is an explanatory diagram of a cache memory management mode according to the embodiment;

FIG. 5 is a flowchart of a process when a transfer request occurs according to the embodiment;

FIG. 6 is a flowchart of a cache miss process according to the embodiment;

FIG. 7 is a flowchart of a partial hit process according to the embodiment.

FIG. 8 is a flowchart of an all-hit process according to the embodiment.

FIG. 9 is an explanatory diagram of an initial state of the cache memory according to the embodiment;

FIG. 10 is an explanatory diagram of a buffering operation according to the embodiment.

FIG. 11 is an explanatory diagram of a buffering operation according to the embodiment.

FIG. 12 is an explanatory diagram of a case where the buffering operation according to the embodiment becomes unnecessary.

[Explanation of symbols]

1 pickup, 2 objective lens, 2 biaxial mechanism, 4
Laser diode, 5 photo detector, 6 spindle motor, 8 thread mechanism, 9 RF amplifier, 1
0 system controller, 13 interface unit, 14 servo processor, 20 cache memory, 21 buffer manager, 90 disk, 10
0 Host computer

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Tadashi Nakamura 6-7-35 Kita-Shinagawa, Shinagawa-ku, Tokyo Inside Sony Corporation (72) Inventor Taji Tsukada 6-35, Kita-Shinagawa, Shinagawa-ku, Tokyo No. Sony Corporation

Claims (7)

[Claims] A reading means for reading data from a recording medium and performing a required decoding process; a cache memory means for storing data decoded by the reading means as a buffering operation; When a data transfer request is received from the host device, a cache hit determination is performed as to whether or not all or a part of the data to be transferred is stored in the cache memory means and is transferable, For transferable data, there is a cache processing means capable of executing transfer output to the host device without waiting for a transfer instruction, and a data transfer request from an external host device, and a cache hit in the cache processing means. As a result of the determination, a part or all of the data requested to be transferred is cached. When it is determined that transfer is not possible from the memory means, at least the execution of the buffering operation for the non-transferable data is controlled, and in accordance with the transfer being enabled by the buffering operation,
And a system control unit capable of controlling execution of transfer of the data to the host device. 2. The system according to claim 1, wherein said system control means sets or updates a data storage status management parameter in said cache memory means in accordance with execution control of said buffering operation. When there is, the system control unit sets a search parameter indicating the transfer request target, and the cache processing unit performs the cache hit determination by referring to the management parameter and the search parameter. The playback apparatus according to claim 1, wherein the playback is performed. 3. The management parameter includes a parameter capable of discriminating, among the data stored in the cache memory means, data that is valid at the time of reference by the cache processing means. The playback device according to claim 2, wherein: 4. The reproducing apparatus according to claim 1, wherein the cache processing means can add a data format type as one of the determination conditions at the time of the cache hit determination. 5. The reproducing apparatus according to claim 1, wherein the cache processing means can add an error condition at the time of decoding as one of the determination conditions at the time of the cache hit determination. 6. The reproducing apparatus according to claim 1, wherein the cache processing means can add information for copyright protection as one of the determination conditions at the time of the cache hit determination. 7. The cache processing means determines from the cache hit determination that all data requested to be transferred can be transferred, and executes a transfer protocol when executing transfer output to the host device. The reproducing apparatus according to claim 1, wherein the reproducing apparatus is configured to be able to determine.