JPH11297839A - Wiring device between blocks - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable even a first wiring to be laid as proximately as an after wiring, by a method wherein a degree of wiring congestion is taken into consideration. SOLUTION: Data on an arrangement of blocks are inputted (S1), and the upside of a chip is divided to virtual regions (S2). One of nets is selected (S2), all nets contained in the arrangement data are processed, and virtual wirings are laid to connect blocks together (S5). A degree of wiring congestion is calculated for each region by obtaining the probability of the passage of a virtual wiring through each region (S6). Then, a unit wiring capacity is calculated for each region taking a degree of wiring congestion into consideration (S7), and this is used for an isodelay wiring CTS (S8).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an inter-block wiring apparatus, and more particularly to an inter-block wiring apparatus suitable for a clock tree synthesis for wiring to a flip-flop of a function block disposed in a chip for distributing clocks at equal delay times. It relates to a wiring device.

[0002]

2. Description of the Related Art To ensure synchronization, clocks must be distributed from the root of a clock tree to each flip-flop with an equal delay time. Therefore, the wiring in the clock tree synthesis has conventionally been given priority over other signal wiring, and the delay from the root of the clock tree to each flip-flop in a state where no other signal wiring is performed. In order to reduce the difference in clock skew, the delay is calculated and the wiring length is controlled.

In general, as shown in FIG. 6, when other wirings 2 to 5 are formed around an actual wiring 1, the capacitance between the wiring 1 and the wirings 2 to 5 is reduced. The capacity is added and calculated. Therefore, when only the wiring 1 exists, it is difficult to correctly calculate the wiring capacitance of the wiring 1.

[0004] For this reason, the influence of the clock wiring due to the subsequent wiring of other signals is compensated for by isolating the other signal wiring from the clock wiring, providing shield wiring, or using a delay buffer. Or to reduce it.

In the timing-driven automatic placement processing for determining the placement position in consideration of the inter-block delay while performing the delay calculation, virtual wiring processing is performed in the process of obtaining a delay value between blocks. Also in this virtual wiring processing, a virtual wiring path is obtained in a state where wiring of other signals is not performed, and a delay value is calculated based on the virtual wiring path.

Further, Japanese Patent Application Laid-Open Nos. 2-87278 and 8-110915 disclose techniques for improving the accuracy of delay time calculation by considering the influence of other signal wiring. The technique described in Japanese Patent Application Laid-Open No. H8-110915 discloses a technique for solving the problem of the technique described in Japanese Patent Application Laid-Open No. 2-87278. Calculate the representative capacitance value of the wiring board based on the adjacent rate and the crossing rate, which are frequently calculated among the crossing rates, and determine the delay time for all the wirings included in the wiring board based on the representative capacitance value. "
(0062) A delay time calculation device is disclosed.

[0007]

However, of the above-mentioned prior arts, in which shield wiring or the like is performed after other signal wiring, there is a problem that high integration is hindered and complicated processing is required. .

Further, in the technology described in Japanese Patent Application Laid-Open No. 2-87278, it is difficult to say that the influence of the adjacent wiring is sufficiently considered because the virtual wiring is insufficient. Further, in the technique described in Japanese Patent Application Laid-Open No. H8-110915, after automatic wiring is performed, the delay time is verified using the capacitance obtained in consideration of the actual congestion degree of the wiring, so that clock tree synthesis is performed. It is not useful for the first wiring, like the wiring in the above.

An object of the present invention is to provide an inter-block wiring apparatus which can perform wiring similar to wiring after other wiring has been performed by taking into account the degree of wiring congestion even in the first wiring. It is in.

[0010]

According to the present invention, there is provided an inter-block wiring apparatus comprising: a wiring congestion degree calculating means for calculating a wiring congestion degree of each part in a chip based on arrangement data of function blocks arranged on the same chip; A wiring capacitance value calculating unit that calculates a unit wiring capacitance value for each of the parts based on the wiring congestion degree; a delay time calculating unit that calculates a delay time of each of the parts using the unit wiring capacitance value; And wiring means for performing wiring between the function blocks by using

In the inter-block wiring apparatus according to a preferred embodiment of the present invention, the wiring congestion degree calculating means includes: chip dividing means for dividing the chip into a virtual area by the placement data; Connected 2
Virtual wiring means for assuming all routes in which the region is a unit of passage for each of the three function blocks to obtain virtual wiring; passing probability calculating means for obtaining the passing probability of the virtual wiring for each of the regions; And congestion degree calculating means for calculating a wiring congestion degree based on the number of virtual wirings and the passage probability.

In the inter-block wiring apparatus according to a preferred embodiment of the present invention, the passing probability is a reciprocal of the number of all virtual wirings between two function blocks.
The wiring means is a clock tree synthesis means for performing wiring for distributing to the flip-flops in each of the function blocks with equal delay time using the delay time.

In the inter-block wiring apparatus according to a preferred embodiment of the present invention, the wiring means is used in a timing-driven automatic placement process for determining a placement position in consideration of a delay between blocks while calculating a delay. It is a wiring processing means for virtual wiring.

[0014]

Next, embodiments of the present invention will be described.

An embodiment of the present invention comprises a wiring congestion degree calculating means for calculating the wiring congestion degree of each part in a chip based on the arrangement data of the function blocks arranged on the same chip; A wiring capacitance value calculating unit that calculates a unit wiring capacitance value for each part; a delay time calculating unit that calculates a delay time of each of the parts using the unit wiring capacitance value; Wiring means for performing the above wiring.

In a circuit operating in synchronization with a clock, it is ideal to supply a clock with zero skew to flip-flops scattered from the root of the clock tree to each part of the circuit. For this reason, wiring in clock tree synthesis (hereinafter, referred to as CTS) has priority over wiring for other signals and is performed in a state where wiring for other signals is not performed. However, after wiring for other signals is performed, wiring for supplying a clock is affected by wiring for other signals. The present invention is intended to realize a CTS that takes into account the influence of a fine virtual wiring for other signal wirings.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a flowchart showing a processing procedure in an apparatus for performing CTS, which is one embodiment of the inter-block wiring apparatus of the present invention.

First, layout data for which layout processing such as automatic layout has been completed is input (S1). Here, the arrangement data refers to an arrangement position of each function block (hereinafter, referred to as a block) arranged on the same chip.

Next, the chip is divided into several virtual areas (S2). FIG. 2A shows a chip divided into 25 square areas A. In S3, one of the nets is selected from the placement data. The net is information indicating which block is connected to which block among the blocks included in the arrangement data. Then, virtual wiring is performed until all nets have been processed (S4) (S4).
5). The virtual wiring is, for example, as shown in FIG. 3, a path in which an area conceivable when connecting the block S and the block T is a unit of passage. In FIG. 3, there are six routes (A) to (F), that is, virtual wiring.

Next, the congestion degree is calculated by obtaining the passage probability of the virtual wiring in each area (S6). In this example, the passage probability is the reciprocal of the number of the virtual wiring. Therefore, with respect to the virtual wiring in FIG. 3, the passage probability of each region is a value obtained by multiplying 1/6 by the frequency of the virtual wiring passing through that region, as shown in FIG. Since the wiring passage probability can be considered to be higher in a portion where the wiring congestion degree is higher,
The wiring passage probability is set as the wiring congestion degree. FIG. 2 (B)
FIG. 2C and FIG. 2C show areas where wiring is sparse and wiring is dense when wiring is actually performed.

It should be noted that a net composed of three or more terminals may be divided into two-terminal nets and determined by the above-described method.

Next, the unit wiring capacitance C _area of each area is calculated by the following equation in consideration of the wiring congestion degree K _area (S
7).

C _area = a × C _p × K _area + C _b where a is a constant used when converting the wiring congestion degree K _area into unit wiring capacitance, and C _p and C _b are constants determined by the process. . FIG. 5 shows that one net connecting block 1, block 2 and block 3 is a region A22,
A23, A24, A25, A34, A44 and A54
Shows a state formed by passing through the slab. Each unit wiring capacitance of each of these regions is obtained by the above equation,
C22, C23, C24, C25, C34, C respectively
44 and C54. Therefore, the wiring capacity of this net is obtained by multiplying the area of the wiring portion passing through each area by the unit wiring capacity of each area, obtaining the wiring capacity of each area, and adding them. Can be calculated.

Next, by performing a delay time using the unit wiring capacitance C _area of each area obtained as described above,
The equal delay wiring CTS is performed (S8). As a typical delay time calculation method, for example, an Elmore model is known. The Elmore model is based on Elmore (WCE
lmore: The Transistor Resp
once of Dumped Linear Net
work withPartical Regal
d to Wireband Amplifire. :
Journal of Applied Physic
s, Vol. 19 (1948), p. 53-63). In the π-type model as shown in FIG. 7, the wiring resistance for a wiring having a unit length and a unit width is r, and the wiring capacitance is c.
Then, the delay time t in the wiring of length l and width w is

[0025]

(Equation 1)

## EQU1 ## Note that _CL is a load capacitance for the wiring.

A specific method of executing the CTS is as follows. Now, a case where a two-stage clock tree is generated will be described with reference to FIG.

First, as shown in FIG. 8A, chips are divided into four groups so that flip-flops arranged near each other are included in the same group. Then, the two flip-flops in the same group and the wiring, at a point on the wiring delay time T _1, T ₂ to each flip-flop find point P ₁ such that the same (Figure 8
(B)). For other flip-flops, in the same way, find the point P ₂ (with the wiring Figure 8 (C) .P ₁ and P _2, a point on its wiring, the delay time until the four flip-flops A point P ₃ where T ₅ and T ₆ are the same.
The Locate (Fig 8 (D)), to connect the buffer to the point P ₃ (FIG. 8 (E)). By operating the above-described procedure for the other flip-flops 4, a two-stage clock tree is completed as shown in FIG. In this clock tree, it is understood that the delay time from the root to each flip-flop becomes equal by the above-described procedure.

FIG. 9 is a flowchart showing a processing procedure in another embodiment of the present invention in which the present invention is applied to timing-driven automatic wiring processing for obtaining placement data.
In FIG. 9, first, a netlist, which is information connecting blocks, is input (S11), and an initial block arrangement process is performed (S12). Next, S2 to S6 in FIG.
Is calculated (S13), and a wiring capacitance value corresponding to S7 in FIG. 1 is calculated (S14). Then, the layout is improved from the initial layout in consideration of the delay time until a predetermined limit is reached (S15, S16).

Further, the processing shown in FIG. 1 or FIG. 9 can be programmed, the program can be recorded on a recording medium, and the program can be read and executed by a computer as shown in FIG.

[0031]

According to the present invention, at the time of wiring, the unit wiring capacity for each area can be set according to the wiring congestion degree of other signals. Can be performed in consideration of the increase in the delay time. In particular, it is effective to reduce clock skew in CTS.

[Brief description of the drawings]

FIG. 1 is a flowchart illustrating a processing procedure according to an embodiment of the present invention.

FIG. 2 is a diagram showing a concept of a region and a state of sparse and dense wiring in the present invention.

FIG. 3 is a diagram illustrating a virtual wiring according to the present invention;

FIG. 4 is a diagram showing a passage probability of each region of the virtual wiring shown in FIG. 3;

FIG. 5 is a diagram showing unit wiring capacities for each region according to the passage probability of FIG. 4;

FIG. 6 is a general diagram for explaining capacitance between wirings.

FIG. 7 is a general equivalent circuit diagram for obtaining a wiring delay time.

FIG. 8 is a diagram for explaining a general CTS.

FIG. 9 is a flowchart showing a processing procedure in another embodiment of the present invention.

FIG. 10 is a diagram showing a state in which a computer recording a processing procedure in the present invention is read from a recording medium by a computer.

[Explanation of symbols]

 A area B block

Claims (9)

[Claims] 1. A wiring congestion degree calculating means for calculating a wiring congestion degree of each part in a chip based on arrangement data of a function block arranged on the same chip, and a unit wiring capacitance for each part based on the wiring congestion degree. A wiring capacitance value calculating means for calculating a value, a delay time calculating means for calculating a delay time of each portion using the unit wiring capacitance value, and a wiring means for wiring between the function blocks using the delay time And a wiring device between blocks. 2. The wiring congestion degree calculating means includes: chip dividing means for dividing the chip into a virtual area by the placement data; and dividing the area for each of two function blocks connected by the placement data. Virtual wiring means for obtaining virtual wiring by assuming all routes as passing units; passing probability calculating means for obtaining the passing probability of the virtual wiring for each area; and the number and passing probability of the virtual wiring for each area 2. The inter-block wiring device according to claim 1, further comprising a congestion degree calculating means for calculating a wiring congestion degree by the following. 3. The method according to claim 2, wherein the passage probability is a value obtained by multiplying the reciprocal of the number of virtual wires between two function blocks by the frequency of virtual wires passing through the region. Wiring device between blocks. 4. The clock tree synthesizing means for performing wiring for distributing to the flip-flops in each of the function blocks with equal delay time using the delay time. The inter-block wiring device according to any one of claims 1 to 3. 5. The wiring means according to claim 1, wherein said wiring means is a wiring processing means for virtual wiring used in automatic placement processing for determining a placement position in consideration of inter-block delay while performing delay calculation. The inter-block wiring device according to claim 1. 6. A process of calculating a wiring congestion degree of each part in a chip based on the placement data of a function block disposed on the same chip, and calculating a unit wiring capacitance value of each part based on the wiring congestion degree. A program for causing a computer to execute a process, a process of calculating a delay time of each portion using the unit wiring capacitance value, and a process of performing wiring between the function blocks using the delay time is recorded. A program readable recording medium. 7. The calculation of the wiring congestion degree includes a process of dividing the chip into a virtual area based on the placement data;
A process of obtaining virtual wiring by assuming all paths using the region as a unit of passage for each of the two function blocks connected by the placement data; and a process of obtaining a passing probability of the virtual wiring for each of the regions.
7. The recording medium according to claim 6, further comprising: a process of calculating a wiring congestion degree for each of the regions based on the number of the virtual wirings and the passage probability. 8. The system according to claim 7, wherein the passage probability is a value obtained by multiplying the reciprocal of the number of virtual wires between two function blocks by the frequency of virtual wires passing through the region. recoding media. 9. A process for performing wiring for distributing clocks for distributing to flip-flops in each of the function blocks with equal delay time using the delay time.
9. The recording medium according to claim 6, wherein the recording medium is a tree synthesis process.