JPH11297848A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

(57) [Summary] [PROBLEMS] In a conventional manufacturing method in which a plurality of types of gate oxide film thicknesses are formed by a single effective gate oxidation, the work function and sheet resistance of the gate electrode fluctuate greatly. A plurality of types of transistors having different characteristics depending on the thickness of a gate insulating film are provided. The thickness of the gate insulating film 6 is set to a constant value among the plurality of types of transistors, and the polycrystalline gate electrodes 22a (for example, made of a high melting point metal silicide) on the gate insulating film 6 are formed.
The grain size of 22b is changed according to the type of transistor. Specifically, for example, before the crystallization heat treatment, at least one of the type and the amount of impurities to be introduced into the film to be the gate electrodes 22a and 22b is changed,
The thicknesses of the films a and 22b are locally changed by, for example, selective etching.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a method of forming two or more effective gate oxide films in one gate oxidation (one type of gate oxide film). And a method of manufacturing the same.

[0002]

2. Description of the Related Art As the scale of integration of LSIs increases,
With only the combination of the conventional processor and the memory, L
Software development is beginning to become a bottleneck for shortening the SI development period. For this reason, there has been an increasing demand for incorporating application-specific LSIs (ASICs) into LSI chips in advance. Also, this ASIC cannot be separated from a system using the ASIC with an increase in integration scale, and has recently been developed into what is called a system LSI. Devices integrated in such a system LSI include not only processors and DRAMs but also non-volatile memories and various interface circuits.

[0003] However, the complexity of the wafer process for integrating various devices into one chip is rapidly increasing. For example, in the conventional LSI, one type of film thickness is often used in the conventional LSI, whereas in the system LSI, one type of gate oxide film is used as the number of devices increases. It is unlikely that multi-oxide (Multi-O
xide) Processes are becoming more common. This is because even if the design rules are the same, the required characteristics differ depending on the device. For example, in a logic circuit, the driving capability (operation speed and the like) of a transistor is required, so that the gate oxide film must be relatively thin. In contrast, in memories such as DRAM,
For example, a voltage higher than the external power supply voltage may be used due to internal boosting from the viewpoint of operation speed improvement, and a relatively thick gate oxide film is used from the viewpoint of ensuring a withstand voltage accompanying this or to improve retention characteristics. Can be Also, in many LSIs including other memories, in the case of a multi-power supply LSI in which the power supply voltage is dropped or boosted internally, the gate oxide film thickness of the interface circuit or the high voltage portion is relatively increased due to a problem with dielectric strength. May be thicker.

When such a multi-oxide process is used, a gate oxide film is usually formed twice (by additional oxidation) in a portion where a thick gate oxide film is formed. On the other hand, in a portion where a thin gate oxide film is formed, an oxide film grown in a subsequent oxidation step is used as a gate oxide film. Therefore,
In the portion where the thin gate oxide film is formed, it is necessary to selectively remove the oxide film after the first oxidation step using a resist mask process.

As described above, the conventional method requires a resist mask process corresponding to the type of the gate oxide film thickness. However, in this resist mask process, ashing is required for resist removal after the substrate region where the transistor is formed is exposed, particularly in a portion where a thin gate oxide film is formed, and thus there is a problem of substrate contamination. In addition, resist coating and ashing must be performed while the gate oxide film is exposed, and the problem of contamination of the gate oxide film from the resist and introduction of damage cannot be ignored.

On the other hand, Japanese Patent Application Laid-Open No. Hei 3-94464 proposes a semiconductor device in which the impurity concentration of a polycrystalline silicon (PolySi) gate electrode is changed to change the effective gate capacitance. . FIG.
10A is a cross-sectional view showing regions having different gate oxide film thicknesses, and FIG. 10B shows various parameters described in the above-mentioned publication. In FIG. 10, a chip portion where a thin gate oxide film is originally required is defined as a region A, and a portion where a thick gate oxide film is originally required is defined as a region B. Further, reference numeral 100 in the figure denotes a semiconductor substrate, and 102 denotes LOCO.
S, 104a, 104b are gate oxide films, 106a, 1
06b is a gate electrode made of polysilicon, 108 is an interlayer insulating film, 110 is a connection plug, and 112 is a wiring layer.

In this semiconductor device, as shown in FIG. 10B, the impurity concentration in the polysilicon between the regions A and B is changed by using the resist mask process twice. For this reason, the completed effective gate oxide film thickness can be realized with different values between the regions A and B. here,
The “effective gate oxide film thickness” is the thickness of a region where there is no charge that determines the gate capacitance, and a predetermined potential is added to the physical gate oxide film thickness and the polysilicon layer portion in contact with the gate oxide film thickness. This is the sum of the thickness of the depletion layer formed at the time of application.

By using the technique of changing the impurity concentration in the polysilicon of the gate electrode, a plurality of types of gate oxide thicknesses can be effectively formed by one gate oxidation (one type of physical gate oxide thickness). Can be formed.

[0009]

However, Japanese Patent Application Laid-Open No.
The method disclosed in Japanese Patent Application Laid-Open No. 9-94464 has a problem that the work function and sheet resistance of the completed gate electrode are also changed at the same time. In particular, in order to provide an effective difference in the effective gate oxide film thickness, it is necessary to considerably lower the impurity concentration in the polysilicon of one region (region B). The rise is fatal. In this regard, “IEEETRANSACTION
As shown in ON ELECTRON DEVICES, VOL.ED-32, NO.3, 1985, p620 ", when the impurity concentration falls below the order of 10 ¹⁹ cm ^-3 , for example, the sheet resistance exponentially decreases with decreasing impurity concentration. It is known that the increase in the sheet resistance affects the operation speed of the element without arranging the gate electrode wiring, so that the degree of freedom in device and circuit design is lost. Also, especially on the low-concentration polysilicon side, the work function and sheet resistance of the gate electrode are greatly affected by the gate bias and temperature, and this is taken into consideration when designing devices and circuits. Therefore, this method of changing the impurity concentration in polysilicon requires a fundamental re-design from the device and circuit design, and as a result, the conventional design assets are reduced. You will not be able to use it.

[0010] In view of the above background, there is a need for a method of forming an insulated gate transistor that can locally control only the gate capacitance without largely changing the work function of the gate electrode and the completed sheet resistance.

The present invention has been made in view of such circumstances, and has a plurality of types of effectively completed gate oxide film thicknesses while performing gate oxidation only once (one type of gate oxide film thickness). It is an object of the present invention to realize a semiconductor device without a large change in work function or sheet resistance of a gate electrode.

[0012]

In order to solve the above-mentioned problems of the prior art and to achieve the above object, the present inventor has proposed:
As a result of various studies, it has been experimentally found that in a silicide single-layer gate electrode such as WSix, as the grain size of the resulting silicide grows, the effective finished gate oxide film thickness increases. . This is considered to be due to the fact that the capacitive material condenses on the grain boundary.

The present invention utilizes such properties of the polycrystalline gate electrode material. A semiconductor device according to the present invention is a semiconductor device having a plurality of types of transistors having a difference in characteristics depending on a thickness of a gate insulating film, and the thickness of the gate insulating film is different between the plurality of types of transistors. The grain size of the polycrystalline gate electrode (which is made of, for example, high-melting-point metal silicide) on the gate insulating film is set to a constant value and is changed according to the type of transistor.

Further, a method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device having a plurality of types of transistors having characteristics different depending on a gate insulating film thickness. A gate insulating film of a transistor is formed at one time in a single film formation process on a semiconductor substrate surface, and a polycrystalline gate electrode is formed over the gate insulating film by changing the size of Glen according to the type of the transistor.

There are the following two methods for locally changing the grain size. (1) For example, before heat treatment after forming a film to be a polycrystalline gate electrode, the impurity is introduced into the polycrystalline gate electrode by changing at least one of the type and amount of the impurity according to the type of the transistor. I do. (2) For example, after forming a film to be a polycrystalline gate electrode, the film is locally thinned by etching or the like to a film thickness corresponding to the type of the transistor.

In the method of manufacturing a semiconductor device according to the present invention, an oxidation step for forming a gate oxide film is performed only once.
Moreover, the substrate is not exposed when the photoresist is formed. By a process capable of avoiding the substrate contamination and the like, the completed effective gate oxide film thickness can be set to different values in the same wafer by changing the grain size of silicide or the like. For this reason, although there is a difference in the sheet resistance of the gate electrode corresponding to the thickness and the grain size of the silicide, see Japanese Patent Application Laid-Open No. 3-94464.
The sheet resistance does not change by orders of magnitude as in the method disclosed in Japanese Patent Application Laid-Open Publication No. H10-260,036. Further, silicide doped with impurities is a metal in material, and its sheet resistance and temperature characteristics of work function are relatively small. For the above reasons, when applying the method of manufacturing a semiconductor device according to the present invention, it is only necessary to change the process without changing already designed devices or circuit specifications.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS As described above, the present inventor has found through experiments that the effective finished gate oxide film thickness increases as the grain size grows larger in a silicide single-layer gate electrode. Was. Since the present invention has been devised based on the results of the experiment, the following briefly describes the results of the experiment, and then describes an embodiment of a semiconductor device and a method of manufacturing the same according to the present invention with reference to the drawings. This will be described in detail with reference to FIG.

FIG. 8 is a graph showing the result of CV measurement in which a change in gate capacitance according to the type of impurity ions was examined. FIG. 9 is a graph showing the relationship between the effective gate oxide film thickness and the ion dose obtained by calculation from the measured gate capacitance value. In this experiment, the dose of WSix to the film was fixed at 5 × 10 ¹⁵ cm ⁻² and Pho
A sample which was ion-implanted while changing the kind of impurities such as s, As, Sb, and B, and then annealed under predetermined conditions was used as an evaluation target.

As shown in FIG. 8, the value of the gate capacitance Cg differs depending on the type of the doped impurity (Phos, As, Sb, B, etc.), especially on the positive gate bias side. This is because the crystallization speed in the above-mentioned annealing is different in the silicide films of the respective samples, and the grain size is different. It is considered that the reason why the gate capacitance Cg changes due to the difference in the grain size is that the capacitive material is condensed on the grain boundary portion. By using the gate capacitance value at the time of a predetermined gate bias, an effective gate oxide film thickness Tox.eff can be obtained by calculation. This effective gate oxide film thickness Tox.eff depends on the dose of impurity ions, as shown in FIG.
You can see the difference widens. This is consistent with the observation that the larger the dose, the larger the grain size. It is generally known that the grain size of a polycrystalline material is such that the larger the film thickness, the larger the final crystal grain size.

As described above, in the gate electrode of a single layer of silicide, by controlling the grain size of the resulting silicide, a plurality of types of transistors having different effective gate oxide thicknesses are manufactured even with the same oxide thickness. It turned out to be possible. And
It has been found that the grain size of the resulting silicide can be changed by changing the type and dose of the impurity introduced into the silicide, or by locally changing the thickness of the silicide.

For example, in the case of WSix, by doping As or Phos at a concentration of up to 5 × 10 ²⁰ cm ⁻³ , the work function is increased by about 0.3 V from the center of the silicon band gap to n ⁺ PolySi in any case. It is possible to shift to the side. In the case of As doping, the finished grain size is larger than that of Phos doping, and the effective gate oxide film thickness Tox.eff increases. In other words, in the combination of As and Phos, two types of transistors differing only in the effective gate oxide film thickness Tox.eff completed while shifting the work function by the same direction and amount and making the sheet resistance almost the same. it can. Also, a p-type impurity and an n-type impurity, for example, B and As
In this combination, although the shift direction of the work function is different and causes a difference, the difference in the effective gate oxide film thickness Tox.eff can be made larger. On the other hand, if the WSix film thickness is locally changed by the resist mask process, the finished grain size of WSix changes greatly depending on the film thickness even with the same heat treatment. Although this method alone can locally change the effective gate oxide film thickness Tox.eff, a larger Tox. eff difference can be realized.

Hereinafter, more specific embodiments of the present invention will be described.
The formation of a gate electrode of a MOS type semiconductor device will be described as an example.

First Embodiment In the present embodiment, the type and dose of impurities are changed. FIG. 1 is a sectional view of a main part of a MOS type semiconductor device according to the present embodiment. In FIG. 1, reference numeral 1 denotes a MOS semiconductor device, 2 denotes a silicon substrate, 4 denotes an element isolation region such as LOCOS, 6 denotes a gate oxide film, 8a and 8b denote gate electrodes made of WSix, and 10 denotes an interlayer insulating film. In FIG. 1, a chip region A where the effective gate oxide film thickness Tox.eff is to be reduced is shown on the left side, and a chip region B where the Tox.eff is desired to be thicker is shown on the right side.

In this embodiment, a gate oxide film 6 formed on a silicon substrate 2 serving as a bulk is, for example, WS
The gate electrodes 8a and 8b of ix are formed.
The thickness of the gate oxide film 6 is, for example, about 5 nm, and the thickness of the gate electrodes 8a, 8b is, for example, about 100 nm.
The ph is applied to the gate electrode 8a in one region A.
os is, for example, a concentration of ５5 × 10 ²⁰ cm ⁻³ , and As is formed on the gate electrode 8b in the other region B, for example,
Each is doped at a concentration of 1 × 10 ²¹ cm ⁻³ . In this example, by changing the type and concentration of the n-type impurity in WSix in this manner, for example, the maximum grain size after the heat treatment at a maximum heat treatment temperature of 850 ° C. for about 30 minutes is shown in FIG. The area B is sufficiently larger than the area A. As a result, the resulting effective gate oxide film thickness Tox.eff (calculated value) is provided with a difference of up to 6 nm on the region A side and up to 8 nm on the region B side. In the case of this example, the work function of WSix is n ⁺ S from the center of the silicon band gap regardless of which impurity is used.
The position is shifted by 0.3 V to the i side.

In the semiconductor device 1 of this embodiment as described above, while keeping the physical oxide film thickness immediately after film formation (As Grown) constant,
In other words, by changing the type and / or concentration of the impurity introduced into WSix by one-time gate oxidation, the effective gate oxide film thickness is locally changed.

Although phos and As are used as different types of impurities in the example of FIG. 1, the type of impurities is not limited in this embodiment. For example, boron (B) can be used as an impurity that inhibits grain growth. At this time, the work function of WSix shifts by about 0.3 V from the center of the band gap of silicon to the p ⁺ Si side. Therefore, although the work function is different from that of WSix doped with other n-type impurities, the completed effective gate oxide film thickness Tox.eff becomes close to that immediately after film formation to about 5.5 nm, which is larger. To
There is an advantage that x.eff difference can be obtained. In any case, basically, as the impurity dose is increased, the growth of the resulting grains can be promoted or suppressed. Other configurations are not limited to the above description. A semiconductor device to which the present invention can be applied may be any MIS semiconductor device that is insulated from a substrate by a gate insulating film (not limited to an oxide film). The substrate may be such as SOI, and the gate electrode may be a general polycrystalline silicide or metal such as MoSix, TaSix, Mo,
W, Ta or the like may be used. Other polysilicon may be used as the polycrystalline material. Further, the types and concentrations of impurities to be introduced are only examples.

Next, a method of manufacturing the semiconductor device having the above-described configuration will be described with reference to the drawings. 2 to 5 are cross-sectional views showing respective manufacturing steps of the present manufacturing method.

First, in FIG. 2A, an element isolation region 4 is formed on the prepared silicon substrate 2 by the LOCOS method or the like. Next, in FIG. 2B, the gate oxide film 6 is
Immediately after film formation, it is grown by thermal oxidation or the like so as to have a thickness of, for example, 6 nm. On the gate oxide film 6, a WSix film 8 is deposited to a thickness of, for example, about 100 nm by, for example, a CVD method.
The deposition conditions of WSix at this time are, for example, as follows.

[Deposition conditions of WSix] Cold Wall type LP-CVD apparatus, pressure: 133 Pa, susceptor temperature: 595 ° C., introduced gas: SiH ₂ Cl ₂ / WF ₆ = 100 / 1.8 s
ccm.

In FIG. 3C, on the WSix film 8,
A resist pattern 9 opening in the region A is formed. Then, Phos ⁺ is doped into the entire surface by ion implantation.
This ion implantation condition is, for example, an acceleration voltage: 25 Ke.
V, dose amount: 5 × 10 ¹⁵ cm ⁻² . This allows
Through the opening 9a of the resist pattern 9, the W
Phos is introduced only into the Six film portion.

Subsequently, as shown in FIG. 3D, a resist pattern 11 different from the previously formed resist pattern 11 is formed on the WSix film 8.
Is formed, and As ⁺ is doped by ion implantation only into the WSix film portion of the region B through the opening 11b. The ion implantation conditions at this time are, for example, acceleration voltage: 50 K
The eV and the dose amount are set to 1 × 10 ¹⁶ cm ⁻² .

As shown in FIG. 4E, a photoresist 13 for obtaining a gate electrode pattern is formed on the WSix film 8 doped with different impurities in this manner, as shown in FIG. W using resist 13 as a mask
The Six film 8 and the gate oxide film 6 are etched by, for example, a method such as RIE. After removing the photoresist 13 and forming an LDD region and a high-concentration impurity region (not shown), an interlayer insulating film is deposited. The formation of these impurity regions is performed in the same manner as in a normal MOS transistor manufacturing process. That is, the formation of the LDD region is performed after the formation of the gate electrode, and the formation of the high-concentration impurity diffusion region is performed after the formation of the sidewall insulating layer.
Using a gate electrode pattern or LOCOS (and a sidewall insulating layer) as a self-alignment mask, and using a resist mask to protect one of the nMOS and the pMOS, different impurities are separately applied.

Next, a heat treatment for activating the impurities is performed.
For example, it is performed under the following conditions. As a result, as shown in detail in FIG. 1, the grain size is small in the gate electrode 8a on the region A side and large in the gate electrode 8b on the region B side.

[Heat treatment conditions]; electric furnace annealing, 850 ° C. for 30 minutes in N ₂ atmosphere.

Thereafter, as shown in FIG.
Similar to the S transistor fabrication process, the connection plug 12
(Formation of contact holes and embedding of metal) and formation of wirings 14 are sequentially performed to form the semiconductor device 1.
To complete.

In the manufacturing method of this embodiment, the gate oxide film is formed only once (FIG. 2B), and is immediately covered with the WSi film 8. Until the patterning is performed in FIG. 4F, the gate oxide film 6 and the substrate surface are never exposed. As a result, the gate oxide film 6 and the substrate surface are not contaminated or damaged by organic matter. The present manufacturing method is not only a highly reliable gate formation process as described above, but also has an advantage that the effective gate oxide film thickness can be easily changed by selectively implanting impurities.

It should be noted that the above-described method of forming each part is merely an example, and the method and conditions are not limited. For example, WSi
As the film forming method of x, a physical film forming method such as a vapor deposition method and a sputtering method can be adopted in addition to the CVD method. In any of the film forming methods, a layered film of, for example, polysilicon and a high melting point metal may be formed instead of WSix, and this may be reacted at the time of heating to be changed to a WSix single layer film. In addition, co-evaporation and co-supattment (metal-silicon are supplied from separate sources)
ering) and various methods such as a sputtering method using a silicide target formed by hot pressing.

Second Embodiment This embodiment is directed to a case where the thickness of a polycrystalline gate electrode is locally changed to change the grain size at the time of completion. FIG. 6 is a sectional view of a principal part of the MOS semiconductor device according to the present embodiment. FIG. 7 is a cross-sectional view showing a step of setting the thickness of a silicide film serving as a polycrystalline gate electrode in the process of manufacturing the MOS semiconductor device of FIG. FIG. 7 corresponds to the step of FIG. 3 in the first embodiment, and the other steps are basically the same as those of the first embodiment. The configuration is also the same as that of the first embodiment except for the thickness of the silicide film. In the following, the same components are denoted by the same reference numerals, and detailed description is omitted.

Generally, the finished grain size of a polycrystalline material such as silicide increases as the film thickness increases. Therefore, if the thickness of the local polycrystalline material is reduced using a mask after depositing a constant thickness, the grain size of the completed polycrystalline film can be locally changed within the wafer. Becomes For example, in the example of FIG. 6, even though the same impurity is ion-implanted in both the region A and the region B to make the WSix film conductive, the WS
Only by controlling the thickness of the i film, after the crystallization annealing,
The grain size of the gate electrode 22b in the region B is
Can be made larger than the gate electrode 22a side. More specifically, the maximum annealing temperature is 850 ° C. and the time is 30 minutes.
If the thickness of the WSix 22a is set to about 50 nm in the region A in the case of about min, the completed effective gate oxide thickness Tox.
It is possible to get ff. On the other hand, when the thickness of the WSix 22b is increased to about 150 nm in the region B, the effective oxide film thickness Tox.eff completed under the same annealing conditions becomes about 7 nm. The higher the maximum heat treatment temperature at the time of annealing, the more the grain growth in the WSix thick portion is promoted, and the larger the grain size becomes when an impurity such as As that promotes the grain growth is introduced.

As a specific method for providing a difference in WSix film thickness, first, in FIG. 7A, a photoresist 9 having an opening only in the region A is formed. Next, in the step of FIG. 7B, the WSix 22 is deposited only in the region A through the opening 9a of the photoresist 9 (to a thickness of 15 to 15 nm).
0 nm) to about 50 nm, for example, to locally reduce the thickness by etching. This thinning of WSix22 is based on R
Dry etching such as IE may be used, or wet etching may be used. In this example, FIG.
Before and after the step, it is necessary to dose a predetermined amount of a predetermined impurity by ion implantation over the entire surface.

According to such a method, the ion implantation and the formation of the photoresist mask pattern can be omitted once each as compared with the case of the first embodiment, and the process is simple. The change in grain size by controlling the film thickness may be combined with the first embodiment, that is, the type and / or dose of the impurity to be introduced and the film thickness of WSix may be simultaneously changed. Thus, although the number of steps increases, the effective oxide film thickness Tox.eff can be further increased between the regions A and B. Here, it is the same as in the first embodiment that the type of the polycrystalline material and the impurities, and the processing method and conditions can be modified.

[0042]

According to the semiconductor device and the method of manufacturing the same of the present invention, a transistor having two or more effective oxide film thicknesses by one oxidation (the oxide film thickness immediately after film formation is constant) can be obtained. It can be manufactured. As a result, a multi-oxide process can be performed without being affected by contamination from a resist or the like. Further, since a gate electrode such as metal or silicide is used, the sheet resistance of the gate electrode does not greatly change due to the completed effective gate oxide film thickness or grain size. For this reason, it is possible to respond only by changing the process without changing the basic parts of the already designed devices and circuit specifications, and it is possible to use the resources of such a design.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a main part of a MOS semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view showing each process of manufacturing the MOS type semiconductor device shown in FIG. 1, up to the formation of a WSix film.

FIG. 3 is a sectional view following FIG. 2, showing up to the implantation of impurity ions into a WSix film;

FIG. 4 is a sectional view following FIG. 3, showing up to WSix film processing (gate electrode formation);

FIG. 5 is a cross-sectional view following FIG. 4, showing up to the formation of an upper layer wiring;

FIG. 6 is a sectional view of a main part of a MOS type semiconductor device according to a second embodiment of the present invention.

FIG. 7 is a cross-sectional view showing a step of setting the thickness of a silicide film serving as a polycrystalline gate electrode in the process of manufacturing the MOS semiconductor device shown in FIG.

FIG. 8 is a graph showing the result of CV measurement in which a change in gate capacitance according to the type of impurity ions was examined.

FIG. 9 is a graph showing a relationship between an effective gate oxide film thickness and an ion dose obtained by calculation from a gate capacitance.

FIG. 10 is a view showing a cross-sectional structure in two regions having different gate oxide thicknesses, together with various manufacturing parameters, of a MOS type semiconductor device formed by a conventional method of changing an effective gate oxide thickness.

[Explanation of symbols]

1, 20 MOS type semiconductor device (semiconductor device), 2 silicon substrate, 4 element isolation region, 6 gate oxide film (gate insulating film), 8, 22 WSix film, 8a, 8b, 2
2a, 22b ... gate electrode (polycrystalline gate electrode), 9,
11, 13: photoresist, 10: interlayer insulating film, 12
... Connection plug, 14 ... Wiring, Cg ... Gate capacitance, Tox.e
ff: Completed effective gate oxide film thickness.

Claims (9)

[Claims] 1. A semiconductor device having a plurality of types of transistors having different characteristics depending on the thickness of a gate insulating film, wherein the thickness of the gate insulating film is constant among the plurality of types of transistors. And a grain size of a polycrystalline gate electrode on the gate insulating film is changed according to a type of a transistor. 2. The semiconductor device according to claim 1, wherein said polycrystalline gate electrode is made of a refractory metal silicide. 3. The semiconductor device according to claim 1, wherein at least one of the type and the amount of the impurity introduced into the polycrystalline gate electrode differs according to the type of the transistor. 4. The semiconductor device according to claim 1, wherein said polycrystalline gate electrode has a different thickness depending on the type of said transistor. 5. A method of manufacturing a semiconductor device having a plurality of types of transistors having different characteristics depending on the thickness of a gate insulating film, wherein the plurality of types of transistors have a gate insulating film formed on a surface of the semiconductor substrate. A method for manufacturing a semiconductor device in which a polycrystalline gate electrode is formed at one time by a single film forming step and a grain size is changed over the gate insulating film in accordance with a type of a transistor. 6. The method according to claim 5, wherein in forming the polycrystalline gate electrode, a refractory metal silicide film is formed, and the grain size is changed by heat treatment. 7. The method according to claim 5, wherein in forming the polycrystalline gate electrode, after laminating polycrystalline or amorphous silicon and a refractory metal, a grain is generated or changed in size when silicidation is performed by heat treatment. A method for manufacturing a semiconductor device. 8. A method for controlling the grain size according to the type of the transistor by changing at least one of the type and amount of impurities introduced into the polycrystalline gate electrode material when forming the polycrystalline gate electrode. A method for manufacturing a semiconductor device according to claim 5. 9. The method of manufacturing a semiconductor device according to claim 5, wherein, when forming said polycrystalline gate electrode, a grain size is controlled in accordance with a type of said transistor by changing a thickness setting thereof.