JPH11298267A - Audio fade circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a voice fading circuit which has its characteristic equiva lent to the case that a voice fading operation is executed by an analog signal using simple circuit constitution by generating a multiplication coefficient so that the way of a change in the coefficient to be inputted to a multiplication means varies in a straight line having plural gradients. SOLUTION: A voice fading circuit is provided with a multiplication circuit 4 which multiplies digital voices to be inputted by a multiplication coefficient and performs fade-in and fade-out operations and a multiplication coefficient generation circuit 3 which generates the multiplication coefficient that is multiplied by the circuit 4. Thus, the voice fading circuit is used both as a multiplication circuit so as to be used for a digital filter, for example and accordingly the number of circuits and their parts to be used can be decreased. At the same time, the voice fading characteristic that is similar to an analog voice fading operation can be secured by changing the multiplication coefficient generated by the circuit 2 in a polygonal line form. As a result, the number of constituted circuits and their parts can be reduced and the voice fading circuit can be easily taken in an integrated circuit, etc.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an audio fade circuit suitable for use in a digital video camera (DVC), a mini disc player (MD), and the like.

[0002]

2. Description of the Related Art In recent years, in a DVC or MD audio processing circuit, a fade-in function in which the sound gradually increases and a fade-out function in which the sound gradually decreases to effectively record and reproduce the sound. Many have a voice fade function.

[0003] A conventional audio fade circuit will be described below. Conventionally, the audio fade circuit has been
No. 0 is known. FIG. 6 shows the audio fade circuit. FIG. 6 shows a block diagram of a conventional audio fade circuit, and FIG. 7 shows a signal waveform at each point in FIG. 6, reference numeral 1 denotes an audio input terminal to which an audio signal is input, and 5 denotes an amplifier circuit for amplifying the audio signal input from the audio signal input terminal 1, and an automatic gain control function for controlling the gain of the input audio signal. It has. Reference numeral 2 denotes an audio output terminal for outputting an audio signal output from the amplifier circuit 5 to the outside, reference numeral 3 denotes a DC voltage addition terminal to which a DC voltage (for example, +5 V) is input, and reference numeral 4 denotes an audio fade control signal input by a user operation. The audio fade control signal input terminal receives a control signal when the user operates a fade switch provided in, for example, a video camera. Reference numeral 8 denotes a switch circuit for generating an audio fade signal from the audio fade control signal from the audio fade control signal input terminal 4 and the DC voltage from the DC voltage adding element 3, and 7 denotes only a low frequency band of the audio fade signal from the switch circuit 8. A low-pass filter (hereinafter, referred to as an LPF) 6 that passes therethrough is a voltage limit circuit that controls the gain in the amplifier circuit 5 based on the audio fade signal from the LPF 7.

The operation of the conventional audio fade circuit configured as described above will be described below.

First, when the audio fade control signal is not input (between waveforms A and B in FIG. 7C and after point E), the potential at point S4 in FIG. Since no electric potential is applied, the audio signal (the waveform of FIG. 7A) input to the audio input terminal 1 is amplified by the gain by the amplifier circuit 5 and output to the audio output terminal 2. (Between waveforms A and B in FIG. 7B and after point E).

Next, when an audio fade control signal is input to the audio fade control terminal 4 (waveform B in FIG.
7), a voice fade signal having a waveform shown in FIG. 7D is generated in the switch circuit 8 by the DC voltage applied to the DC voltage addition terminal 3 and the voice fade control signal. The audio fade signal changes as shown in the waveform of FIG. 7E by passing through the LPF 7. The time during which the DC voltage is applied is determined by the time constant in the LPF 7. The applied voltage is applied to the automatic gain control circuit of the amplifier circuit 5 to operate the automatic gain control. Therefore, although the voltage applied to the point S5 in FIG. 6 is determined by the voltage limit circuit 6, it is necessary to have a level sufficient to operate the automatic gain control circuit of the amplifier circuit 5 sufficiently.
Automatic gain control is gradually performed in the automatic gain control circuit by the voltage applied to the point S5 in FIG. 6, and the amplitude of the audio signal output from the amplifier circuit gradually decreases (FIG. 7 (b)). ) Waveforms B to C). As described above, the time during which the amplitude of the output audio signal is reduced and faded out is determined by the time constant in the LPF 7.

When the input of the audio fade control signal is stopped after the input of the audio fade control signal (point D in FIG. 7C), the potential at the point S4 in FIG. Since the DC voltage reaches the ground level, the DC voltage applied to the point S5 in FIG. 6 gradually falls to the ground level mainly through the voltage limit circuit 6, and the automatic gain control circuit does not operate. As a result, the automatic gain control circuit gradually stops the automatic gain control, and the amplitude of the audio signal output from the amplifier circuit gradually increases (between waveforms D to E in FIG. 7B). Therefore, the time during which the amplitude of the audio signal increases (fade-in) is determined by the voltage held by the voltage limit circuit 6 and the amount of current when the voltage is discharged. The audio fade operation is performed as described above.

[0008]

However, in the above-mentioned conventional configuration, since the audio fade is performed when the audio signal is an analog signal, the automatic gain control circuit and the voltage limit described in the above-mentioned conventional configuration are used. A circuit such as a circuit is required, which is disadvantageous for downsizing the circuit.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problems, and has as its object to provide an audio fade circuit having a characteristic equivalent to that of performing an audio fade operation with an analog signal using a simple circuit configuration. I do.

[0010]

In order to achieve the above object, an audio fade circuit according to the present invention is an audio fade circuit capable of fading in and out an input digital audio signal. And a multiplication coefficient generating means for generating a multiplication coefficient set so that the manner of changing the coefficient input to the multiplication means changes with a straight line having at least two slopes. It is a thing.

With such a configuration, it is possible to obtain an audio fade circuit having a characteristic equivalent to that of performing an audio fade operation with an analog signal using a simple circuit configuration.

The multiplication coefficient generation circuit includes a timing generation means for generating a clock of a counter included in the multiplication coefficient generation means at a timing for generating a multiplication coefficient;
A first counter that operates based on a clock generated from the timing generation means, an enable signal that allows the counter to operate when the value of the first counter reaches a predetermined value, and a first counter A first decoder for generating a signal for resetting the clock, an up / down counter for increasing or decreasing a multiplication coefficient by an enable signal from the first decoder and a clock from the timing generation means, and a signal generated by the up / down counter. A second decoder for controlling the operation of the first decoder in accordance with a value of the multiplication coefficient, wherein the up / down counter operates as a down counter for gradually decreasing the coefficient from the maximum multiplication coefficient when fading out, and fading in. Sometimes as an up-counter that gradually increases the coefficient from the smallest multiplication coefficient It is intended to generate a multiplication factor, such as work.

With this configuration, it is possible to obtain an audio fade circuit having a characteristic equivalent to that of performing an audio fade operation with an analog signal using a simple circuit configuration.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The invention according to claim 1 of the present invention is an audio fade circuit capable of fading an input digital audio signal in and out, wherein the input digital audio signal is multiplied by a multiplication coefficient. Multiplying means, and a multiplying coefficient generating means for generating a multiplying coefficient set so that the way of changing the coefficient input to the multiplying means changes with a straight line having at least two slopes, Using a simple circuit configuration, it is possible to obtain an audio fade circuit having the same characteristics as those when performing an audio fade operation with an analog signal.

The invention according to claim 2 of the present invention provides:
The multiplication coefficient generation circuit is configured to generate a multiplication coefficient at a timing to generate a clock of a counter included in the multiplication coefficient generation means, and to operate based on a clock generated from the timing generation means. A counter, and a first signal for generating an enable signal permitting the operation of the counter when the value of the first counter reaches a predetermined value or a signal for resetting the first counter.
And an up / down counter for increasing or decreasing a multiplication coefficient by an enable signal from the first decoder and a clock from the timing generator.
A second decoder for controlling the operation of the first decoder in accordance with the value of the multiplication coefficient generated by the up / down counter, wherein the up / down counter gradually decreases the coefficient from the maximum multiplication coefficient when fading out. It operates as a counter and generates a multiplication coefficient that operates as an up counter that gradually increases the coefficient from the minimum multiplication coefficient at the time of fade-in. Using a simple circuit configuration, an analog signal is used to perform audio fade operation. This has the effect that an audio fade circuit having the same characteristics as in the case can be obtained.

Hereinafter, an embodiment of the present invention will be described with reference to FIG.
This will be described with reference to FIG. (Embodiment 1) FIG. 1 is a block diagram of an audio fade circuit of the present embodiment. In FIG. 1, reference numeral 1 denotes a digital audio input terminal for inputting a digital audio signal, and reference numeral 2 denotes an audio fade control command signal. An audio fade control input terminal 3 is a multiplication coefficient generation circuit which is a multiplication coefficient generation means for determining a time constant and characteristic inclination of the audio fade, and 4 is a digital audio signal input from the digital audio input terminal 1 and a multiplication coefficient generation circuit 3 The multiplication circuit is a multiplication means for multiplying the multiplication coefficient generated by the multiplication factor, and is also used as a multiplication circuit used in, for example, a digital filter. Reference numeral 5 denotes a digital audio output terminal for outputting the digital audio signal output from the multiplication circuit 4 to the outside.

FIG. 2 is a block diagram showing an example of the multiplication coefficient generating circuit 3 of FIG. In FIG. 2, reference numeral 11 denotes a timing generation circuit which generates a clock of a counter included in the multiplication coefficient generation circuit 3 at a timing for generating a multiplication coefficient, and 12 denotes a counter which operates based on the clock generated from the timing generation circuit 11. , 13 is the counter 1
A first decoder 14 for generating an enable signal for allowing the operation of the counter 12 and a signal for resetting the counter 12 when the value of 2 becomes a certain value, a down decoder for gradually decreasing the coefficient from the maximum multiplication coefficient at the time of fade-out An up-down counter that operates as a counter and generates a multiplication coefficient so as to operate as an up-counter that gradually increases the coefficient from the minimum multiplication coefficient at the time of fade-in, and 15 corresponds to the value of the multiplication coefficient generated by the up-down counter 14 A second decoder 16 for determining the operation of the first decoder 13 is a multiplication coefficient output terminal for outputting the multiplication coefficient generated by the up / down counter 14.

FIGS. 3 and 4 are timing charts of respective signals in the present embodiment. The continuation of the timing chart of FIG. 3 is the timing chart of FIG. FIG.
6 is a characteristic diagram showing characteristics of a multiplication coefficient that changes with time.

The operation of the audio fade circuit of the present embodiment configured as described above will be described with reference to FIGS.

First, the fade-out operation of the audio fade circuit according to the present embodiment will be described.

In the timing generation circuit 11 of FIG.
A clock signal as shown in FIG. 3A is output so that the digital audio signal input from the digital audio input terminal 1 of FIG. The counter 12 is set so that the counter value increases for each clock output from the timing generation circuit 11. In the second decoder 15 monitoring the output of the multiplication coefficient from the up / down counter 14, the multiplication coefficient (here, X) is out of the range indicated as α and β in the characteristic diagram of the multiplication coefficient in FIG. In the case of (X> α, X <β), for example, “0” is output, and within the range indicated by α and β (β ≦ X
When ≦ α), for example, an operation is performed to output “1”.

The first decoder 13 operates so as to enable the up-down counter 14 (permit operation) and control the reset of the counter 12 by watching the output value from the second decoder 15. For example, t2 in FIG.
3 (b) when the output value from the second decoder 15 is "0" (when the multiplication coefficient X is out of the range of [alpha] to [beta], for example, M in FIG. 5). 12
When the output value of the first decoder 13 becomes “3”, the first decoder 13
3D to output a signal of “1” as shown in FIG. 3D to output an enable signal and a reset signal. Also, as at the timing of t1 in FIG. 4, the output value from the second decoder 15 is “1” (the multiplication coefficient X is α to
When the output value of the counter 12 is “0” in the range of β, for example, N in FIG. 5, the first decoder 13 outputs a signal of “1” as shown in FIG. And outputs an enable signal and a reset signal.

In this case, the first decoder 13 operates so that the output value from the second decoder 15 is "0", the output value of the counter 12 is "3", and the enable signal and the reset signal are output. If so, the output signal of the counter 12 operates so as to repeatedly output "0" to "3" as shown in the counter output of FIG. Further, when the output value from the second decoder 15 is “1”, the counter 1
2 is "0" and the first decoder 13 is operating to output the enable signal and the reset signal, as shown in the counter output after t1 in FIG. Operates so as to repeatedly output "0".

When a fade-out operation is performed, a fade control signal input from the audio fade control input terminal 2 is received, and the up-down counter 14 in FIG. 2 operates as a down counter that gradually decreases.

In the fade-out operation, if the multiplication coefficient is out of the range indicated by α and β on the characteristic diagram of the multiplication coefficient shown in FIG. 5, the output value of the counter 12 is changed as shown in FIG. When "3" is reached, the up-down counter 14 operates so as to gradually decrease by one from the maximum value of the multiplication coefficient (here, M). Also, when the multiplication coefficient is within the range shown as α and β,
As shown after t1 in FIG. 4B, the output of the counter 12 becomes "0" in all ranges, and the enable signal is input to the up-down counter 14 in FIG. 2 in all ranges. As a result, in the up / down counter 14, every time a clock signal is input, the multiplication coefficient decreases, for example, by 1 from the value when X = α (here, N).

The multiplication coefficient output from the multiplication coefficient generation circuit 3 shown in FIG.
Is multiplied by the multiplication circuit 4 and the digital audio signal output from the digital audio output terminal 5 is faded out by an approximate straight line as shown in the characteristic diagram of the multiplication coefficient in FIG. Will work.

Further, in the case of the fade-in operation, the operation of the multiplication coefficient generating circuit 3 is completely opposite to the operation of the fade-out operation, and the up / down counter 14 functions as an up counter that gradually increases by one from the minimum multiplication coefficient. Perform the operation. The multiplication coefficient thus generated is output to the multiplication circuit 4, and the multiplication circuit 4 multiplies the multiplication coefficient with the digital audio input from the digital audio input terminal 1, thereby obtaining the digital audio output from the digital audio output terminal 5. A fade-in operation can be performed.

As described above, according to the present embodiment, a multiplication circuit 4 for multiplying an input digital voice by a multiplication coefficient to perform fade-in and fade-out, and a multiplication circuit for generating a multiplication coefficient to be multiplied by the multiplication circuit 4 By providing the coefficient generation circuit 3, the circuit and the number of components used can be reduced by, for example, using the same as a multiplication circuit used in a digital filter, and the multiplication coefficient generated by the multiplication coefficient generation circuit 3 is shown. By changing the characteristic as shown in FIG. 5, it is possible to obtain an audio fade characteristic similar to the analog audio fade operation.

In the above description, the switching range of the second decoder 15 in FIG. 2 is set to two points α and β, but control may be performed with three or more switching ranges. Further, the values of the enable and reset controls of the first decoder 13 in FIG. 2 are set to “0” and “3”, but it is naturally possible to set other values.

In the above description, the increase / decrease value of the up / down counter 14 is set to "1", but it is naturally possible to set this to other numbers. further,
In the above description, a straight line having the same inclination is used for the fade-out and the fade-in, but a different line may be used for the fade-out and the fade-in.

[0031]

As described above, according to the present invention, it is possible to reduce the number of configured circuits and components, to easily incorporate the circuit into an integrated circuit, etc. An excellent effect that it is possible to obtain the same fade characteristics as the fade operation is obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram of an audio fade circuit according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a multiplication coefficient generation circuit according to the first embodiment.

FIG. 3 is an operation waveform diagram for explaining an operation of the audio fade circuit according to the first embodiment;

FIG. 4 is an operation waveform diagram for describing an operation of the audio fade circuit according to the first embodiment.

FIG. 5 is a characteristic diagram of a multiplication coefficient in the audio fade circuit according to the first embodiment.

FIG. 6 is a block diagram of a conventional audio fade circuit.

FIG. 7 is a signal waveform diagram for explaining the operation of a conventional audio fade circuit.

[Explanation of symbols]

 Reference Signs List 1 digital audio input terminal 2 audio fade control input terminal 3 multiplication coefficient generation circuit 4 multiplication circuit 5 digital audio output terminal

Claims (2)

[Claims] 1. An audio fade circuit capable of fading in and out an input digital audio signal, wherein the multiplication means multiplies the input digital audio signal by a multiplication coefficient, and a change in a coefficient input to the multiplication means. And a multiplication coefficient generating means for generating a multiplication coefficient set such that the method changes in a straight line having at least two slopes. 2. A multiplication coefficient generation circuit, comprising: timing generation means for generating a clock of a counter included in the multiplication coefficient generation means at a timing for generating a multiplication coefficient; and a clock generated from the timing generation means. A first counter that operates, a first decoder that generates an enable signal that allows the operation of the counter when the value of the first counter reaches a predetermined value, and a signal that resets the first counter. An up / down counter for increasing or decreasing a multiplication coefficient by an enable signal from the first decoder and a clock from the timing generation means; and the first decoder according to a value of the multiplication coefficient generated by the up / down counter. And a second decoder for controlling the operation of the up / down counter. 2. A multiplication coefficient which operates as a down counter for gradually decreasing a coefficient from a maximum multiplication coefficient and operates as an up counter for gradually increasing a coefficient from a minimum multiplication coefficient during fade-in. Audio fade circuit.