JPH11307785A - Power semiconductor device - Google Patents

Abstract

(57) [Summary] [Problem] To increase breakdown voltage without increasing chip size,
Alternatively, reduce the chip size without reducing the withstand voltage. SOLUTION: An n- type semiconductor layer 1 having a main surface
And a p + formed on the n− type semiconductor layer 1 and terminating a pn junction with the n− type semiconductor layer 1 on the main surface.
Type anode layer 2, a groove 6 formed on the main surface between the pn junction and the end of n @-type semiconductor layer 1, an insulating film 7 formed in groove 6, and a groove 6 formed in groove 6. And a gate electrode 8 insulated from the n − type semiconductor layer 1 via an insulating film 7.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a termination structure of a power semiconductor device used in a circuit for high power use.

[0002]

2. Description of the Related Art As an electric circuit, there is a circuit for high power application to which a large voltage of, for example, about 100 V is applied. For such a circuit for high power use, a semiconductor device having a very high withstand voltage, for example, called a power semiconductor device is used.

As this type of semiconductor device, there is, for example, a horizontal diode used as a rectifier in a circuit. FIG. 19A is a plan view of a conventional lateral diode, and FIG.
FIG. 20B is a sectional view taken along line XIXB-XIXB in FIG.

As shown in FIGS. 19A and 19B, n-
The mold layer 301 is made of, for example, a silicon substrate, and a p + -type anode layer 302 is formed in a surface region of the n − -type layer 301. This p + type anode layer 302 is an n − type layer 3
01, that is, away from the end of the chip. Thereby, the p + type anode layer 302 and the n− type layer 301
The n-junction, or main junction, terminates in the major plane of n-type layer 301. The anode electrode 303 is a p + type anode layer 30
2 is electrically connected. An n + -type cathode layer 304 is formed at a portion along the end of the n − -type layer 301. The n + -type cathode layer 304 is formed along the end of the n − -type layer 301, that is, along the end of the chip, and thus surrounds the p + -type anode layer 302 in a plane. Thereby, a horizontal diode is formed.

The n + -type cathode layer 304 is formed along the end of the chip, so that the pn junction between the p + -type anode layer 302 and the n − -type layer 301, that is, from the main junction to the end of the chip. The extended depletion layer serves to prevent contact with the end of the chip. That is, the n + -type cathode layer 304 functions as a cathode and also serves as a stopper layer, which is one of the terminal structures. Cathode electrode 305 is electrically connected to n + -type cathode layer 304.

[0006]

However, in the conventional lateral diode, in order to increase the breakdown voltage of the product, p
The distance between the + type anode layer 302 and the n + type cathode layer 304 has to be increased, which leads to an increase in chip size.
Further, in order to reduce the chip size of a product, there has been a situation that the breakdown voltage of the product must be reduced.

The present invention has been made in view of the above circumstances, and has as its object to increase the withstand voltage without increasing the chip size or to reduce the chip size without decreasing the withstand voltage. Is to provide.

[0008]

In order to achieve the above object, in a power semiconductor device according to the present invention, a semiconductor substrate of a first conductivity type having a main surface and a semiconductor substrate of the first conductivity type are provided. A semiconductor region of the second conductivity type formed and terminating a main junction with the semiconductor substrate at the main surface; and formed at the main surface between the main junction and an end of the semiconductor substrate. A groove, an insulator formed in the groove, and an electrode body formed in the groove and insulated from the semiconductor substrate via the insulator.

Further, a semiconductor substrate of a first conductivity type having a main surface and a main junction formed in the semiconductor substrate of the first conductivity type and terminating at the main surface are terminated at the main surface. A semiconductor region of a second conductivity type, a first electrode electrically connected to the semiconductor substrate of the first conductivity type, and a second electrode electrically connected to the semiconductor region of the second conductivity type. A groove formed on the main surface between the semiconductor substrate of the first conductivity type and the semiconductor region of the second conductivity type;
An insulator formed in the groove, and an insulator formed in the groove;
It is characterized by comprising an electrode body insulated from the semiconductor substrate via the insulator.

In the power semiconductor device having the above configuration, when the semiconductor substrate and the semiconductor region are reverse-biased, the equipotential lines in the insulator formed in the trench are set to “dense”.
It is possible. If the equipotential lines in the insulator formed in the trench become “dense”, the equipotential lines in the semiconductor substrate become “sparse”. Thus, the electric field in the semiconductor substrate can be reduced.

In addition, since the main surface between the main junction and the end of the semiconductor substrate has a groove in which an electrode body is formed, it is possible to eliminate a corner where an electric field is concentrated from the main junction, or Even if there is a part, it is possible to reduce the concentration of the electric field. Eliminating the corners or alleviating the electric field at the corners makes it less likely to cause avalanche breakdown.
Therefore, the breakdown voltage can be increased without increasing the chip size, or the chip size can be reduced without decreasing the breakdown voltage.

[0012]

Embodiments of the present invention will be described below with reference to the drawings. In this description, common parts are denoted by common reference numerals throughout the drawings. [First Embodiment] FIG. 1A is a plan view of a lateral diode according to a first embodiment of the present invention, and FIG. 1B is a plan view of the IB in FIG. 1A.
It is sectional drawing which follows the -IB line.

As shown in FIGS. 1A and 1B, the n − type layer 1 is made of, for example, a silicon substrate, and ap + type anode layer 2 is formed in the surface region of the n − type layer 1. I have. The p @ + -type anode layer 2 is separated from the terminal of the n @-type layer 1, that is, the terminal of the chip. As a result, the pn junction between the p + -type anode layer 2 and the n − -type layer 1, that is, the main junction, terminates at the main plane of the n − -type layer 1. The anode electrode 3 is electrically connected to the p + type anode layer 2. An n + -type cathode layer 4 is formed at a portion along the end of the n − -type layer 1. The n + -type cathode layer 4 is formed along the end of the n − -type layer 1, that is, along the end of the chip, and thus surrounds the p + -type anode layer 2 in a plane. Thereby, a horizontal diode is formed.

The n + -type cathode layer 4 is formed along the end of the chip, so that the pn junction between the p + -type anode layer 2 and the n − -type layer 1, ie, from the main junction to the end of the chip. The extended depletion layer serves to prevent contact with the end of the chip. That is, the n + type cathode layer 4
At the same time as functioning as a cathode, it also serves as a stopper layer, which is one of the terminal structures. Cathode electrode 5 is electrically connected to n + type cathode layer 4.

Further, a groove 6 is formed in a portion of the n− type layer 1 between the p + type anode layer 2 and the n + type cathode layer 4. The groove 6 is formed between the p + type anode layer 2 and the n − type
It is formed between the n-junction and the end of the chip. A gate electrode 8 is formed inside the groove 6 via an insulating film 7.
The insulating film 7 is made of, for example, silicon dioxide.

FIG. 2 is an enlarged view of the inside of the frame II in FIG. FIG. 2 shows that the gate electrode 8 is connected to the anode electrode 3 with the anode electrode 3 and the cathode electrode 5 reversely biased.
Shows the potential distribution when connected to.

As shown in FIG. 2, when the anode electrode 3 and the cathode electrode 5 are reversely biased, the n− type layer 1
Then, a depletion layer extends from the p + -type anode layer 2 to the n + -type cathode layer 4. When the gate electrode 8 is connected to the anode electrode 3 in the reverse biased state, a p-type inversion layer is induced around the groove 6. As a result, part of the electric field generated between the p + -type anode layer 2 and the n + -type cathode layer 4
It will cover the insulating film 7 in the groove 6. Therefore, the electric field in the n − -type layer 1 is reduced, and the extension of the depletion layer to the n − -type layer 1 can be suppressed. The broken lines in FIG. 2 indicate equipotential lines. As shown by the broken line, the equipotential lines become “dense” in the insulating film 7 formed in the trench 6.

FIGS. 3A and 3B are diagrams showing the potential distribution when the gate electrode 8 is connected to the anode electrode 3 in a state where the anode electrode 3 and the cathode electrode 5 are reversely biased, respectively. is there. FIG. 3A shows the potential distribution of the conventional horizontal diode product, and FIG. 3B shows the potential distribution of the horizontal diode product according to the first embodiment. Further, the anode electrode 3 and the cathode electrode 5
Is 100 V.

As compared with the conventional lateral diode shown in FIG. 3A, the lateral diode according to the first embodiment shown in FIG. 3B has an equal potential in the insulating film 7 formed in the groove 6. Since the line becomes “dense”, the equipotential lines in the n− type layer 1 become “sparse”.
become. A "dense" portion of the equipotential lines indicates a large electric field, and a "sparse" portion indicates a small electric field. For example, comparing the distance from the end of the chip to the 75 V equipotential line, the distance is “L” in the conventional horizontal diode shown in FIG. In the lateral diode according to the first embodiment, the distance “L ′” is longer than the distance “L”. An increase in the distance from the end of the chip to an equipotential line of, for example, 75 V indicates that the electric field in the n − -type layer 3 has decreased.

As shown in FIG. 2A, in the conventional lateral diode, the pn junction between the p + -type anode layer 2 and the n--type layer 1, that is, the main junction is the main surface of the n--type layer 1. Has ended. Therefore, the main joint has a corner portion 201. In the corner portion 201, the electric field is easily concentrated, and avalanche breakdown is likely to occur. On the other hand, in the lateral diode according to the first embodiment, the main junction is terminated in the groove 6 to eliminate a corner portion from the main junction as shown in FIG. Even if there is a portion, the gate electrode 8 having substantially no potential difference with the anode electrode 3 can be arranged adjacent to the portion, so that concentration of the electric field at the corner portion can be reduced. Therefore, avalanche breakdown can be made more difficult to occur.

According to such a first embodiment, p
When a reverse bias is applied to the pn junction between the + type anode layer 2 and the n − type layer 1, that is, the main junction, the main junction and the n − type layer 1
The end of the chip, that is, the equipotential line generated between the end of the chip,
Since the potential can be unevenly distributed so as to be “dense” in the insulating film 7 formed in the groove 6 and “sparse” in the n − -type layer 1, the electric field in the n − -type layer 1 can be reduced.

Further, even if there is a portion where the electric field tends to concentrate at the main junction, the concentration of the electric field at this portion can be reduced, and avalanche breakdown can be less likely to occur. Therefore,
The breakdown voltage of the lateral diode can be improved, and if the chip size is the same as that of the conventional product, the breakdown voltage can be further increased. If the breakdown voltage is the same as that of the conventional product, the chip size can be further reduced.

The above-mentioned lateral diode has a capacity of 10 as described above.
It is used in circuits for high power applications where a reverse bias of 0 V or more is applied. In such a circuit for high power use, the horizontal diode can be used, for example, as a rectifier.

[Second Embodiment] In the above-described first embodiment, an example of a horizontal diode has been described. However, the present invention can be applied not only to a horizontal diode but also to a vertical diode with the same effect as described above. .

FIG. 4A is a plan view of a vertical diode according to a second embodiment of the present invention, and FIG. 4B is a sectional view taken along the line IVB-IVB in FIG. FIG. 5 is FIG.
It is an enlarged view in the frame V in (B).

As shown in FIGS. 4A and 4B, the n + -type cathode layer 4 ′ is formed not on the end of the n − -type layer 1 but on the back surface thereof. The cathode electrode 5 'is electrically connected to an n + type cathode layer 4' formed on the back surface of the n- type layer 1. Thereby, the diode becomes a vertical type.

At the end of the n − -type layer 1, that is, at the end of the chip, the p + -type anode layer 2 is planarized similarly to the n + -type cathode layer 4 shown in FIGS. 1A and 1B. An n @ + -type layer 24 is formed so as to surround it. The n @ + -type layer 24 is a stopper layer which is one of the termination structures, and a pn junction between the p @ + -type anode layer 2 and the n @--type layer 1, that is, a depletion layer generated at the main junction contacts the end of the chip. Has the role of preventing
This suppresses remarkable deterioration in breakdown voltage caused by the depletion layer reaching the end of the semiconductor substrate.

In the second embodiment, as shown in FIG. 5, when the anode electrode 3 and the cathode electrode 5 'are reverse-biased, the p + type anode layer 2 A depletion layer is generated which extends toward the negative-type cathode layer 4 and at the same time toward the end of the n − -type layer 1. When the gate electrode 8 is connected to the anode electrode 3 in the reverse biased state,
A p-type inversion layer is induced around the groove 6. This allows
From the pn junction between the p + type anode layer 2 and the n − type layer 1, n
-A part of the electric field generated toward the end of the mold layer 1 is applied to the insulating film 7 in the groove 6.

The broken lines in FIG. 5 indicate equipotential lines. As shown by the broken line, in the second embodiment, the equipotential lines are "dense" in the insulating film 7 formed in the groove 6 as in the first embodiment. Thereby, the electric field in the n − -type layer 1 can be reduced, and the extension of the depletion layer toward the end of the n − -type layer 1 can be suppressed.

Further, similar to the first embodiment, since the groove 6 is provided, the pn layer between the p + type anode layer 2 and the n −
The corner portion can be eliminated from the junction, or the electric field at the corner portion can be reduced. Thereby, avalanche breakdown can hardly occur.

Therefore, the withstand voltage of the vertical diode can be improved, the withstand voltage can be further increased if the chip size is the same as that of the conventional product, and the chip size can be further increased if the withstand voltage is the same as that of the conventional product. Can be smaller.

The vertical diode is used in a circuit for a high power application in which a reverse bias of, for example, 100 V or more is applied, like the horizontal diode, and is used, for example, as a rectifier.

[Third Embodiment] In the first and second embodiments, the electric field between the main junction formed on the semiconductor substrate, for example, the pn junction between the anode and the cathode of the diode and the terminal of the semiconductor substrate is reduced. Although an example of relaxation is shown, the present invention can also relax the electric field between the main junction and an electrode formed in the middle of the semiconductor substrate. As a semiconductor device having an electrode formed in the middle of a semiconductor substrate, for example, there is an IGBT with a freewheeling diode.

FIG. 6 is a plan view of an IGBT with a free wheel diode according to a third embodiment of the present invention, and FIG.
It is sectional drawing which follows the I-VII line. FIG. 8 is an enlarged view in a frame VIII in FIG.

As shown in FIGS. 6 to 8, the n − -type base layer 31 is made of, for example, a silicon substrate, and a p-type base layer 32 is formed in a surface region of the n − -type base layer 31. This p-type base layer 32 is separated from the end of the n − -type base layer 31, that is, the end of the chip. In the third embodiment, the p-type base layer 32 is disposed on both sides of a region 101 (hereinafter, center region) located at the center of the chip. In the third embodiment, the center region 101 is extended in one direction, and is a band-like region when viewed from a plane. On the surface of the center region 101, the n @-type base layer 31 is exposed. In the center region 101, an n + type cathode layer 33 is formed. This n + type cathode layer 33 is
Are separated from the p-type base layer 32 disposed on both sides of the p-type base layer 32. Further, in the third embodiment, the n + -type cathode layer 33 is formed in a band along the center region 101. A cathode electrode 34 is electrically connected to the n + type cathode layer 33.

On the back surface of the n- type base layer 31, ap + type collector layer 35 is formed. A collector electrode 36 is electrically connected to the p + type collector layer 35. The cathode electrode 34 is electrically connected to the collector electrode 36 (see FIG. 7).

The p-type base layer 32 has a plurality of trenches (hereinafter referred to as trenches) 37 penetrating therethrough and reaching the n − -type base layer 31. In the third embodiment, the plurality of trenches 37 extend in a direction along the center region 101, and are arranged in a stripe shape when viewed from above. A gate insulating film 38 is formed in each of the trenches 37, and a gate electrode 39 that is capacitively coupled to the p-type base layer 32 via the gate insulating film 38 is formed. The gate insulating film 38 is made of, for example, silicon dioxide, and the gate electrode 39 is made of, for example, conductive polysilicon. The gate electrode 39 formed in the trench 37 is a control terminal for receiving a control signal for switching the IGBT.

An n + -type emitter layer 40 is formed on the surface of the p-type base layer 32 exposed between the trenches 37. In the n + type emitter layer 40, a p + type layer 41 penetrating therethrough and reaching the p type base layer 32 is formed. An emitter electrode 42 is electrically connected to the n + -type emitter layer 40 and the p + -type layer 41.

Of the plurality of trenches 37, the trench 37 adjacent to the center region 101 and the center region 1
A p + -type anode layer 43 is formed in a region between the n + -type cathode layer 33 and the n + -type cathode layer 33. This p +
The anode layer 43 is separated from the n + cathode layer 33. In the third embodiment, the p + -type anode layer 43 is formed along the trench 37 along the n + -type cathode layer 3.
3 is formed in a belt shape so as to face each other. An anode electrode 44 is electrically connected to the p + type anode layer 43. The anode electrode 44 is electrically connected to the emitter electrode 42 (see FIG. 7). Thereby, in the third embodiment, the IGBT
And a diode having a cathode connected to the collector of the IGBT and an anode connected to the emitter of the IGBT, are formed in one chip. This diode is a freewheeling diode FWD (Free Whe
elingDiode). In addition, these IGBTs and the reflux diode F
An n + type stopper layer 45 is formed so as to surround the portion where WD is formed.

A groove 46 is formed in the portion of the n − -type base layer 31 between the p + -type anode layer 43 and the n + -type cathode layer 33.
Are formed. This groove 46 is formed in the p + type anode layer 43.
Junction between the N + -type base layer 31 and an electrode formed in the middle of the chip. In the third embodiment, the n + -type cathode electrode 34 (the n + -type cathode layer 3
3) is formed. An insulating film 47 is provided inside the groove 46.
A gate electrode 48 is formed through the substrate. Insulating film 47
Is made of, for example, silicon dioxide, and the gate electrode 48 is made of, for example, conductive polysilicon. The gate electrode 48 formed in the groove 46 is formed between the p + type anode layer 43 and the n +
-When the pn junction with the mold base layer 31 is reverse biased,
The electric field generated in the n − -type base layer 31 in the center region 101 is reduced, and is similar to the gate electrode 8 of the first and second embodiments.

In the third embodiment, the emitter electrode 42
Is at a low potential, the collector electrode 36 is at a high potential, and the control signal received by the gate electrode 39 is at a level that turns off the IGBT. A depletion layer extends from 43 toward the n + -type cathode layer 33. When the gate electrode 48 is connected to the emitter electrode 42 in this state,
As in the first and second embodiments, a p-type inversion layer is induced around the groove 46. Therefore, the p + type anode layer 43
From the pn junction between the n− type base layer 31 and the main junction,
A part of the electric field generated toward the n + -type cathode layer 33 is applied to the insulating film 47 in the groove 46, and the electric field in the insulating film 47 formed in the groove 46 is similar to the first and second embodiments. , The equipotential lines become “dense”. Thereby, the electric field in the n − -type base layer 31 in the center region 101 can be reduced.

As in the first and second embodiments,
Since the groove 46 is provided, the corner portion can be eliminated from the pn junction between the p + -type anode layer 43 and the n − -type base layer 31, or the concentration of the electric field can be reduced even if the corner portion exists.
Thereby, avalanche breakdown can hardly occur.

As a result, the IGB with the freewheel diode is provided.
At T, the breakdown voltage can be further increased if the chip size is the same as that of the conventional product, and the chip size can be further reduced if the breakdown voltage is the same as that of the conventional product.

The IGBT with the freewheeling diode is used in a circuit for a high power application in which a reverse bias of, for example, 100 V or more is applied, and is used, for example, as a switching element.

In the third embodiment, the groove 46 is n
Although an example is shown in which two are formed so as to sandwich the + type cathode layer 33 therebetween, for example, the groove 46 may be formed in a planar annular shape so as to surround the n + type cathode layer 33. In this case, the gate electrode 48 formed in the groove 46 also
It may be formed in an annular shape similar to the above.

[Fourth Embodiment] The fourth embodiment is similar to the third embodiment in that an IGB with a free wheel diode is provided.
It is an example of T. The difference from the third embodiment is that
That is, the cathode or anode of the reflux diode is shared with the terminal structure of the chip, that is, the region functioning as a stopper layer.

FIG. 9 is a plan view of an IGBT with a free wheel diode according to a fourth embodiment of the present invention, FIG. 10A is a sectional view taken along line XA-XA in FIG. 9, and FIG. FIG.
It is sectional drawing which follows the XB-XB line in the inside. FIG. 11 is an enlarged view of a frame XI in FIG.

As shown in FIGS. 9 to 11, the n + -type cathode layer 33 'is formed not at the center region of the chip but at its end, that is, at the end of the n--type base layer 31.
The cathode electrode 34 'is electrically connected to the n + type cathode layer 33'. The n + type cathode layer 33 'is formed along the terminal portion of the chip so as to surround the portion where the IGBT is formed. Therefore, the n + type cathode layer 33' functions as a stopper layer. Thus, in the fourth embodiment, the cathode of the free wheel diode FWD is shared with the chip termination structure, that is, the region functioning as the stopper layer.

In the fourth embodiment, unlike the third embodiment, there is no center region where no IGBT is formed, and the fourth embodiment is surrounded by the n + -type cathode layer 33 ′ The IGBT is formed over the entire portion away from the ′.

In the fourth embodiment, as in the third embodiment, the emitter electrode 42 is at a low potential, the collector electrode 36 is at a high potential, and the control signal received by the gate electrode 39 is "IGBT". When the level is "off", the n- type base layer 31 between the p + type anode layer 43 and the n + type cathode layer 33 'and the p + type anode layer 43 toward the n + type cathode layer 33'. A depletion layer that extends is generated. When the gate electrode 48 is connected to the emitter electrode 42 in this state, similar to the first to third embodiments,
A p-type inversion layer is induced around the groove 46. For this reason,
From the pn junction between the p + -type anode layer 43 and the n − -type base layer 31, a part of the electric field generated toward the n + -type cathode layer 33 ′, that is, toward the end of the chip, is applied to the insulating film 47 in the groove 46. In the same manner as in the first to third embodiments, the equipotential lines become “dense” in the insulating film 47 formed in the groove 46. Thereby, the electric field in the n − -type base layer 31 is reduced.

Further, similarly to the third embodiment, the groove 46 is formed.
Therefore, the corner portion can be eliminated from the pn junction between the p + -type anode layer 43 and the n − -type base layer 31, or the concentration of the electric field can be reduced even if there is a corner portion. Thereby, avalanche breakdown can hardly occur.

Therefore, in the fourth embodiment, similarly to the third embodiment, the IGB with the free wheel diode is provided.
The withstand voltage of the T product is improved, and if the chip size is the same as the conventional product, the withstand voltage can be further increased. If the withstand voltage is the same as the conventional product, the chip size can be further reduced.

The fourth embodiment can be combined with the third embodiment. When combined in this manner, the n + type cathode layer 33 'is formed in a frame shape when viewed from above. The n + -type cathode layer 33 connects the frame-shaped n + -type cathode layers 33 ′ with each other to form a linear shape.
Alternatively, the n @ + -type cathode layers 33 'are connected to each other to form a lattice. The groove 46 is formed in a ring shape in a region surrounded by the n + -type cathode layers 33 and 33 '. A plurality of the annular grooves 46 are formed in the chip,
Are formed in, for example, each of a plurality of regions surrounded by the groove 46 formed in an annular shape. The p + -type anode layer 43 of the free wheel diode is formed, for example, in an annular shape between the region where the IGBT is formed and the groove 46.

As described in the third embodiment, the IGBT with the freewheeling diode is, for example, 100 V
It is used in a circuit for a high power application to which the above reverse bias is applied, and is used, for example, as a switching element.

[Fifth Embodiment] The fifth embodiment is a modification of the third embodiment or the fourth embodiment, in which the anode electrode of the freewheel diode is shared with the emitter electrode of the IGBT. It is.

FIG. 12 is a sectional view of an IGBT with a free wheel diode according to a fifth embodiment of the present invention. This figure 1
The cross section shown in FIG. 2 corresponds to, for example, a cross section shown in a frame VIII in FIG. 7 or a frame XI in FIG.

As shown in FIG. 12, the p-type base layer 32
Are formed not only between the trenches 37 but also between the trenches 37 and the grooves 46. Thereby, the surface of the p-type base layer 32 is exposed between the trench 37 and the groove 46. An n + -type emitter layer 40 is formed on the exposed p-type base layer 32. n + type emitter layer 40
A p + -type anode layer 43 ′ penetrating therethrough and reaching the p-type base layer 32 is formed on the groove 46 side. The emitter electrode 42 'is electrically connected to each of the n + type emitter layer 40 and the p + type anode layer 43'.

The p + -type anode layer 43 ′ is very similar to the p + -type layer 41 formed in the region between the trenches 37, but has a different concentration, for example. For example, the concentration of the p + -type layer 41 is set to achieve ohmic contact with the emitter electrode 42, while the p + -type anode layer 43 ′ achieves ohmic contact with the emitter electrode 42, The concentration is set to match the characteristics required for the reflux diode.

In the fifth embodiment, the third and fourth embodiments
Similarly to the embodiment, if the chip size is the same as the conventional one, it is possible to obtain an IGBT product with a freewheeling diode with a higher withstand voltage, and if the withstand voltage is the same as the conventional one, with a freewheeling diode with a smaller chip size. IGBT products can be obtained.

Further, in the fifth embodiment, the anode electrode of the freewheeling diode is shared with the emitter electrode of the IGBT, so that there is an advantage that the chip size can be reduced as compared with the third embodiment or the fourth embodiment. Obtainable.

Sixth Embodiment In the first to fifth embodiments, the p + -type anode layers (2, 43, 43 ') and n +
When the gate electrode (8, 48) is connected to the anode electrode in a state where the + -type cathode layer (4, 33, 33 ') is reverse-biased, the electric field in the n- type layer 1 or the n- type layer 31 is reduced. Explained what you can do.

In the sixth embodiment, the gate electrodes (8, 4
8) Regarding an example of applying another voltage to. Hereinafter, an example of applying another voltage to the gate electrodes (8, 48) according to the sixth embodiment of the present invention will be described with a horizontal diode as an example. The sixth embodiment aims particularly at reducing the “ON resistance”.

FIG. 13 is a diagram showing a voltage application example according to the sixth embodiment of the present invention. As shown in FIG. 13, when a forward bias is applied between the anode electrode 3 and the cathode electrode 5 of the diode to cause a current to flow from the p + -type anode layer 2 to the n − -type layer 1, the potential of the gate electrode 8 is reduced. Is lower than the potential applied to the cathode electrode 5 to form a p-type inversion layer 61 along the groove 6 in the n − -type layer 1 and
This p-type inversion layer 61 is brought into electrical contact with the p + -type anode layer 2. As a result, the effective area of the p + -type anode layer 2 increases, and the contact area between the p + -type anode layer 2 and the n − -type layer 1 increases. By increasing the contact area, the efficiency of injection of p-type carriers, that is, holes, from the p + -type anode layer 2 to the n − -type layer 1 is improved. p + type anode layer 2 to n
When the efficiency of injecting holes into the n-type layer 1 is improved, the injection of holes from the p @ + type anode layer 2 into the n @-type layer 1 is promoted, and the density of holes in the n @-type layer 1 is increased. Can be reduced.

In the sixth embodiment, when a current is caused to flow from the p + type anode layer 2 to the n − type layer 1,
p-type inversion layer 61 electrically contacting p @ + -type anode layer 2
Is generated along the groove 6, the "on resistance" of the diode can be reduced. By combining such a voltage application example with the first to fifth embodiments, it is possible to reduce the “ON resistance” of the product without impairing the effects of the first to fifth embodiments.

[Seventh Embodiment] The seventh embodiment relates to an example of applying another voltage to the gate electrode as in the sixth embodiment.

FIG. 14 is a diagram showing a voltage application example according to the seventh embodiment of the present invention. As shown in FIG. 14, when a current is caused to flow from the p + -type anode layer 2 to the n − -type layer 1, a p-type inversion layer 61 that is in electrical contact with the p + -type anode layer 2 is formed in the groove 6. In order for the potential to be generated along, the potential of the gate electrode 8 may be lower than the potential applied to the anode electrode 3.

In the seventh embodiment, the same effects as in the sixth embodiment can be obtained.
[Eighth Embodiment] The eighth embodiment relates to an example of applying another voltage to the gate electrode for the purpose of reducing the "reverse recovery loss".

FIG. 15 is a diagram showing an example of voltage application according to the eighth embodiment of the present invention. As shown in FIG. 15, the diode is switched from a forward bias state between the anode electrode 3 and the cathode electrode 5 to a reverse bias state, and p +
Immediately before the current substantially does not flow from the mold anode layer 2 to the n − -type layer 1, the potential of the gate electrode 8 is made equal to the potential applied to the cathode electrode 5. This allows
For example, the p-type inversion layer 61 formed along the groove 6 in the n- type layer 1 disappears, the effective area of the p + type anode layer 2 decreases, and the p + type anode layer 2 and the n− type The contact area with layer 1 is reduced. By reducing the contact area, the efficiency of injection of p-type carriers, that is, holes, from the p + -type anode layer 2 to the n − -type layer 1 decreases. Therefore, the injection of holes from the p + -type anode layer 2 into the n − -type layer 1 is suppressed, the density of holes in the n − -type layer 1 is reduced, and the “reverse recovery loss” of the diode can be reduced. it can.

In the eighth embodiment, the current flows from the p + -type anode layer 2 to the n − -type layer 1, for example, along the trench 6 immediately before the current is not substantially allowed to flow. The “reverse recovery loss” of the diode can be reduced by eliminating the p-type inversion layer 61 that is in electrical contact with the p + -type anode layer 2 that has occurred. By combining such a voltage application example with the first to fifth embodiments, the "reverse recovery loss" of the product can be reduced without impairing the effects of the first to fifth embodiments. .

Of course, the eighth embodiment can be used together with the sixth and seventh embodiments. Ninth Embodiment The ninth embodiment relates to an example of applying another voltage to the gate electrode as in the ninth embodiment.

FIG. 16 is a diagram showing a voltage application example according to the ninth embodiment of the present invention. As shown in FIG.
In the state where a current is flowing from the mold anode layer 2 to the n − -type layer 1, immediately before the current is substantially prevented from flowing, for example, the groove 6
In order to eliminate the p-type inversion layer 61 that is in electrical contact with the p + -type anode layer 2 that has been generated along with the gate electrode 8, the potential of the gate electrode 8 is made equal to the potential applied to the anode electrode 3. You may do it.

In the ninth embodiment, the same effects as in the eighth embodiment can be obtained. Of course, the ninth embodiment can be used together with the sixth and seventh embodiments.

In order to eliminate the p-type inversion layer 61 as in the eighth and ninth embodiments, the potential of the gate electrode 8 must be higher than the potential of the cathode electrode 5 or lower than the potential of the anode electrode 3. May be increased.

[Tenth Embodiment] The tenth embodiment relates to a specified example of the thickness of the insulating film 7 formed in the groove 6.
Hereinafter, a prescribed example of the film thickness according to the tenth embodiment of the present invention will be described using a lateral diode as an example.

FIG. 17 is a diagram showing the relationship between the thickness of the insulating film 7 and the withstand voltage of the lateral diode according to the tenth embodiment of the present invention. As shown in FIG. 17, when the thickness of the insulating film 7 is increased, the breakdown voltage of the diode increases. This is because the electric field that the insulating film 7 bears increases as the thickness of the insulating film 7 increases. For example, when the insulating film 7 is made of silicon dioxide, its thickness is 0.5 μm and about 100 V
Although the above breakdown voltage can be ensured, when the thickness is increased to 2.0 μm, the breakdown voltage can be improved to about 180 V.

[Eleventh Embodiment] As described in the tenth embodiment, for example, in order to set the withstand voltage to 200 V, the insulating film 7 needs to have a thickness of 2.0 μm or more.

The eleventh embodiment intends to provide a structure capable of improving the breakdown voltage even if the thickness of the insulating film 7 is reduced. Hereinafter, an eleventh embodiment of the present invention will be described using a vertical diode as an example.

FIG. 18 is a sectional view of a vertical diode according to the eleventh embodiment of the present invention. The cross section shown in FIG. 18 corresponds to, for example, the cross section shown in a frame V in FIG. As shown in FIG. 18, at least the double groove 6-1;
6-2 are formed between the p + -type anode layer 2 and the n + -type cathode layer 4, respectively. A p @ + -type guard ring 71 of a conductivity type opposite to that of the n @--type layer 1 is formed between the double grooves 6-1 and 6-2. A guard ring electrode 72 is electrically connected to the p + -type guard ring 71. The guard ring electrode 72 is electrically connected to the gate electrode 8-2 formed in the groove 6-2 on the n + type cathode layer 4 side. Guard ring electrode 72 and gate electrode 8-2 are formed in an electrically floating state.

Next, the principle will be described. When the thickness of the insulating film 7 is reduced, the effect of relaxing the electric field in the n − -type layer 1 is reduced.
The pn junction between the + type anode layer 2 and the n − type layer 1, that is, the electric field at the corner of the main junction becomes relatively strong. However, even if the electric field at this corner becomes strong, the depletion layer generated at the main junction punches through the p + guard ring 71 before the pn junction at this corner undergoes avalanche breakdown. As a result of the punch-through, the electric field at the corner part is once weakened, and avalanche breakdown at this corner part is avoided. In addition, as a result of the punch-through, the potential of the gate electrode 8-2 becomes a potential close to the potential of the anode electrode 3. When the potential of the gate electrode 8-2 becomes a potential close to the potential of the anode electrode 3, similarly to the insulating film 7-1 formed in the groove 6-1, the insulating film 7- formed in the groove 6-2. 2 makes the equipotential lines in the n − -type layer 1 between the groove 6-2 and the n + -type cathode layer 4 “sparse” and reduces the electric field in this portion.

As described above, according to the eleventh embodiment, even if the thickness of the insulating film 7 is reduced, the p + type anode layer 2 and the n −
Breakdown of the pn junction with the mold layer 1, that is, the main junction, can be suppressed.

The structure according to the eleventh embodiment is not limited to the vertical diode, but also to the horizontal diode described in the first embodiment and the IGBT with a free wheel diode described in the third and fourth embodiments. Can be applied to any of the above.

Further, the eleventh embodiment is described in the third and fourth embodiments.
With freewheel diode described according to the embodiment of the present invention
When applied to T, it goes without saying that the fifth embodiment in which the anode electrode of the freewheel diode is shared with the emitter electrode of the IGBT can be used together.

Further, the eleventh embodiment is similar to the sixth to ninth embodiments.
It is also possible to use the application example of the voltage described in the above embodiment together. As described above, the present invention has been described with reference to the first to eleventh embodiments. However, the present invention is not limited to these embodiments, and can be modified without departing from the gist thereof.

For example, in the above embodiment, the semiconductor substrate is n-
Although the mold layer 1 is of the n-type, it may be of the p-type. In this case, the anode electrode is deformed so as to be formed along the end of the chip, on the back surface of the chip as in the second embodiment, or in the middle of the chip as in the third embodiment. .

In the third and fourth embodiments, the freewheeling diode and the trench type IGBT are shown as on-chip examples. However, the IGBT is not limited to the trench type, but may be a planar type IGBT.

In the third and fourth embodiments, an example is shown in which the freewheel diode and the IGBT are on-chip.
The freewheel diode is a power semiconductor element other than an IGBT,
For example, a double diffusion type MOSFET (power MOSFET)
T) etc. may be used on-chip.

[0087]

As described above, according to the present invention,
The breakdown voltage can be increased without increasing the chip size,
Alternatively, it is possible to provide a power semiconductor device capable of reducing a chip size without reducing a withstand voltage.

[Brief description of the drawings]

FIG. 1A is a plan view of a lateral diode according to a first embodiment of the present invention, and FIG.
Sectional drawing which follows the B-IB line.

FIG. 2 is an enlarged view of a frame II in FIG. 1 (B).

FIG. 3A is a diagram showing a potential distribution of a conventional lateral diode, and FIG. 3B is a diagram showing a potential distribution of a lateral diode according to the first embodiment of the present invention.

FIG. 4 (A) is a plan view of a vertical diode according to a second embodiment of the present invention, and FIG. 4 (B) is an IV in FIG. 4 (A).
Sectional drawing which follows the B-IVB line.

FIG. 5 is an enlarged view inside a frame V in FIG. 4 (B).

FIG. 6 is a plan view of an IGBT with a free wheel diode according to a third embodiment of the present invention.

FIG. 7 is a sectional view taken along line VII-VII in FIG. 6;

FIG. 8 is an enlarged view in a frame VIII in FIG. 7;

FIG. 9 is a plan view of an IGBT with a free wheel diode according to a fourth embodiment of the present invention.

10A is a sectional view taken along line XA-XA in FIG. 9, FIG. 10B is a sectional view taken along line XB-XB in FIG. 9,

FIG. 11 is an enlarged view of a frame XI in FIG. 10 (A).

FIG. 12 is a cross-sectional view of an IGBT with a free wheel diode according to a fifth embodiment of the present invention.

FIG. 13 is a diagram showing a voltage application example according to a sixth embodiment of the present invention.

FIG. 14 is a diagram showing a voltage application example according to a seventh embodiment of the present invention.

FIG. 15 is a diagram showing a voltage application example according to an eighth embodiment of the present invention.

FIG. 16 is a diagram showing a voltage application example according to a ninth embodiment of the present invention.

FIG. 17 is a view showing the relationship between the thickness of an insulating film formed in a groove and the breakdown voltage of a lateral diode according to a tenth embodiment of the present invention.

FIG. 18 is a sectional view of a vertical diode according to an eleventh embodiment of the present invention.

19A is a plan view of a conventional lateral diode, and FIG. 19B is a cross-sectional view taken along line XIXB-XIXB in FIG. 19A.

[Explanation of symbols]

 1 ... n- type layer, 2 ... p + type anode layer, 3 ... anode electrode, 4, 4 '... n + type cathode layer, 5, 5' ... cathode electrode, 6, 6-1 and 6-2 ... groove , 7 ... insulating film, 8, 8-1, 8-2 ... gate electrode, 24 ... stopper layer, 31 ... n- type base layer, 32 ... p-type base layer 32, 33, 33 '... n + type cathode layer , 34, 34 '... cathode electrode, 35 ... p + type collector layer, 36 ... collector electrode, 37 ... groove (trench), 38 ... gate insulating film, 39 ... gate electrode, 40 ... n + type emitter layer, 41 ... p + -type layer, 42, 42 '... emitter electrode, 43, 43' ... p + -type anode layer, 44 ... anode electrode, 45 ... n + -type stopper layer, 46 ... groove, 47 ... insulating film, 48 ... gate electrode Reference numeral 61: p-type inversion layer 71: p + -type guard ring 72: guard ring electrode 101 ... Center area.

Claims (10)

[Claims] A semiconductor substrate of a first conductivity type having a main surface; and a main junction formed in the semiconductor substrate of the first conductivity type and terminating at the main surface with the semiconductor substrate. Second
A conductive semiconductor region, a groove formed on the main surface between the main junction and the end of the semiconductor substrate, an insulator formed in the groove, and formed in the groove, A power semiconductor device comprising: an electrode body that is insulated from the semiconductor substrate via an insulator. 2. The power semiconductor device according to claim 1, wherein said main junction is a junction between an anode layer and a cathode layer of a diode. 3. The semiconductor device according to claim 2, wherein an anode electrode electrically connected to the anode layer or a cathode electrode connected to the cathode layer is formed along an end of the semiconductor substrate. The power semiconductor device according to any one of the preceding claims. 4. A semiconductor substrate of a first conductivity type having a major surface, and a main junction formed in the semiconductor substrate of the first conductivity type and terminating at the major surface with the semiconductor substrate. Second
A conductive type semiconductor region; and a first conductive type semiconductor region electrically connected to the first conductive type semiconductor substrate.
And a second electrode electrically connected to the semiconductor region of the second conductivity type.
A groove formed on the main surface between the semiconductor substrate of the first conductivity type and the semiconductor region of the second conductivity type; an insulator formed in the groove; A power semiconductor device comprising: an electrode body formed on the semiconductor substrate and insulated from the semiconductor substrate via the insulator. 5. The power semiconductor device according to claim 4, wherein said main junction is a junction between an anode layer and a cathode layer of a diode. 6. The power semiconductor according to claim 2, wherein the diode is a freewheeling diode of a power semiconductor element formed on the semiconductor substrate. apparatus. 7. The power semiconductor device is an insulated gate bipolar transistor, and an anode electrode or a cathode electrode of the freewheeling diode is shared with an emitter electrode of the insulated gate bipolar transistor. Item 7. A power semiconductor device according to item 6. 8. When the anode layer and the cathode layer are forward-biased, the electrode body is electrically connected to the anode layer, and an inversion layer of the same conductivity type as the anode layer is formed along the groove. 8. The power semiconductor device according to claim 2, wherein the bias is applied to a potential generated by the power semiconductor device. 9. The method according to claim 8, wherein before switching the anode layer and the cathode layer from a forward bias to a reverse bias, the electrode body is biased to a potential at which the inversion layer disappears. Power semiconductor device. 10. The groove is provided at least doubly,
The power semiconductor device according to claim 1, wherein a guard ring having a conductivity type opposite to that of the main surface is provided between the double grooves.