JPH113132A - Power management device - Google Patents
Power management deviceInfo
- Publication number
- JPH113132A JPH113132A JP9153307A JP15330797A JPH113132A JP H113132 A JPH113132 A JP H113132A JP 9153307 A JP9153307 A JP 9153307A JP 15330797 A JP15330797 A JP 15330797A JP H113132 A JPH113132 A JP H113132A
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- frequency
- circuit
- low
- control
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P80/00—Climate change mitigation technologies for sector-wide applications
- Y02P80/10—Efficient use of energy, e.g. using compressed air or pressurized fluid as energy carrier
Landscapes
- Power Sources (AREA)
Abstract
(57)【要約】
【課題】パワーマネージメント制御において、周波数を
下げるかもしくは、ある一定期間クロックの動作をスト
ップさせるという周波数の制御だけで、低周波数への移
行に伴う低電圧制御を使用した低消費電力化を行う。
【解決手段】パワーマネージメント制御により周波数を
下げた際、低周波化に伴ってスイッチング時間を長くす
ることによりノイズの低減と温度上昇の制限等をはか
り、動作可能な範囲まで動作電圧を低く設定することで
更なる低所比電力化がはかれる。
(57) [Summary] In power management control, a low-frequency control using a low-voltage control accompanying a shift to a low frequency is performed only by controlling the frequency of lowering the frequency or stopping the operation of the clock for a certain period of time. Reduce power consumption. When a frequency is reduced by power management control, a switching time is lengthened with a reduction in frequency to reduce noise, limit a rise in temperature, and the like, and set an operating voltage low to an operable range. This will further reduce the specific power at low places.
Description
【0001】[0001]
【発明の属する技術分野】本発明は、パワーマネージメ
ント制御により動作周波数を下げた際、低周波化に伴っ
て電源電圧を低くするように制御することで、更なるパ
ワーマネージメント処理の制御をすることに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to controlling power management processing by lowering the power supply voltage as the operating frequency is lowered by power management control. About.
【0002】[0002]
【従来の技術】従来、パワーマネージメント制御により
動作周波数を変更するには、周波数を下げるかもしくは
ある一定期間クロックの動作をストップさせるという方
法を取る。これにより稼働率が下がり、低消費電力化が
はかれる。2. Description of the Related Art Conventionally, to change the operating frequency by power management control, a method of lowering the frequency or stopping the operation of the clock for a certain period is adopted. As a result, the operating rate is reduced, and power consumption is reduced.
【0003】この種の技術は、例えば特開平7−134
628号公報に開示される。[0003] This type of technology is disclosed in, for example, Japanese Patent Application Laid-Open No.
No. 628.
【0004】[0004]
【発明が解決しようとする課題】従来の技術では周波数
の制御だけで、低周波数への移行に伴う低電圧制御を使
用した低消費電力化は行われていない。In the prior art, low power consumption using low voltage control accompanying a shift to a low frequency is not performed only by controlling the frequency.
【0005】[0005]
【課題を解決するための手段】本発明では、従来のパワ
ーマネージメント制御により周波数を下げた際、低周波
化に伴ってスイッチング時間を長くすることによりノイ
ズの低減と温度上昇の制限等をはかり、動作可能な範囲
まで動作電圧を低く設定する。According to the present invention, when the frequency is reduced by the conventional power management control, the switching time is extended along with the lower frequency to reduce noise and limit the temperature rise. Set the operating voltage low to the operable range.
【0006】[0006]
【発明の実施の形態】本発明の実施例を詳細に説明す
る。図1は、周波数および電圧制御の概略図である。図
2は、定電圧回路の動作波形形態図である。図3は、定
電圧回路と制御されるべき各電圧の構成図である。図4
は、定電圧回路内での機能回路の電圧制御構成図であ
る。DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described in detail. FIG. 1 is a schematic diagram of frequency and voltage control. FIG. 2 is an operation waveform diagram of the constant voltage circuit. FIG. 3 is a configuration diagram of a constant voltage circuit and each voltage to be controlled. FIG.
FIG. 3 is a configuration diagram of voltage control of a functional circuit in a constant voltage circuit.
【0007】次に図1の周波数および電圧制御の方法に
ついて説明する。Next, a method of frequency and voltage control in FIG. 1 will be described.
【0008】定電圧回路FVC0は、電圧制御部PVC
1に供給される電圧Vinを電圧変換して出力された電
圧Voutを定電圧として使用し、一定周波数のパルス
信号を出力する。また、定電圧回路FVC0は、従来の
パワーマネージメント制御として、周波数制御部PFC
から周波数抑制信号Ctrl−Fを受けて周波数を低く
設定される。低周波数に抑制された定電圧回路FVC0
は、ノイズの低減と温度上昇の制限等により動作電圧に
余裕が生まれるため、本発明では動作可能な電圧値まで
下げるように、周波数制御部PFCから電圧制御部PV
C1に電圧抑制信号Ctrl−Vが送られる。さらに本
発明では、周波数抑制信号Ctrl−Fによる周波数値
の違いによって、電圧抑制信号Ctrl−Vによる電圧
抑制の割合を変更し、ある期間中周波数をOFFさせる
ときには電圧制御部PVC1からの電圧出力をストップ
させる。[0008] The constant voltage circuit FVC0 includes a voltage control unit PVC.
The voltage Vout supplied to 1 is converted into a voltage, and the output voltage Vout is used as a constant voltage to output a pulse signal of a constant frequency. Further, the constant voltage circuit FVC0 has a frequency control unit PFC as a conventional power management control.
The frequency is set low by receiving the frequency suppression signal Ctrl-F from. Constant voltage circuit FVC0 suppressed to low frequency
Since the operating voltage has a margin due to the reduction of noise and the restriction of temperature rise, the frequency control unit PFC controls the voltage control unit PV to reduce the voltage to an operable voltage value in the present invention.
The voltage suppression signal Ctrl-V is sent to C1. Further, in the present invention, the rate of voltage suppression by the voltage suppression signal Ctrl-V is changed by the difference in frequency value by the frequency suppression signal Ctrl-F, and when the frequency is turned off during a certain period, the voltage output from the voltage control unit PVC1 is changed. Stop.
【0009】次に図2の定電圧回路内における動作波形
制御について説明する。Next, operation waveform control in the constant voltage circuit of FIG. 2 will be described.
【0010】定電圧回路FVC0の通常の動作状態で
は、波形1のように振幅電圧VLT1、パルス幅PLS
1で動作しているとすると、周波数抑制信号Ctrl−
Fによって波形2のようにパルス幅が、PLS2(>P
LS1)と低周波動作となる。さらに定電圧回路FVC
0の波形は、電圧抑制信号Ctrl−Vによって波形3
のように振幅電圧が、VLT2(>VLT1)と低電圧
になる。In a normal operation state of the constant voltage circuit FVC0, as shown in a waveform 1, an amplitude voltage VLT1 and a pulse width PLS
1, the frequency suppression signal Ctrl-
The pulse width of PLS2 (> P
LS1) and low frequency operation. Furthermore, constant voltage circuit FVC
The waveform of 0 is the waveform 3 by the voltage suppression signal Ctrl-V.
, The amplitude voltage becomes as low as VLT2 (> VLT1).
【0011】スイッチング時間はdV/dtで表される
電圧の時間変化量の傾きを示すので、図2において波形
1から波形2に移行する際、ディレイ制御によって周波
数を制御した場合、電圧が変化する時間が長くなりパル
ス波形の傾きが緩和され、スイッチング時間が長くな
る。Since the switching time indicates the slope of the amount of time change of the voltage expressed by dV / dt, the voltage changes when the frequency is controlled by delay control when transitioning from waveform 1 to waveform 2 in FIG. The time becomes longer, the inclination of the pulse waveform is reduced, and the switching time becomes longer.
【0012】また、波形2から波形3に移行する際、電
圧の変化量が小さくなるので、更に傾きが緩和され、ス
イッチング時間は長くなり、低電圧で動作させても誤動
作の可能性が低減する。Further, when transitioning from waveform 2 to waveform 3, the amount of change in voltage is reduced, so that the slope is further alleviated, the switching time is lengthened, and the possibility of erroneous operation is reduced even when operated at a low voltage. .
【0013】次に図3の各定電圧回路と電圧の構成及び
制御について説明する。Next, the configuration and control of each constant voltage circuit and voltage shown in FIG. 3 will be described.
【0014】電圧Vinが供給された電圧制御部PVC
1から各定電圧回路に、それぞれ定常時に同電圧の電圧
VoutC1,VOutC2,VoutC3及び異電圧
の電圧VoutA,VoutBが電圧変換されて出力さ
れる。各電圧は、電圧抑制信号Ctrl−Vのパターン
により抑制を受けるかどうか、また、どの程度の抑制を
受けるのかを電圧制御部PVC1から設定される。The voltage control unit PVC supplied with the voltage Vin
1 to each constant voltage circuit, the voltages VoutC1, VOutC2, VoutC3 of the same voltage and the voltages VoutA, VoutB of different voltages are converted and output in a steady state. Each voltage is set by the voltage control unit PVC1 as to whether or not to be suppressed by the pattern of the voltage suppression signal Ctrl-V and to what extent the voltage is to be suppressed.
【0015】通常は、電圧の異なる回路(例えばFVC
1とFVC2とそれ以外)を分離するために用いる電圧
制御部PVC1を本発明では、電圧の抑制の仕方あるい
は抑制する電圧の量が異なる定電圧回路(たとえばFV
C3とFVC4とFVC5)においても回路を分離して
いる。Usually, circuits having different voltages (for example, FVC
In the present invention, the voltage control unit PVC1 used to separate the voltage control circuit 1 from the voltage control circuit FVC2 and the voltage control circuit FVC2 is separated from each other by a constant voltage circuit (for example, FV2) having different voltage suppression methods or different voltage suppression amounts.
C3, FVC4 and FVC5) also separate the circuit.
【0016】次に図4の定電圧回路内での機能回路の電
圧制御について説明する。Next, voltage control of a functional circuit in the constant voltage circuit of FIG. 4 will be described.
【0017】各機能回路CirAおよびCirBは、定
電圧回路(例えば図2のFVC2)内の一部で、同じ定
電圧回路内に存在する電圧制御回路PVC2およびPV
C3によって電圧を抑制される。電圧制御回路PVC2
およびPVC3は、定電圧回路に供給されている電圧と
同様に供給を受け、電圧抑制信号Ctrl−Vによって
各機能回路CirAおよびCirBへの供給電圧V1お
よびV2を抑制する。定電圧回路自体が電圧の抑制を受
ける以上に機能回路CirAおよびCirBが電圧抑制
されることになる。Each of the functional circuits CirA and CirB is a part of a constant voltage circuit (for example, FVC2 in FIG. 2) and includes voltage control circuits PVC2 and PV2 existing in the same constant voltage circuit.
The voltage is suppressed by C3. Voltage control circuit PVC2
And PVC3 are supplied in the same manner as the voltage supplied to the constant voltage circuit, and suppress the supply voltages V1 and V2 to the functional circuits CirA and CirB by the voltage suppression signal Ctrl-V. The function circuits CirA and CirB are suppressed in voltage more than the constant voltage circuit itself is suppressed in voltage.
【0018】[0018]
【発明の効果】本発明によれば、動作周波数を低くした
際、動作電圧も低くすることにより、更なる低消費電力
化が行える。According to the present invention, the power consumption can be further reduced by lowering the operating voltage when the operating frequency is lowered.
【0019】例えば、動作周波数を50%、動作電圧を
90%に設定した際、消費電力は以下の式により、約4
0%にすることができる。For example, when the operating frequency is set to 50% and the operating voltage is set to 90%, the power consumption becomes about 4 by the following equation.
It can be 0%.
【0020】P=CV2fα (ただし、P:消費電力、C:静電容量、V:電圧、
f:動作周波数、α:活性化率)P = CV 2 fα (where P: power consumption, C: capacitance, V: voltage,
f: operating frequency, α: activation rate)
【図1】周波数および電圧制御概略図FIG. 1 is a schematic diagram of frequency and voltage control.
【図2】定電圧回路の動作波形形態図FIG. 2 is an operation waveform diagram of a constant voltage circuit.
【図3】定電圧回路の制御電圧の構成図FIG. 3 is a configuration diagram of a control voltage of a constant voltage circuit.
【図4】定電圧回路内の機能回路の電圧制御図FIG. 4 is a voltage control diagram of a functional circuit in a constant voltage circuit.
Vin…電圧制御部に供給される電圧、Vout…電圧
制御部で変換され定電圧回路に供給される電圧、 P
VC1〜PVC3…電圧変換制御を行う電圧制御部、
PFC…周波数制御部、 Ctrl−V…電圧制御部
の電圧変換量を変更する電圧抑制信号、Ctrl−F…
定電圧回路の動作周波数を変更する周波数抑制信号、
FVC0〜FVC5…定電圧回路、VLT1〜VLT
2…SMl不正処理、 PLS1〜PLS2…lrキ
ー装置、VoutA,VoutB,VoutC1〜Vo
utC3…定電圧回路への供給電圧、 V1〜V2…機
能回路への供給電圧。Vin: voltage supplied to the voltage control unit, Vout: voltage converted by the voltage control unit and supplied to the constant voltage circuit, P
VC1 to PVC3: voltage control units for performing voltage conversion control;
PFC: Frequency control unit, Ctrl-V: Voltage suppression signal for changing the voltage conversion amount of the voltage control unit, Ctrl-F:
A frequency suppression signal that changes the operating frequency of the constant voltage circuit,
FVC0 to FVC5 ... constant voltage circuit, VLT1 to VLT
2 ... SMl illegal processing, PLS1 to PLS2 ... lr key device, VoutA, VoutB, VoutC1 to Vo
utC3: Supply voltage to constant voltage circuit, V1 to V2: Supply voltage to functional circuit.
Claims (1)
ス出力回路と、前記所定の周波数のパルス周波数を下げ
る信号を出力する低周波動作移行回路と、前記低周波移
行指示回路回路低周波動作へ移行したことに応じて前記
パルス出力回路から出力するパルスの出力電圧を低下さ
せる電圧制御手段を備えたことを特徴とするパワーマネ
ージメント装置。1. A pulse output circuit for outputting a pulse signal of a predetermined frequency, a low frequency operation transition circuit for outputting a signal for lowering the pulse frequency of the predetermined frequency, and a low frequency transition instruction circuit circuit for low frequency operation A power management device comprising voltage control means for reducing an output voltage of a pulse output from the pulse output circuit in accordance with the shift.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9153307A JPH113132A (en) | 1997-06-11 | 1997-06-11 | Power management device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9153307A JPH113132A (en) | 1997-06-11 | 1997-06-11 | Power management device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH113132A true JPH113132A (en) | 1999-01-06 |
Family
ID=15559629
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9153307A Pending JPH113132A (en) | 1997-06-11 | 1997-06-11 | Power management device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH113132A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002140130A (en) * | 2000-08-03 | 2002-05-17 | Internatl Business Mach Corp <Ibm> | Method and device for synchronizing clock modulation with electric power source modulation in spread spectrum clock system |
| US6774713B2 (en) | 2002-07-30 | 2004-08-10 | Renesas Technology Corp. | Circuit for producing a reference voltage for transistors set to a standby state |
-
1997
- 1997-06-11 JP JP9153307A patent/JPH113132A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002140130A (en) * | 2000-08-03 | 2002-05-17 | Internatl Business Mach Corp <Ibm> | Method and device for synchronizing clock modulation with electric power source modulation in spread spectrum clock system |
| US6774713B2 (en) | 2002-07-30 | 2004-08-10 | Renesas Technology Corp. | Circuit for producing a reference voltage for transistors set to a standby state |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5757173A (en) | Semi-soft switching and precedent switching in synchronous power supply controllers | |
| CN100571001C (en) | switching regulator | |
| TWI472132B (en) | Constant on-time switching converters with sleep mode and control methods thereof | |
| CN101594056B (en) | DC-to-DC converter and method thereof | |
| CN201750340U (en) | Switching power supply with fast transient response | |
| JP7251351B2 (en) | Gate drive and power converter | |
| JP2003079131A (en) | Drive control device, power conversion device, control method of power conversion device, and method of using power conversion device | |
| US9048863B2 (en) | Pulse density digital-to-analog converter with slope compensation function | |
| TWI399022B (en) | A heterodyne dual slope frequency feedback control circuit, control method and the power supply system having the same control circuit | |
| JPH09219637A5 (en) | ||
| CN100446392C (en) | A controller of switching regulated power supply with pulse intercycle modulation | |
| CN120433589A (en) | COT Buck Converter | |
| US6792042B1 (en) | Pulse width modulation control system | |
| JPH113132A (en) | Power management device | |
| CN102280908B (en) | Frequency Generation Mode with Heterodyne Slope for Light-to-Heavy Load Switching of Power Supplies | |
| US20230056382A1 (en) | Clock sync input dropout protection | |
| CN110572035B (en) | Floating gate width self-adaptive switching logic circuit applied to PWM DC/DC | |
| KR20070025864A (en) | Computer system and its power supply method | |
| JP6736344B2 (en) | Slew rate control device and slew rate control method | |
| CN117318479B (en) | Ultralow-power-consumption step-down DC-DC converter applicable to FLTR | |
| JPH08294269A (en) | Dc-dc converter | |
| JP2005057988A (en) | Control circuit of pulse-width modulation dc-dc converter and its method | |
| JPH04347535A (en) | Power supply system | |
| WO2019182511A1 (en) | Comparator circuit arrangement and method of forming the same | |
| JP2812114B2 (en) | SCSI controller |