JPH1131665A - Method for manufacturing semiconductor integrated circuit device - Google Patents

Abstract

[PROBLEMS] To form a shallow junction semiconductor region having a high impurity concentration and a steep impurity concentration distribution. SOLUTION: After an ion implantation process (step 100) for forming a shallow junction semiconductor region on a semiconductor substrate 1,
Immediately before the heat treatment for impurity activation (step 103), a thin cap film 2 is formed to prevent outward diffusion (step 1).
02).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a technology for manufacturing a semiconductor integrated circuit device, and more particularly to a technology effective when applied to a technology for forming a shallow junction in a semiconductor integrated circuit device.

[0002]

2. Description of the Related Art With the advance of fine processing technology in the manufacture of semiconductor integrated circuit devices, miniaturization of elements and the like has been promoted. The technology for forming shallow junctions not only promotes the miniaturization of devices and improves the degree of device integration, but also
It is an important technology as it can improve the element performance.

For example, in a bipolar transistor,
Forming a shallow base region while maintaining a high impurity concentration can realize a higher frequency and lower noise of the semiconductor integrated circuit device. In addition, MOS · FET (Metal Ox
Forming shallow source / drain regions in the ide Semiconductor Field Effect Transistor while maintaining a high impurity concentration can improve the current driving capability of the MOS-FET while suppressing the short channel effect.

In order to form a semiconductor region having such a shallow junction on a semiconductor substrate, it is generally formed by implanting impurity ions at low energy and then subjecting the semiconductor substrate to a short-time annealing treatment. It is.

A technique for forming such a shallow junction is described in, for example, Press Journal Inc., 1993
Published on 20th October, "Semiconductor World
uctor World) "on pages 54 to 59.

[0006]

However, the present inventor has found that the above-described technique for forming a semiconductor region having a shallow junction has the following problems.

That is, in the low energy ion implantation technique for forming a semiconductor region having a shallow junction, it is difficult to use an insulating film having a thickness usable as a cap for a heat treatment step in a normal process including cleaning. In the heat treatment step, since the surface of the semiconductor substrate is exposed, a part of the implanted ions is lost due to outward diffusion or the like, and a shallow junction having a target impurity concentration and a steep impurity concentration distribution is provided. However, there is a problem that it is difficult to form the semiconductor region.

It is an object of the present invention to provide a technique capable of forming a shallow junction semiconductor region having a steep impurity concentration distribution while maintaining a target impurity concentration.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0010]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

A method of manufacturing a semiconductor integrated circuit device according to the present invention includes the steps of: introducing a predetermined impurity into a semiconductor substrate to form a shallow junction semiconductor region in the semiconductor substrate;
Forming a cap film thinner than the impurity range immediately before or at the initial stage of the heat treatment for activating the predetermined impurity.

In the method for manufacturing a semiconductor integrated circuit device according to the present invention, the temperature for forming the thin cap is 750 ° C. or less.

In the method of manufacturing a semiconductor integrated circuit device according to the present invention, the thin cap has a thickness of 2 nm or less.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below in detail with reference to the drawings. (Note that components having the same functions in all drawings for describing the embodiments are denoted by the same reference numerals.) , And the repeated explanation is omitted).

(Embodiment 1) FIG. 1 is an explanatory view of a main part of a method of manufacturing a semiconductor integrated circuit device according to the present invention, and FIGS. FIG. 11 is a cross-sectional view of a main part during the process, FIG. 11 is a diagram showing an impurity concentration distribution of a semiconductor region constituting the semiconductor integrated circuit device of FIG. 10, and FIG. It is a graph which shows the relationship between the depth of a semiconductor substrate, and the impurity concentration in the case of the technique which is not formed.

The method of manufacturing a semiconductor integrated circuit device according to the present invention is an effective technique for forming a shallow junction semiconductor region on a semiconductor substrate. The main part will be described with reference to FIG.

First, predetermined impurities are introduced into the semiconductor substrate 1 by an ion implantation method or the like. The energy at this time is
In order to form a semiconductor region with a shallow junction, it is required that
Low energy of 1 KeV or less (step 100). The semiconductor substrate 1 of FIG. 1 is made of, for example, a single silicon (Si) single crystal of a predetermined conductivity type.

Subsequently, after performing a cleaning process on the semiconductor substrate 1 (Step 101), a thin cap film 2 is formed on the main surface of the semiconductor substrate 1 (Step 102).

The thin cap film 2 is made of, for example, silicon dioxide (SiO ₂ ) and formed by thermal oxidation at a low temperature of, for example, 750 ° C. or less, and has a thickness of an ion projection range (for example, about 5 nm). Thinner, for example 2 nm
Less than or equal.

The advantage of forming the thin cap film 2 at a low forming temperature is that a shallow junction semiconductor region which does not cause evaporation of implanted ions or ordinary thermal diffusion when forming the cap film 2 is formed. Thin cap film 2 at convenient temperature
Can be formed. Also, since the oxidation rate can be reduced, the thin cap film 2 can be formed with good control.

The advantage of making the cap film 2 extremely thin is that the cap film 2 can be easily formed at a low temperature as described above, and in addition, when the cap film 2 needs to be removed in the manufacturing process. That is, the cap film 2 can be easily removed by etching without substantially causing an adverse effect such as scraping of the element isolation film.

Thereafter, a heat treatment for activating the implanted ions is performed on the semiconductor substrate 1 (step 103). At this time, in the first embodiment, by forming the thin cap film 2 on the main surface of the semiconductor substrate 1, it is possible to prevent impurities implanted in the semiconductor substrate 1 from diffusing outward. , So while maintaining a high impurity concentration,
Further, a semiconductor region having a shallow junction with a steep impurity concentration distribution can be formed on the semiconductor substrate 1.

Next, in the first embodiment, an example in which the present invention is applied to, for example, a method of forming a bipolar transistor will be described with reference to FIGS.

FIG. 2 is a sectional view of a main part of the semiconductor substrate 1 during a manufacturing process of the semiconductor integrated circuit device according to the first embodiment.

The semiconductor substrate 1 is a so-called SOI (Silicon On Insulator) substrate in which a thin semiconductor layer 1c for element formation is provided on a supporting substrate 1a via an insulating layer 1b.

[0026] The supporting substrate 1a is a member for mainly ensuring the substrate strength, for example, p ^- consisting form of Si single crystal. The insulating layer 1b has a function of electrically separating the supporting substrate 1a and the thin semiconductor layer 1c.
It is made of iO ₂ or the like. The thin semiconductor layer 1c for element formation is
For example, it is made of an n-type Si single crystal.

A field insulating film 3a and a trench isolation 4 are formed in the element isolation region of the thin semiconductor layer 1c. The field insulating film 3a is made of, for example, SiO ₂ or the like, and is formed by a selective oxidation method or the like. Further, the groove-shaped separation portion 4 is formed, for example, with a SiO
_A separation film 4b of ₂ or the like is embedded and formed.

A field insulating film 3b is formed in the isolation region in the device of the thin semiconductor layer 1c. The field insulating film 3b is made of, for example, SiO _2, and is formed simultaneously with the field insulating film 3a in the element isolation region by a selective oxidation method or the like. Note that no groove-shaped separation portion is formed below the field insulating film 3b.

An insulating film 5 made of, for example, SiO ₂ is formed on the thin semiconductor layer 1c in the collector forming region surrounded by the field insulating films 3a and 3b. On the insulating film 5, an insulating film 6 made of, for example, SiO ₂ is formed in a pattern so as to cover the left and right field insulating films 3a and 3b.

First, on such a semiconductor substrate 1, FIG.
As shown in FIG. 1, after a polysilicon film 7 is deposited by a CVD method or the like, boron fluoride (BF ₂ ) or the like is introduced into a predetermined region of the polysilicon film 7 by an ion implantation method or the like. The resistance of the polysilicon film 7 is reduced.

Subsequently, by patterning the polysilicon film 7 by photolithography and etching, a conductor pattern 7a made of low-resistance polysilicon is formed as shown in FIG.

After that, on the semiconductor substrate 1, for example, SiO
After forming an insulating film 8 made of ₂ or the like by a CVD method or the like, the conductor pattern 7a and the insulating film 8 are patterned by a photolithography technique and an etching technique, as shown in FIG. Opening 9 such that upper surface of 1c is exposed
And a base lead electrode 7a1 made of low-resistance polysilicon is formed.

Next, in the first embodiment, in order to form an intrinsic base region having a shallow junction, for example, BF ₂
Is implanted into the upper portion of the thin semiconductor layer 1c through the opening 9 by ion implantation. The ion implantation energy at this time is, for example, about 3 KeV, and the dose is 1 × 10
It is about ¹⁴ cm ² .

Subsequently, for example, 6
The thin cap film described above is formed on the thin semiconductor substrate 1 exposed from the opening 9 by performing a dry oxidation treatment at about 00 ° C. for about 30 s.

Thereafter, for activation of the implanted ions, the semiconductor substrate 1 is heated to about 950.degree.
By performing a heat treatment of about s in a nitrogen gas atmosphere, a shallow junction intrinsic base region (shallow junction semiconductor region) 10 is formed as shown in FIG.

In the first embodiment, by forming the thin cap film prior to the heat treatment for activating the impurity ions, the impurities implanted in the thin semiconductor layer 1c are diffused outward. Can be formed, the intrinsic base region 10 having a shallow junction with a steep impurity concentration distribution can be formed while maintaining a high impurity concentration, and the intrinsic base resistance can be reduced by about half. ing.

At the same time, as shown in FIG. 7, the base extraction region 11 is formed on the outer periphery of the intrinsic base region 10 by thermally diffusing the p-type impurity of the base extraction electrode 7a1 into the semiconductor layer 1c.

Subsequently, on the semiconductor substrate 1, for example, SiO 2
After depositing an insulating film made of ₂ etc. by a CVD method or the like,
The sidewall 12 is formed on the inner wall surface of the opening 9 by etching back the insulating film.

Thereafter, a polysilicon film, for example, is deposited on the semiconductor substrate 1 by a CVD method or the like, and an arsenic (As) of an n-type impurity is
Are introduced by ion implantation or the like, and then the low-resistance polysilicon film is patterned by photolithography and etching techniques, as shown in FIG. 8, to form an emitter electrode 13 made of low-resistance polysilicon or the like. To form

Next, as shown in FIG.
On top, for example, BPSG (Boro Phospho Silicate Glass
) Is deposited by CVD or the like, and then heat-treated.

By this heat treatment, the surface of the interlayer insulating film 14a is made smooth and the n
The impurity is thermally diffused into the thin semiconductor layer 1c to form an emitter region 15 in the upper layer of the thin semiconductor layer 1c. Thus, the bipolar transistor 16 is formed on the semiconductor substrate 1.
To form

Subsequently, a connection hole 17 is formed by photolithography and etching so that the upper surface of the semiconductor layer 1c in the collector formation region, a part of the base extraction electrode 7a1, and a part of the emitter electrode 13 are exposed.

Thereafter, a conductor film made of, for example, an aluminum (Al) -Si-copper (Cu) alloy is deposited on the semiconductor substrate 1 by a sputtering method or the like, and the conductor film is patterned by a photolithography technique and an etching technique. By doing so, as shown in FIG.
A first layer wiring 18 is formed.

After that, on the semiconductor substrate 1, for example, SiO
_An interlayer insulating film 14b made of ₂ or the like is deposited by a CVD method or the like. The first layer wiring 18 is formed by the interlayer insulating film 14b.
Is coated.

FIG. 11 shows an impurity concentration distribution in the collector region, the base region and the emitter region of the bipolar transistor 16 formed as shown in FIG. Further, the depth of the semiconductor substrate and the impurity concentration (such as boron) in the case of the present embodiment and the technology of performing the heat treatment without the cap film.
Is shown in FIG.

In the first embodiment, the same junction depth (for example, 20 n
m, 3 × 10 ¹⁷ / cm ² ), the doping efficiency can be doubled and the layer resistance can be halved from, for example, 4 KΩ □ to 2 KΩ □. Also, for example, 1 × 10 ¹⁸ to
In the impurity concentration region of 1 × 10 ¹⁹ / cm ³ , the shape of the impurity concentration distribution can be sharpened.
Thus, the resistance of the intrinsic base region 10 of the bipolar transistor 16 (see FIG. 10) can be reduced by about half.

According to the first embodiment, the following effects can be obtained.

(1) By forming the thin cap film 2 on the thin semiconductor layer 1c prior to the heat treatment for activating the impurity ions, the impurities implanted in the thin semiconductor layer 1c diffuse outward. Therefore, it is possible to form a shallow junction intrinsic base region 10 having a steep impurity concentration distribution while maintaining a high impurity concentration, and to reduce the intrinsic base resistance by about half. It becomes possible.

(2) According to the above (1), it is possible to obtain the bipolar transistor 16 which can operate at high frequency and has low noise. The operation speed of the semiconductor integrated circuit device can be improved, and the operation reliability of the semiconductor integrated circuit device that operates at high speed can be ensured.

(3) By forming the thin cap film 2 at a low temperature, evaporation of implanted ions and normal thermal diffusion during the formation of the cap film 2 can be prevented, and a shallow junction semiconductor region is formed. It is possible to form the thin cap film 2 at a temperature that is convenient to perform.

(4) By setting the temperature for forming the thin cap film 2 at a low temperature, the oxidation rate can be reduced, so that the thin cap film 2 can be formed with good controllability.

(5) By making the cap film 2 extremely thin, not only can the above-described low-temperature formation of the cap film 2 be facilitated, but also if the cap film 2 needs to be removed in the manufacturing process. For example, the cap film 2 can be easily removed by etching with almost no adverse effect such as scraping of the element isolation film.

(Embodiment 2) FIGS. 13 to 19 are cross-sectional views of essential parts during a manufacturing process of a semiconductor integrated circuit device according to another embodiment of the present invention, and FIG. 20 shows the semiconductor integrated circuit device of FIG. FIG. 4 is a diagram showing an impurity concentration distribution of a semiconductor region to be constituted.

In the second embodiment, an example in which the present invention is applied to, for example, a method of forming a p-channel type MOS • FET will be described with reference to FIGS.

FIG. 13 is a sectional view showing a main part of a semiconductor integrated circuit device according to the second embodiment during a manufacturing process. The semiconductor substrate 1 is a so-called SOI (Silicon On Insulator) substrate in which a thin semiconductor layer 1c for element formation is provided on a supporting substrate 1a via an insulating layer 1b.

[0056] The supporting substrate 1a is a member for mainly ensuring the substrate strength, for example, p ^- consisting form of Si single crystal. The insulating layer 1b has a function of electrically separating the supporting substrate 1a and the thin semiconductor layer 1c.
It is made of iO ₂ or the like. The thin semiconductor layer 1c for element formation is
For example, it is made of an n-type Si single crystal.

A field insulating film 3a and a trench isolation 4 are formed in the element isolation region of the thin semiconductor layer 1c. The field insulating film 3a is made of, for example, SiO ₂ or the like, and is formed by a selective oxidation method or the like. Further, the groove-shaped separation portion 4 is formed, for example, with a SiO
_A separation film 4b of ₂ or the like is embedded and formed.

On the semiconductor substrate 1 surrounded by the field insulating films 3a, 3a, a gate electrode 19g is pattern-formed via a gate insulating film 19i. The gate insulating film 19i is made of, for example, SiO ₂ and is formed by a thermal oxidation method or the like.

The gate electrode 19g is formed by stacking a silicide film 19g2 such as tungsten silicide (WSi ₂ ) on a conductor film 19g1 made of low-resistance polysilicon.

The cap film 20 is formed on the gate electrode 19g. The cap film 20 is an insulating film having a function, such as to prevent peeling of the silicide film 19 g _2, for example made of SiO ₂ or the like.

First, in order to form a semiconductor region having a low impurity concentration in such a semiconductor substrate 1, as shown in FIG.
For example, boron as a p-type impurity is implanted by ion implantation or the like using the gate electrode 19g and the cap film 20 as a mask. At this time, the ion implantation energy is, for example, about 2 KeV, and the dose is, for example, 1 × 10 ¹⁴ / cm.
^{About 2} .

Subsequently, on the semiconductor substrate 1, for example, SiO 2
After depositing an insulating film made of ₂ etc. by a CVD method or the like,
By etching back the insulating film, the side wall 2 is formed on the side wall of the gate electrode 19g as shown in FIG.
Form one.

Thereafter, as shown in FIG. 16, the gate electrode 19g, the cap film 20 and the side walls 21 are used as a mask to form a p-type impurity such as BF
₂ is implanted by ion implantation or the like. The ion implantation energy at this time is, for example, about 5 KeV, and the dose is, for example, about 3 × 10 ¹⁵ / cm ² .

Next, for example, 6
The thin cap film described in the first embodiment is formed on the semiconductor layer 1c by performing a dry oxidation treatment at 00 ° C. for about 30 seconds.

Subsequently, in order to activate the impurity ions, for example, 950 in an atmosphere of nitrogen gas or the like.
The semiconductor substrate 1 is subjected to a heat treatment at about 10 ° C. for about 10 seconds.

As a result, as shown in FIG. 17, a low impurity concentration semiconductor region 19d1 and a high impurity concentration semiconductor region (shallow junction semiconductor region) are formed above the semiconductor layer 1c.
A semiconductor region 19d made of 19d2 is formed, and a p-channel type MOS.FET 19 is formed on the semiconductor substrate 1, for example. The semiconductor region 19d forms the source / drain region of the p-channel type MOSFET 19.

Thereafter, as shown in FIG.
After an interlayer insulating film 14a made of O ₂ or the like is deposited on the semiconductor substrate 1 by a CVD method or the like, a connection hole 17 such that the upper surface of the semiconductor region 19d is exposed in the interlayer insulating film 14a is formed by photolithography and dry etching. Perforated by technique.

Next, on the interlayer insulating film 14a, for example, A
After depositing a conductor film made of an l-Si-Cu alloy by a sputtering method, the conductor film is patterned by a photolithography technique, a dry etching technique, or the like, thereby forming a first layer wiring 1 as shown in FIG.
8 is formed.

Thereafter, for example, SiO 2 is formed on the semiconductor substrate 1.
After depositing the interlayer insulating film 14b of ₂ etc. by the CVD method or the like, the semiconductor integrated circuit device is completed through a normal wiring forming process of the semiconductor integrated circuit device.

FIG. 20 shows the impurity concentration distribution in the formation region of the p-channel type MOS • FET 19 formed as shown in FIG.

In the second embodiment, the same junction depth (for example, 15 n
m, 1 × 10 ¹⁸ / cm ³ ), the doping efficiency can be doubled and the layer resistance can be halved from, for example, 4 KΩ □ to 2 KΩ □. As a result, the series resistance of the source extension unit can be reduced by about half.

According to the second embodiment, the following effects can be obtained.

(1) By forming the thin cap film 2 on the thin semiconductor layer 1c prior to the heat treatment for activating the impurity ions, the impurities implanted in the thin semiconductor layer 1c diffuse outward. Therefore, the semiconductor region 9d having a shallow junction having a steep impurity concentration distribution can be formed while maintaining a high impurity concentration, and the resistance of the semiconductor region 9d can be reduced by about half. Becomes possible.

(2) According to the above (1), the p-channel type MO
The short channel effect of the S • FET 19 can be greatly reduced. Therefore, the p-channel type MOS · F
The miniaturization of the ET 19 can be promoted, the degree of element integration can be improved, and the reduction in the size of the semiconductor chip can be promoted.

(3) According to the above (1), the p-channel type MO
Since the current driving capability of the S-FET 19 can be improved, the operation speed of the p-channel type MOS-FET 19 can be improved.

(4) By forming the thin cap film 2 at a low temperature, evaporation of implanted ions and normal thermal diffusion during the formation of the cap film 2 can be prevented, and a shallow junction semiconductor region can be formed. It is possible to form the thin cap film 2 at a temperature that is convenient to perform.

(5) By setting the forming temperature of the thin cap film 2 at a low temperature, the oxidation rate can be reduced, so that the thin cap film 2 can be formed with good controllability.

(6) By making the cap film 2 extremely thin, not only can the above-described low-temperature formation of the cap film 2 be facilitated, but also if the cap film 2 needs to be removed in the manufacturing process. For example, the cap film 2 can be easily removed by etching with almost no adverse effect such as scraping of the element isolation film.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the first and second embodiments, and the present invention is not limited thereto. It goes without saying that various changes can be made.

For example, in the first and second embodiments,
The case where a thin cap film formed on a semiconductor substrate is formed by a thermal oxidation method or the like before the heat treatment for impurity activation has been described. However, the present invention is not limited to this, and various modifications can be made. For example, a CVD method, a chemical ( It may be formed by a liquid) oxidation method or a plasma oxidation method.

When the thin cap film is formed by the CVD method as described above, the thin cap film can be formed by a nitride film, and the configuration of the process flow can be simplified. In addition, when formed by a chemical oxidation method or a plasma oxidation method, it is possible to easily lower the temperature.

In Embodiments 1 and 2,
The case where the present invention is applied to the method of forming a p-type semiconductor region having a shallow junction has been described. However, the present invention is not limited to this. For example, a shallow junction using an n-type impurity such as phosphorus or arsenic (As) as a dopant is used. Can be applied to the formation of the n-type semiconductor region.

Therefore, the present invention provides an n-channel type MO.
The present invention is also applicable to a method for forming a source / drain region having a shallow junction of an S-FET. Further, the present invention can be applied to a method of forming a pnp bipolar transistor. Further, the present invention can be applied to a semiconductor integrated circuit device in which a MOS FET and a bipolar transistor are provided on the same semiconductor substrate. The present invention can be applied to a condition for forming a semiconductor region having a shallow junction.

[0084]

Advantageous effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.

(1) According to the method for manufacturing a semiconductor integrated circuit device of the present invention, a thin cap film is formed immediately before or at the initial stage of the heat treatment for activating the introduced impurity, thereby enabling the outside of the impurity to be formed. Since diffusion can be prevented by the thin cap film, it is possible to form a shallow junction semiconductor region having a steep impurity concentration distribution while maintaining a desired impurity concentration. Therefore,
The degree of element integration of the semiconductor integrated circuit device can be improved, and the element characteristics and element operation speed can be improved.

(2) According to the method of manufacturing a semiconductor integrated circuit device of the present invention, the temperature at which evaporation of introduced impurities and normal thermal diffusion do not occur is reduced by setting the formation temperature of the thin cap film to 750 ° C. or less. Thus, a thin cap film can be formed. Further, since the oxidation rate is low, a thin cap film made of an extremely thin oxide film can be formed with good controllability.

(3) According to the method of manufacturing a semiconductor integrated circuit device of the present invention, the thin cap film can be formed at a low temperature as described above by setting the thickness of the thin cap film to 2 nm or less. It becomes possible. Further, when the cap film needs to be removed in the manufacturing process, the removal process can be easily performed in a state where there is almost no trouble such as scraping of an oxide film for element isolation.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram of a main part in a method for manufacturing a semiconductor integrated circuit device of the present invention.

FIG. 2 is a fragmentary cross-sectional view of the semiconductor integrated circuit device according to the embodiment of the present invention during a manufacturing step thereof;

3 is a fragmentary cross-sectional view of the semiconductor integrated circuit device according to the embodiment of the present invention during a manufacturing step following that of FIG. 2;

FIG. 4 is a fragmentary cross-sectional view of the semiconductor integrated circuit device according to the embodiment of the present invention during the manufacturing step following FIG. 3;

5 is a fragmentary cross-sectional view of the semiconductor integrated circuit device according to the embodiment of the present invention during a manufacturing step following that of FIG. 4;

6 is a fragmentary cross-sectional view of the semiconductor integrated circuit device according to the embodiment of the present invention during a manufacturing step following that of FIG. 5;

FIG. 7 is a fragmentary cross-sectional view of the semiconductor integrated circuit device according to the embodiment of the present invention during the manufacturing step following FIG. 6;

8 is a fragmentary cross-sectional view of the semiconductor integrated circuit device according to the embodiment of the present invention during a manufacturing step following FIG. 7;

9 is a fragmentary cross-sectional view of the semiconductor integrated circuit device according to the embodiment of the present invention, during a manufacturing step following that of FIG. 8;

10 is a fragmentary cross-sectional view of the semiconductor integrated circuit device according to the embodiment of the present invention, during a manufacturing step following FIG. 9;

11 is an impurity concentration distribution diagram of a semiconductor region included in the semiconductor integrated circuit device of FIG.

FIG. 12 is a graph showing the relationship between the depth of a semiconductor substrate and the impurity concentration in the case of the present embodiment and in the case of a technique in which a cap film is not formed prior to the heat treatment for impurity activation.

FIG. 13 is a fragmentary cross-sectional view of a semiconductor integrated circuit device according to another embodiment of the present invention during a manufacturing step thereof;

14 is a fragmentary cross-sectional view of the semiconductor integrated circuit device according to another embodiment of the present invention during a manufacturing step following that of FIG. 13;

15 is a fragmentary cross-sectional view of the semiconductor integrated circuit device according to another embodiment of the present invention during a manufacturing step following FIG. 14;

16 is a fragmentary cross-sectional view of the semiconductor integrated circuit device according to another embodiment of the present invention during a manufacturing step following that of FIG. 15;

17 is a fragmentary cross-sectional view of the semiconductor integrated circuit device according to another embodiment of the present invention during a manufacturing step following FIG. 16;

18 is a fragmentary cross-sectional view of the semiconductor integrated circuit device according to another embodiment of the present invention during a manufacturing step following FIG. 17;

FIG. 19 is a fragmentary cross-sectional view of the semiconductor integrated circuit device according to another embodiment of the present invention during a manufacturing step following FIG. 18;

FIG. 20 is an impurity concentration distribution diagram of a semiconductor region included in the semiconductor integrated circuit device of FIG. 19;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 1a Supporting substrate 1b Insulating layer 1c Thin semiconductor layer 2 Thin cap film 3a Field insulating film 3b Field insulating film 4 Groove separating part 4a Separating groove 4b Separating film 5 Insulating film 6 Insulating film 7 Polysilicon film 7a Conductor pattern 7a1 Base lead electrode 8 Insulating film 9 Opening 10 Intrinsic base region (shallow junction semiconductor region) 11 Base lead region 12 Side wall 13 Emitter electrode 14 Interlayer insulating film 15 Emitter region 16 Bipolar transistor 17 Connection hole 18 First layer wiring 19 p Channel type MOS / FET 19i Gate insulating film 19g Gate electrode 19g1 Conductive film 19g2 Silicide film 19d Semiconductor region 19d1 Low impurity concentration semiconductor region 19d2 High impurity concentration semiconductor region (shallow junction semiconductor region) 20 Cap film 21 Side wall

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Mitsuharu Honda 2326 Imai, Ome-shi, Tokyo Inside the Device Development Center, Hitachi, Ltd. Hitachi RLS Engineering Co., Ltd.

Claims (6)

[Claims] A step of introducing a predetermined impurity into the semiconductor substrate so as to form a semiconductor region having a shallow junction in the semiconductor substrate; and a step of introducing an impurity immediately before or at an initial stage of a heat treatment for activating the predetermined impurity. Forming a thin cap film as compared to the range of the semiconductor integrated circuit device. 2. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein said semiconductor region having a shallow junction is a base region of a bipolar transistor. 3. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein said shallow junction semiconductor region is a source / drain region of a MIS transistor. 4. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein said predetermined impurity is ion-implanted at a low energy of 0.1 KeV or less per unit atom. A method for manufacturing a circuit device. 5. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein the forming temperature of the thin cap is 750 ° C. or less. 6. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein said thin cap has a thickness of 2 nm or less. .