JPH1132202A - Image processing apparatus and method - Google Patents

Abstract

(57) [Summary] [PROBLEMS] To enable a pattern suitable for applied image processing to be superimposed, to superimpose an appropriate pattern on an image after various types of image processing, and to reliably determine a pattern for specifying a device. In addition to making it possible, the image quality of the formed image is prevented from deteriorating. A selector (14) converts an image signal read from a CCD (105) into a digital CMY signal,
Binary output image processing (binary processing circuit 15 to density conversion circuit 18) or multi-level output image processing (masking / U
It is provided to one of the CR circuit 20 to the density conversion circuit 22).
Machine number pattern generation circuit 25 and pattern modulation control unit 26
Determines a superimposition pattern appropriate for the image processing selected by the selector 14, and generates a signal for forming the superimposition pattern. Comparator circuit 19,2
3 is a pattern modulation control unit 26 for forming a visible image.
Is used to superimpose a superimposition pattern on the image signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an image processing apparatus and method, and more particularly, to an image processing apparatus and method for performing image processing for forming a color image on a recording medium based on an input image.

[0002]

2. Description of the Related Art Conventionally, a color image forming apparatus includes various measures for preventing forgery of a specific document such as a bill or a securities. As one of the techniques, there is a method of superimposing a symbol peculiar to the image forming apparatus, which is difficult to visually recognize, on the image with a fixed modulation amount on the image in order to identify the used image forming apparatus.

According to this method, if securities are forged using the image forming apparatus, a symbol unique to the image forming apparatus is used by using a reading apparatus capable of extracting the forged product only in a specific wavelength range. (Pattern) can be read. For this reason, the image forming apparatus used for forgery can be specified, and it becomes an effective clue for tracking a forger.

[0004]

However, in the above-mentioned conventional example, if the image data input to the image forming apparatus has been subjected to image processing for adjusting the number of gradations, dot formation interval, sharpness, etc. in advance, Alternatively, when the image forming apparatus itself has a plurality of types of image processing circuits as described above, the pattern to be superimposed cannot support all types of image processing. Specifically, a symbol (pattern) unique to the image forming apparatus cannot be read,
Conversely, a problem may occur that the superimposed symbol is too conspicuous and is recognized as an abnormal image.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and in an image forming apparatus to which a plurality of types of image processing can be applied when forming a visible image, a predetermined pattern suitable for the applied image processing is superimposed. It is an object of the present invention to provide an image forming apparatus and a method thereof that enable the above.

[0006]

An image forming apparatus according to the present invention for achieving the above object has the following arrangement. That is, an image forming apparatus that forms a visible image based on an image signal, a determining unit that determines a superimposition pattern based on image processing applied to the image signal, and a superimposition determined by the determining unit. Generating means for generating a signal for forming a pattern; and superimposing means for superimposing the superimposed pattern on the image signal using a signal generated by the generating means in forming a visible image of the image signal. An image forming apparatus comprising:

According to another aspect of the present invention, there is provided an image forming method for forming a visible image based on an image signal. A determining step of determining a superimposed pattern based on the superimposed pattern; a generating step of generating a signal for forming the superimposed pattern determined in the determining step; and a signal generated in the generating step in the visible image formation of the image signal. And superimposing the superimposition pattern on the image signal using

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below in detail with reference to the accompanying drawings. In the following embodiment, an example of a copying machine (full-color image forming apparatus) is shown, but the present invention is not limited to this, and it is needless to say that the present invention can be applied to various other apparatuses. Further, in each device to which the present invention can be applied, specific documents such as banknotes and securities are targeted for counterfeit prevention.

First Embodiment Hereinafter, a first embodiment of the present invention will be described with reference to an electrophotographic full-color image forming apparatus. It is needless to say that the present invention can be applied not only to the electrophotographic system but also to various image forming systems such as a silver halide photographic system, a thermal transfer system, and a sublimation system.

FIG. 1 is a side sectional view schematically showing the internal structure of the full-color image forming apparatus according to the first embodiment.
In the figure, 1 is a polygon mirror, 2 is a mirror, 3Y
Represents a yellow developing device, 3M represents a magenta developing device, 3C represents a cyan developing device, 3BK represents a black developing device, 4 represents a photosensitive drum, 111 represents a transfer drum, 6 represents a recording material, 7 represents a fixing roller, 101 represents a document, and 102 represents a document. Platen glass, 103 is a light source, 104 is an optical lens, 105 is a CCD, 106 is A
/ D converter, 107 is an image processing unit, 108 is a laser light source, 109 is a charger, 110 is a cleaning blade, 111 is a transfer drum, and 112 is a transfer charger.

FIG. 2 is a flowchart for explaining an image recording operation of the full-color image forming apparatus according to the first embodiment. Hereinafter, a method of forming a color image according to the above configuration will be described with reference to FIGS.

Document 10 placed on platen glass 102
Illumination light from the light source 103 irradiated and reflected on
An image is formed on the CCD 105 by the optical lens 104 and converted into an image signal corresponding to the amount of received light. The image signal is converted into a digital value by the A / D converter 106 and subjected to image processing by the image processing unit 107.
Drive 08. The image processing unit 107 includes a ROM that stores a control program, a CPU that implements various controls based on the control program stored in the ROM,
The RAM includes a RAM that provides a work area necessary for the PU to perform various processes.

The laser light emitted from the laser light source 108 is reflected by the polygon mirror 1 and the mirror 2 and is irradiated on the photosensitive drum 4. The surface of the photosensitive drum 4 is previously cleaned by a cleaning blade 110 so that toner is not deposited thereon, and is uniformly charged by a charger 109.

First, the photosensitive drum 4 on which a latent image is formed by scanning with a laser beam based on an image signal of Y (yellow) rotates in the direction of the arrow shown in the drawing. Development is performed by the developing device 3Y. Further, the photosensitive drum 4 is rotated to adsorb the recording material 6 to the transfer drum 111 (Step S91), and the toner image formed on the photosensitive drum 4 is transferred onto the recording material 6 by the transfer charger 112 (Step S91). Step S92).

Next, after a latent image is formed and developed with an M (magenta) image signal, multiple transfer is performed onto the Y image on the recording material 6 under the position condition that the image registration is adjusted ( Step S93). Similarly, image formation and multiple transfer are performed for C and Bk (steps S94 and S95), and the transfer paper is separated from the transfer drum 111 (step S96).
The image is fixed by the fixing roller pair 7 (step S97). As described above, a color image print is completed.

In the process of forming an image as described above, the full-color image forming apparatus of this embodiment employs a CCD 105
For the image signal input from, one of binary processing suitable for outputting characters and the like and multivalued image processing suitable for outputting a gradation image can be selected and used. When forming a Y image, a pattern unique to the device is recorded in a superimposed manner. Hereinafter, the pattern superimposing process according to the present embodiment will be described.

FIG. 3 is a view for explaining an image processing procedure according to the first embodiment. In FIG. 3, the RGB (R
ed, Green, Blue) signals are obtained by the CCD 105. This RGB signal is an analog signal, and A / D
The signal is converted into a digital RGB signal by the converter 106. The configuration after the shading circuit 12 is a configuration in the image processing unit 107. Shading circuit 12
Corrects the obtained RGB signals in order to correct the sensitivity variation of the individual elements of the CCD 105. Modified RG
The B signal is converted by the LOG conversion circuit 13 into CMY (Cyan,
(Magenta, Yellow) signal.

Further, in the present image forming apparatus, a plurality of types of image processing circuits having different image signal characteristics are incorporated, and a selector circuit 14 for selecting a circuit according to which one is used is provided. ing.

Here, an image processing circuit (hereinafter referred to as an image processing circuit) having a resolution of an 8-bit signal (256 gradations) for forming a gradation image by area width reproduction by pulse width modulation based on the multi-valued information. And an image processing circuit for multi-value output) and an error diffusion method using an average density method, which converts the signal into binary values of 0 and 255 levels and reproduces the gradation by the number of binary image processing dots per unit area. Image processing circuits (hereinafter, image processing circuits for binary output).

The image processing for binary output can satisfactorily reproduce an image when the original is an image mainly composed of characters. on the other hand,
The image processing for multi-level output performs image reproduction by multi-level pulse width modulation, and can perform good image reproduction when the original image is an image centered on a gradation image.

The user can select one of these image processing circuits through the operation panel 201 of the full-color image forming apparatus.

When the user selects image processing for binary output via the operation panel 201 of the image forming apparatus, a signal to that effect is supplied to the selector 14, and the selector 14 selects a binary output image processing circuit. . As a result, the selector 14
Represents the CMY signal input from the LOG conversion circuit 13,
This is supplied to the binarization processing circuit 15 that executes the binarization processing using the above-described error diffusion method.

The CMY signal binarized by the binarization processing circuit 15 is input to a masking / UCR circuit 16 and converted into a color-matched CMYK signal. Further, the spatial filter circuit 16 arranges image signals in order to make the image clearer and smoother. Then, by passing through the density conversion circuit 18, density conversion correction according to the gradation characteristics of the printer is performed.

In the ROM 24, pattern information indicating an optimum pattern is registered for each image processing. The machine number pattern generation circuit 25 generates appropriate pattern information based on an image processing selection signal from the selector 14 (a signal indicating which of the binarized output image processing and the multi-level output image processing has been selected). From the ROM 24 and passed to the pattern modulation controller 26. For example, when the binarized output image processing is selected as described above, the dot pattern of FIG. 4 (hereinafter, also referred to as a unit dot) is selected. And
The pattern modulation control unit 26 converts the selected dot pattern into a Y (Yellow) image signal having the lowest visual resolution and a dot pattern group corresponding to the device number read from the ROM 24 (hereinafter, also referred to as a device number pattern). ) Is output.

After the full-color image is formed, the machine number pattern can be read by separating the yellow signal through a narrow band filter of 350 nm, and even if forgery is performed, it can be read by any machine (image forming apparatus). Can be identified.

The pattern shown in FIG. 4 will be described. FIG. 4 is a diagram showing an example of a dot pattern suitable for binarized output according to the first embodiment. In the case of a binary image, a dot pattern must be embedded between image data in which signals 0 and 255 are scattered. Therefore, it is necessary to increase the area of the dot pattern so that the embedded dot pattern can be read. Further, since the image data is a binary data image, the signal modulation amount of the dot pattern is not a data addition / subtraction, but a specific pixel is forcibly set to 0 and 255 as shown in the figure.
To ensure that it is legible. Pixels with no numbers indicate that no modulation is applied.

A comparator circuit 19 includes a superimposition signal for superimposing a pattern and CMY signals having passed through the density conversion circuit 18.
Input the K signal, superimpose the superimposed signal only on the Y signal,
The obtained CMYK signal is output to the pulse width modulation circuit 27. The pulse width modulation circuit 27 emits laser light corresponding to “0” and “255”, and forms a full-color image through the above-described image forming process.

Next, the case where the image processing for multi-value output, which emphasizes the gradation, is selected will be described. LOG conversion circuit 1
The CMY signal output from 3 is supplied to the masking / UCR circuit 20 by the selector 14. After that, it is supplied to a comparator circuit 23 through a spatial filter circuit 21 and a density conversion circuit 22. Machine number pattern generation circuit 25
Fetches information from the ROM 24 for forming a dot pattern (in this example, the dot pattern in FIG. 5) optimal for multi-value output image processing (in this example, multi-valued pulse width image processing), and performs pattern modulation. It is passed to the control unit 26. The pattern modulation control unit 26 controls the pattern modulation so that the machine number pattern supplied from the machine number pattern generation circuit 25 is formed by the selected dot pattern.

The comparator circuit 23 receives the input CM.
Of the YK signals, Y (Yell
ow) is superimposed on a device number pattern formed by the dot pattern of FIG. 5 on only the image signal. Pulse width modulation circuit 27
Forms a signal having a pulse width corresponding to a value of “0” to “255” according to the CMYK signal input through the comparator circuit 23.

The image data subjected to the pulse width modulation by the pulse width modulation circuit 27 is supplied to a laser diode driver 28.
To form an image.

FIG. 5 is a diagram showing an example of a dot pattern suitable for image data subjected to image processing for multi-value output.

Unlike the binary output dot pattern (FIG. 4), since it is multi-valued data, the modulation amount is added to or subtracted from image data. In FIG. 5, the places where “+ α” and “−α” are written are modulation locations, and it is desirable that “α” is optimized according to the performance of the image forming apparatus. The value of α is determined by, for example, the dot interval (resolution) of the toner. It is preferable to take a larger value of alpha as the resolution is lower (as the dot interval is larger).

The value of α is an environmental sensor (sensor for measuring temperature and humidity, provided in the image forming apparatus,
(Not shown), and may be variably controlled based on the detection value, or variably controlled based on the number of durable sheets. By doing so, it is possible to control the dot pattern so that it can be read more reliably and the pattern is less noticeable.

Further, even if the size of the dot pattern for a multi-valued image is smaller than that of a binary image, the dot pattern can be sufficiently read. If a pattern of the binary image processing is adopted, the dot pattern becomes noticeable and an abnormal image is formed. It looks like.

Next, the pattern adding method and the pattern adding circuit will be described in detail. [Dot Pattern Adding Method] First, an example of a pattern adding method in the present embodiment will be described. As described above, FIGS. 4 and 5 show an example of the dot pattern according to the first embodiment. In the present embodiment, one of these dot patterns is selected in accordance with the type of image processing, and a machine number pattern corresponding to the machine number is superimposed on the Y image using the selected dot pattern.

FIGS. 6 and 7 are views showing an example of the add-on line according to the first embodiment. The add-on line is a line including a dot pattern as shown in FIG. 4 or FIG. Therefore, the number of pixels of the add-on line in the sub-scanning direction is equal to the number of pixels of the dot pattern in the sub-scanning direction, and is 4 pixels when the dot pattern of FIG. 4 is employed and 2 pixels when the dot pattern of FIG. Becomes Hereinafter, the case where the dot pattern of FIG. 4 is used will be described as an example.

In FIG. 6, reference numeral 401 denotes an add-on line having a width of 4 pixels. Each of the dot patterns 401a to 401e is a dot pattern shown in FIG. The dot patterns 401a to 401e are arranged at a substantially constant period of d1 (for example, 128 pixels) in the main scanning direction. Further, in FIG. 7, reference numerals 501 to 510 denote add-on lines, for example, having a width of 4 pixels, and d2 in the sub-scanning direction.
(For example, 16 pixels). Although details will be described later, for example, one add-online indicates 4-bit information (0h to Fh), and the add-online 502
~ 509 Ad-Online is a set of 28
Bit additional information (device number) can be represented (4 bits × 7 = 28 because one of eight lines is a reference line)
bit). The add-on lines are repeatedly formed in the sub-scanning direction. For example, add-ons 501 and 509 shown in FIG. 7 represent the same information.

FIGS. 8 and 9 show an example of a method of expressing information by add-on-line. In FIG.
And 602 are add-on lines, which are adjacent in the sub-scanning direction. 601a, 601b and 602a are dot patterns. In order to prevent the adjacent dot patterns on the ad line from being prominently close to each other, the dot patterns on the adjacent ad line are set so as to have an interval of at least d3 (for example, 32 pixels) in the main scanning direction. .

The data represented by the dot pattern includes a dot pattern 602a and a dot pattern 601.
It is determined by the phase difference from a. FIG. 8 shows an example representing 4-bit information. In FIG. 8, the unit dot 602a represents data '2'. For example, if the unit dot 602a is at the leftmost end, data “0” is indicated, and if the unit dot 602a is at the rightmost end, data “F” is indicated.

In FIG. 9, among the set of add-on lines representing all additional information, FIG. 9A shows the first add-on line 0 and FIG. 9B shows the fourth add-on line 3. As shown in FIG. 9, dot patterns 702a to 702d are added to Line0 at intervals of d4 (for example, 16 pixels) on the right side of all of the original dot patterns 701a to 701d.
Dot patterns 705a to 705d are added at intervals of d5 (for example, 32 pixels) to the right of all of the original dot patterns 704a to 704d. The additional dot is a marker for clarifying the order of each ad online. Note that the reason why the markers are added to the two add-on lines is that the upper and lower sides in the sub-scanning direction can be determined even from the output image.

The addition of the dot pattern described above
Utilizing the fact that human eyes have a low discriminating ability with respect to a pattern drawn with Y toner, this is performed using only Y toner. Also, the dot spacing in the main scanning direction of the additional pattern,
The repetition interval of all additional information in the sub-scanning direction needs to be determined so that all information can be reliably added to a thin and uniform area where dots can be reliably identified in a symmetric specific document.

[Dot pattern addition circuit]
An example of a dot pattern adding circuit according to the embodiment will be described.

FIGS. 10 to 16 show the machine number pattern generation circuit 25, the pattern modulation control unit 26, and the comparator circuit 19.
FIG. 3 is a block diagram for explaining a configuration example of a pattern addition circuit configured from.

FIG. 10 is a diagram showing an example of a circuit configuration of the pattern modulation control section 26. Referring to FIG.
At 19, the main scanning synchronization signal HSYNC is counted, and at the main scanning counter 814, the pixel synchronization signal CLK is counted repeatedly with a 7-bit width, that is, 128 cycles. Gate circuit 8 connected to outputs Q1-Q3 of sub-scanning counter 819
20, according to a selection signal indicating the used image processing,
A signal which becomes “H” for four lines in every 16 lines in the sub-scanning direction (when image processing for binary output is selected), or becomes a high level (H) for two lines in every 16 lines in the sub-scanning direction. A signal (when multi-value output image processing is selected) is output. That is, the gate circuit 820 outputs an H signal during the scan line included in the add-on line, and the add-on enable signal (ADLI)
N).

FIG. 11 is a diagram illustrating the configuration of gate circuit 820. When the selection signal indicates that the image processing for binary output has been performed, the selector 820 c
Select the output of 20a. When the selection signal indicates that image processing for multi-level output has been performed, the AND gate 8
20b is selected and output. AND gate 820
a outputs H when both bit 2 (Q2) and bit 3 (Q3) of the sub-scanning counter 819 are H. That is, the output of the AND gate 820a is
It goes high for a period of four lines per line. on the other hand,
AND gate 890a goes high when both bit 2 (Q2) and bit 3 (Q3) of sub-scanning counter 819 are high and bit 1 (Q1) is low (L). That is, the output of the AND gate 820b becomes H for a period of two lines every 16 lines in the sub-scanning direction.

The gate 822 is connected to the gate circuit 820.
Output and the upper 3 bits (Q4 to Q4) of the sub-scanning counter 810.
Q6), and by taking the logical product of them, the enable signal LIN of the add-on line 0 is input.
E0 is output. Further, the gate 821 generates an enable signal LINE3 of the line 3 in the add-on line.
These signals LINE0 and LINE3 are used to embed a dot pattern indicating a marker as described with reference to FIG.

On the other hand, an initial value is loaded into the main scanning counter 814 by HSYNC, which will be described later in detail. The gates 815 to 817 receive the upper 4 bits (Q3 to Q6) of the main scanning counter 814 and the output signal of the gate circuit 890. FIG. 12 is a diagram illustrating a circuit configuration example of the gate circuit 890. As shown in FIG. 12, a gate circuit 890 includes an AND gate 890a and an OR gate 89.
0b, and becomes H in a section of a period (5 pixels) where Q0 to Q2 are 000 to 100.

Therefore, the output of AND gate 815 is 1
It becomes H only for a period of 5 pixels for every 28 pixels, and this is set as a dot enable signal. Also, AND gates 816 and 8
In addition to the upper 4 bits of the main scanning counter 814 and the signal from the gate circuit 890, the signal
0 and LINE3 are input. Therefore, the AND gates 816 and 817 output the enable signals for the marks of line 0 and line 3, respectively. These dot and mark enable signals are combined by an OR gate 818. Then, the output of the OR gate 818 and the output of the gate circuit 820 are ANDed by the AND gate 824 to provide a dot and mark enable signal which becomes H only at the dot overlap position on the add-on line.

FIG. 13 is a diagram conceptually showing the dot enable signal and the mark enable signal generated as described above. A scanning period of 4 lines (or 2 lines) becomes add-on line for every 16 sub-scan lines,
The 120th pixel to 12th for every 128 pixels in the add-on line
The dot enable signal is output during the period of the fourth pixel and five pixels (1300 in FIG. 13). Also, in the 0th add-on line (LINE0), a mark enable signal is output during the period of the eighth to twelfth pixels (1301 in FIG. 13) for every 128 pixels. Similarly, in the fourth add on-line (LINE3), 24
A mark enable signal is output during the period of the pixels 28 to 28 (1302 in FIG. 13).

The output signal of the AND gate 824 as described above is synchronized with the pixel synchronization signal CLK at the F / F 828, and is ANDed with the 2-bit output color selection signal CNO at the AND gate 830. The bit 0 of the output color selection signal CNO is negated by the inverter 829 and input to the AND gate 830, and the bit 1 of the output color selection signal CNO is input to the AND gate 830 as it is. At this time, that is, at the time of printing the Y image (in this example, CNO = “10” indicates the Y color image), the dot and mark enable signals are enabled.

As described with reference to FIGS. 4 and 5, in the dot pattern of the present embodiment, the first and fifth dot patterns are "0".
Or “−α”, and the third is “255” or “+”
α ”. Therefore, while the above-mentioned dot enable signal or mark enable signal is at H, in order to form a dot pattern as shown in FIGS. 4 and 5, a counter 825, a gate circuit 826, a flip-flop (F / F) ) 827 are provided.

The output of the AND gate 824 is
The counter 825 counts the pixel synchronization signal CLK only when the output of the AND gate 824 is H, that is, when the add-on dot is enabled or the mark is enabled. The bit 1 (Q1) and the bit 0 (Q0) of the output of the counter 825 are input to the gate circuit 826, and the first and fifth clocks in the add-on dot enable period (or mark enable period) (5CLK) are used. The MINUS signal that becomes H, and the signal that becomes H at the first, third, and fifth clocks are output. The output of the gate circuit 826 is synchronized with the pixel synchronization signal CLK by the F / F 827a and the F / F 827b. Here, the signal MINU
When S is H, the add-on dot is modulated to -α.

FIG. 14 is a block diagram illustrating a detailed circuit configuration of gate circuit 826. AND gate 826a
Outputs a signal H when Q0 and Q1 are both L. Accordingly, only the first (000) and the fifth (100) of the outputs of the counters 825 of 000 to 100 become H. Therefore, the above-mentioned MINUS signal is generated. In addition, the inverter 826 b
5, the counter 825 outputs a value of “000” (first), a value of “010” (third), and a value of “100” (fifth). The signal H is output. Therefore, the above signal is obtained.

The F / F 827a removes the whiskers of the signal MINUS and the F / F 827b removes the whisker of the signal and matches the phase with the add-on dot enable signal.

The signals described above, MINUS
Using (), the comparator circuits 19 and 23 superimpose the dot pattern. FIG. 15 is a block diagram illustrating a configuration example of a comparator circuit.

The AND unit 832 receives, for example, an 8-bit modulation amount α, the output of the AND gate 830, and the output of the F / F 827b from the register 831. The α stored in the register 831 is output from the AND unit 832 only at the timing of superimposing the add-on dot pattern (signal is H) and at the timing of the pixel to be modulated (signal is H). become. Therefore, the modulation amount α is output from the AND unit 832 at the timing of the dot to be modulated in the add-on line. Therefore, the pixels other than the dots to be modulated in the add-on line are not modulated because the modulation amount output from the AND unit 832 is 0.

Reference numeral 833 denotes an adder, and 835 denotes a subtractor. For example, an 8-bit image signal V is input to a terminal A. The modulation amount α output from the AND unit 832 is input to the terminal B. The output of the adder 833 is the OR circuit 8
34, and the output of the subtraction unit 835 is
7, respectively.

When modulating, the OR circuit 834 operates as follows:
When the addition result V + α of the addition circuit 833 overflows and the carry signal CY is output, the calculation result is forced to, for example, 255. In addition, the AND circuit 837
When the subtraction result V-α of the subtraction circuit 835 underflows and the carry signal CY is output, the inverter 836
The operation result is forcibly set to, for example, 0 by the carry signal CY inverted in (1). Therefore, by setting “255” as α, it is possible to superimpose the patterns at a time as shown in FIG.

Then, both calculation results “V + α, V−α” or “0, 255” are input to the selector 838, and
The signal MINUS (F / F) generated by the gate circuit 826
827a), and is output from the selector 838.

With the above circuit configuration, the dot modulation shown in FIG. 4 or FIG. 5 is performed. Next, a device number pattern is generated by arranging a dot pattern in each add-on line in accordance with the device number. FIG. 16 is a diagram illustrating a circuit configuration example of a device number pattern generation circuit.
The machine number pattern is generated by controlling the value loaded to the main scanning counter 814 as follows.

First, the F / F 813 and the counter 809 are reset by the sub-scanning synchronizing signal VSYNC.
The initial value of 14 is set to 0.

Here, the signal ADLIN input to the clock terminals of the counter 809 and the F / F 813 synchronizes the output of the AND gate 820, which is an add-on enable signal, with the main scanning synchronization signal HSYNC by the F / F 823. Signal.

The selector 810 selects one of the registers 801 to 808 in which, for example, a 4-bit value of each of the eight add-on lines is set according to, for example, a 3-bit signal input to the select terminal S. Then, the value set in the selected register is output.

The select signal of selector 810 is signal A
It is generated by a counter 809 that counts DLIN. At the first add-on-line timing, since the counter 809 is cleared by the sub-scanning synchronization signal VSYNC, the select signal is 0. Therefore, the selector 810 selects the register 801. And the signal A
When DLIN rises, the count value of counter 809 advances by one, and selector 810 selects register 802. Thereafter, the selector 810 repeatedly selects the registers 803 to 808 sequentially in synchronization with the signal ADLIN.

The output of the selector 810 is supplied to an adder 811
Is added to the output of the adder 812, input to the F / F 813, latched at the falling edge of the signal ADLIN, and input to the main scanning counter 814.

The output of the F / F 813 is sent to the main scanning counter 814 and the terminal B of the adder 812
, And is added to a constant value, for example, 8 inputted to the terminal A of the adder 812 and sent to the adder 811.
This is an offset value for providing an interval between the dot position of the add-on line and the dot position of the previous add-on line in the sub-scanning direction. The data setting in the registers a801 to h808 is performed based on the device number read from the ROM 24 by the CPU.

In the present embodiment, the CPU
The magnitude of the image signal of the input image is detected, the value of the 8-bit modulation amount α is determined according to the magnitude of the detected density signal, and set in the register 831. For example, by increasing the modulation amount α in the low-density region, it is possible to synthesize a pattern that is easy to see even with a low-density image. Also,
If the selected image processing is image processing for binary output, the CPU sets 255 to the register 831.

FIG. 17 is a diagram showing an example of a copy result according to the first embodiment. FIG. 17 shows only an example of the arrangement of the dot pattern of the add-on line. In FIG. 17, reference numeral 901 denotes a specific document image, for example. The dot pattern of the add-on line is indicated by a triangle.

As described above, according to the first embodiment, the optimum dot shape pattern for the pattern added to encode or encode the serial number unique to the copying machine is selected according to the type of image processing. You can choose. For this reason, it is possible to superimpose a readable dot pattern without deteriorating the quality of the copied image. Therefore, even if this embodiment is used for unauthorized copying,
By judging an illegal copy, it is possible to reliably specify the copying machine used for the illegal copy regardless of the type of image processing applied.

Note that in the upper embodiment. Although the comparator circuits 19 and 23 are configured as one circuit and achieve their respective functions by the selection signal, they may be provided as separate circuits for each image processing.

[Second Embodiment] FIG. 18 is a diagram showing a configuration of an apparatus according to a second embodiment. This system is
It plays a role as a multifunction machine of a copying machine and a printer. The image output device 53 receives, via an interface (I / F) 52, image data from the reading device 51 and image data output from the personal computer PC 55 and passing through the controller 54. The I / F 52 can receive an image output command from the reading device 51 and the controller 54, and can cope with an interrupt process or the like. The controller 54 includes a circuit for performing image processing related to the number of gradations, image resolution, pixel shape after output, and color matching.

FIG. 19 is a diagram showing a flow of an image signal in the image processing section of the second embodiment. When functioning as a copying machine, an image signal from the reading device 51 is used. LD driver 28 from CCD 105
Is basically the same as in the first embodiment, and a description thereof will be omitted. However, the I / F 52 is connected to the reading device 51.
Image signal LOG conversion circuit 13 and
This is notified to the machine number pattern generation circuit 25 and the pattern modulation control unit 26. The masking / UCR circuit 6
The 1-comparator circuit 64 may be configured as the selectors 14-comparator circuits 19 and 23 in FIG. 3 so as to be capable of supporting binary output and multi-level output.

On the other hand, in response to the image signal emitted from the PC 55, the controller 54 controls the image output device 53.
The most suitable image processing is performed. The signal is C
The MYK decomposed image signal enters the I / F 52. In this case, the I / F 52 selects the route 52a and
The signal is set to pass without passing through the OG conversion 13, the masking / UCR 61, the spatial filter 62, and the density conversion circuit 63.

At this time, the controller 54 passes a code corresponding to the image processing performed by itself to the machine number pattern generation circuit 25 via the I / F 52. Machine number pattern generation circuit 2
In step 5, a corresponding superimposed dot shape pattern is loaded from the ROM 24 and set. For example, if the image data has been binarized, the controller 54 outputs a signal to that effect to the I / O
It notifies the machine number pattern generation circuit 25 and the pattern modulation control unit 26 via F52. Machine number pattern generation circuit 25
The pattern modulation control unit 26 superimposes the device number pattern based on the device number read from the ROM 24 using the dot pattern shown in FIG.

In the second embodiment, an example has been described in which all image processing is performed by the controller 54 and CMYK signals are generated, but the RGB signals are passed to the image forming apparatus,
Some systems use image processing in the image forming apparatus. In that case, it goes without saying that a dot pattern according to the image processing of the main body may be selected and superimposed.

As described above, according to the second embodiment, a dot pattern for encoding or adding a production number unique to a copying machine is added to an image signal from outside the image forming apparatus. However, the most suitable one can be selected according to the type of image processing. For this reason, even when image formation is performed using image processing outside the image forming apparatus, it is possible to reliably recognize the superimposed dot pattern.

[Third Embodiment] Next, a third embodiment will be described. In the third embodiment, a case will be described in which image processing is switched in one image output product.

FIG. 20 is a diagram showing the appearance of an image forming apparatus according to the third embodiment. A so-called editor device including a pen-type indicator 71 for indicating a coordinate position on the pressure plate 72 of the platen holder and a sensor capable of detecting the coordinate position is provided. A document to be copied is applied to a designated position on the pressure plate 72, and a plurality of areas are designated by the pen-type indicator 71. FIG. 21 is a diagram illustrating an example of a position in a designated state of an area. In this example, the area A and the area B are specified. For example, it is assumed that an image having gradation characteristics such as a photograph is recorded in an area A, and an image centered on a character / line image is recorded in an area B. Therefore, image processing that is good at tone reproduction is performed in an area A having gradation characteristics such as a photograph, while area B, which requires reproducibility of details centering on characters / line drawings, is resolved. The correspondence between the area and the image processing is instructed by the operation panel and the editor device so that the processing is performed by the unique image processing.

FIG. 22 is a view for explaining an image processing procedure according to the third embodiment. FIG. 3 described in the first embodiment
The same reference numerals are given to the same components as in the first embodiment.

The image area selector 81 switches the image signal supply destination according to the area set as described above. That is, when the scanning position is the area A, the image signal is output to the masking / UCR circuit 20 in order to provide the image signal to the multi-value output image processing. On the other hand, when the scanning position is the area B, the image signal is supplied to the binarization processing circuit 15 in order to apply the binarized output image processing.

The information representing the image processing selected by the image area selector 81 is stored in the device number pattern generation circuit 25.
The dot pattern (FIGS. 4 and 5) suitable for each image processing is selected in the same procedure as in the first embodiment, and the device number pattern is superimposed.

As described above, according to the third embodiment, even when a gradation part and a character / line drawing part are mixed in one image, switching to the optimum image processing is performed for each. Is realized, and it is possible to superimpose the device number pattern by using an appropriate dot pattern corresponding thereto.
Therefore, even when a plurality of types of image processing are required in one image, it is possible to superimpose the patterns so that they can be reliably read.

In the third embodiment, an example has been described in which the user designates an area by himself. However, the area of a photographic image or a character image is automatically determined based on the pattern of a read image.
It is apparent that the image processing and the dot pattern may be automatically switched for each determined area.

The present invention can be applied to a system including a plurality of devices (for example, a host computer, an interface device, a reader, a printer, etc.), but can be applied to a single device (for example, a copier, a facsimile). Device).

Further, an object of the present invention is to supply a storage medium storing a program code of software for realizing the functions of the above-described embodiments to a system or an apparatus, and to provide a computer (or CPU) of the system or the apparatus.
And MPU) read and execute the program code stored in the storage medium.

In this case, the program code itself read from the storage medium realizes the functions of the above-described embodiment, and the storage medium storing the program code constitutes the present invention.

As a storage medium for supplying the program code, for example, a floppy disk, hard disk, optical disk, magneto-optical disk, CD-ROM, CD
-R, a magnetic tape, a nonvolatile memory card, a ROM, or the like can be used.

When the computer executes the readout program code, not only the functions of the above-described embodiment are realized, but also the OS (Operating System) running on the computer based on the instruction of the program code. ) May perform some or all of the actual processing, and the processing may realize the functions of the above-described embodiments.

Further, after the program code read from the storage medium is written into a memory provided in a function expansion board inserted into the computer or a function expansion unit connected to the computer, based on the instructions of the program code, It goes without saying that the CPU included in the function expansion board or the function expansion unit performs part or all of the actual processing, and the processing realizes the functions of the above-described embodiments.

[0090]

As described above, according to the present invention, a pattern suitable for applied image processing can be superimposed in an image forming apparatus to which a plurality of types of image processing can be applied when forming a visible image. Becomes For this reason, an appropriate pattern can be superimposed on the image after various types of image processing, and the pattern for specifying the device can be reliably determined, and the deterioration of the image quality of the formed image can be prevented.

[0091]

[Brief description of the drawings]

FIG. 1 is a side sectional view schematically showing an internal configuration of a full-color image forming apparatus according to a first embodiment.

FIG. 2 is a flowchart illustrating an image recording operation of the full-color image forming apparatus according to the first embodiment.

FIG. 3 is a diagram illustrating an image processing procedure according to the first embodiment.

FIG. 4 is a diagram illustrating an example of a dot pattern suitable for binarized output according to the first embodiment.

FIG. 5 is a diagram illustrating an example of a dot pattern suitable for image data subjected to image processing for multi-value output.

FIG. 6 is a diagram illustrating an example of an add-on line according to the first embodiment.

FIG. 7 is a diagram illustrating an example of an add-on line according to the first embodiment.

FIG. 8 is a diagram showing an example of a method for expressing information by add-on-line.

FIG. 9 is a diagram showing an example of a method of expressing information by add-on-line.

FIG. 10 is a diagram illustrating an example of a circuit configuration of a pattern modulation control unit 26.

FIG. 11 is a diagram illustrating a configuration of a gate circuit 820.

FIG. 12 is a diagram illustrating a circuit configuration example of a gate circuit 890.

FIG. 13 is a diagram conceptually showing a dot enable signal and a mark enable signal generated as described above.

FIG. 14 is a block diagram illustrating a detailed circuit configuration of a gate circuit 826.

FIG. 15 is a block diagram illustrating a configuration example of a comparator circuit.

FIG. 16 is a diagram illustrating a circuit configuration example of a device number pattern generation circuit.

FIG. 17 is a diagram illustrating an example of a copy result according to the first embodiment.

FIG. 18 is a diagram showing a configuration of an apparatus according to a second embodiment.

FIG. 19 is a diagram illustrating a flow of an image signal in an image processing unit according to the second embodiment.

FIG. 20 is a diagram illustrating an appearance of an image forming apparatus according to a third embodiment.

FIG. 21 is a diagram illustrating an example of a position in an area designation state.

FIG. 22 is a diagram illustrating an image processing procedure according to the third embodiment.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Polygon mirror 2 Mirror 3 Developing device 4 Photoreceptor drum 6 Recording material 7 Fixing roller 101 Document 102 Platen glass 103 Light source 104 Optical lens 105 CCD 106 Laser 111 Transfer drum

Claims (19)

[Claims] A selection unit that selects an optimal image processing based on an input image; a generation unit that generates a pattern indicating predetermined additional information based on the image processing applied to each of the input images. An image processing apparatus comprising: an adding unit configured to add a pattern generated by the generating unit to the input image so that the pattern is not easily recognized by human eyes. 2. The image processing apparatus according to claim 1, further comprising a plurality of image processing units for processing the image signals, wherein the plurality of image processing units perform at least image processing for binarizing and outputting the image signals, and multi-valued image signals. The image processing apparatus according to claim 1, further comprising: image processing for outputting the image data. 3. The apparatus according to claim 1, wherein the predetermined additional information is information for specifying the image processing apparatus.
Or the image processing device according to 2. 4. A pattern suitable for image processing for binarizing and outputting an input image has a larger size than a pattern suitable for image processing for outputting a multi-valued input image. The image processing apparatus according to claim 2. 5. The image processing apparatus according to claim 1, wherein said generating means uses a pattern in which a minimum value and a maximum value of the input image are arranged as a pattern for image processing for binarizing and outputting the input image. 3. The image processing device according to 2. 6. The method according to claim 1, wherein said generating means uses a pattern in which the number of gradations to be applied to the input image is arranged as a pattern for image processing for outputting the input image in multi-valued form. 3. The image processing device according to 2. 7. An image processing apparatus further comprising: input means for inputting data indicating image processing content adopted for an input image, wherein said generating means is configured to output said data based on data indicating image processing content input by said input means. The image processing apparatus according to claim 1, wherein the pattern is determined. 8. An image processing apparatus, further comprising: a plurality of areas in one image; and designating means for designating image processing contents in each of the plurality of areas, wherein the generating means sets the image processing contents set in the plurality of areas. The image processing apparatus according to claim 1, wherein a pattern to be used in each of the plurality of regions is determined based on the pattern. 9. An image processing apparatus further comprising: an image processing unit that performs image processing while switching image processing to be applied to the input image based on a plurality of areas specified by the specification unit and image processing content. 9. The image processing apparatus according to claim 8, wherein a superimposition pattern to be applied is sequentially determined in synchronization with switching of image processing in the image processing unit. 10. A selecting step of selecting an optimum image processing based on an input image, and a generating step of generating a pattern indicating predetermined additional information based on the image processing applied to each of the input images. An image processing method, comprising: adding, to the input image, a pattern generated in the generating step so that the pattern is difficult to recognize by human eyes. 11. The image processing apparatus further comprises a plurality of image processing steps for processing an image signal, wherein the plurality of image processing steps include image processing for binarizing and outputting the image signal, and multi-valued image signal processing. The image processing method according to claim 10, further comprising: image processing for outputting the image data. 12. The image processing method according to claim 10, wherein the predetermined additional information is information that can specify the image processing method. 13. A pattern suitable for image processing for binarizing and outputting an input image has a larger size than a pattern suitable for image processing for outputting a multi-valued input image. The image processing method according to claim 11. 14. The method according to claim 1, wherein the generating step uses a pattern in which a minimum value and a maximum value of the input image are arranged as a pattern for image processing for binarizing and outputting the input image. 12. The image processing method according to item 11. 15. The method according to claim 15, wherein the generation step uses a pattern in which the number of gradations to be applied to the input image is arranged, as a pattern for image processing for outputting the input image in multi-valued form. 12. The image processing method according to item 11. 16. An input step of inputting data indicating image processing content adopted for an input image, wherein the generating step includes the step of: The image processing method according to claim 10, wherein a pattern is determined. 17. An image, comprising: a plurality of regions;
The image processing apparatus further includes a designation step of designating image processing contents in each of the plurality of areas, wherein the generating step includes, based on the image processing contents set in the plurality of areas, a pattern to be used in each of the plurality of areas. 11. The method according to claim 10, wherein the determination is performed.
The image processing method according to 1. 18. The image processing apparatus according to claim 18, further comprising: an image processing step of performing image processing while switching image processing to be applied to the input image based on the plurality of areas specified in the specifying step and image processing content. 18. The image processing method according to claim 17, wherein a superimposition pattern to be applied is sequentially determined in synchronization with switching of the image processing in the image processing step. 19. A computer-readable memory storing a control program for performing image processing for forming a visible image on an input image, wherein the control program selects an optimum image processing based on the input image. A code of a selecting step, a code of a generating step of generating a pattern indicating predetermined additional information based on image processing applied to each of the input images, and a code of a generating step of generating the pattern for the input image. And a code for an additional step of adding the pattern so that it is difficult for the human eye to recognize the pattern.