JPH113275A - Information processing device - Google Patents

Abstract

(57) [Problem] To provide an information processing apparatus that realizes high-speed bit access from a CPU. An address conversion circuit includes a memory.
A memory address for reading a plurality of bits of data from the memory and a bit address for specifying 1-bit data from the plurality of bits of data read by the memory address are generated from an address output from the CPU 103. High speed bit access is achieved by using a read bit aligner that generates data to be transferred to the CPU 103 based on the address and a write bit aligner that generates data to be transferred to the memory 103 based on the bit address.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to an information processing apparatus, and more particularly, to an information processing apparatus which executes a bit operation at high speed.

[0002]

2. Description of the Related Art The performance of CPUs has been increasing at a remarkable pace due to advances in semiconductor technology and computer architecture. The internal arithmetic units and registers of CPUs are 16-bit or 32-bit, and the unit of memory access is longword. (32-bit), word (16-bit), and byte (8-bit) in many cases, and a bit-by-bit operation requires processing through software.

A description will be given of a case where a process of calculating bit data on a memory and storing the calculated data at a certain bit address on the memory is executed.

(1) Byte data including a bit address to be input is stored from a memory into internal data. (2)
A specific bit is read from the byte data
A shift operation for aligning to the SB side is performed. (3) Perform a bit operation using a register. (4) In order to write back the bit operation result to a certain bit address, the byte data including the bit to be stored is read from the memory to the internal register. The bit operation result is inserted only into the portion corresponding to the bit address in the read data, and the inserted byte data is stored in the memory.

[0005]

When a memory access is realized by a software program when the CPU cannot access data of less than bytes, the processes (1), (2) and (4) described above are executed on the program. It takes a long time to execute the program and the speed cannot be increased. In addition, the instruction reading overhead of the increased program instruction increases the overhead of the instruction fetch and lowers the performance. Further, an increase in the number of instructions causes a problem that a large instruction storage memory capacity is required and the cost becomes high.

An object of the present invention is to provide an information processing apparatus which realizes high-speed bit access from a CPU which cannot access a memory of less than bytes.

[0007]

In order to achieve the above object, the present invention provides a CPU for executing a predetermined operation, a memory for storing data, and a plurality of bits stored in a memory from an address output from the CPU. And an address conversion circuit for generating a bit address for designating 1-bit data of a plurality of bits of data read by the memory address.

According to another aspect of the present invention, there is provided a CPU for executing a predetermined operation, a memory for storing data, a memory address for reading one word of data from the memory, and a memory address for reading. An address conversion circuit for generating a bit address for designating 1-bit data from the output 1-word data from an address output from the CPU, and a bit from the 1-word data read from the memory by the memory address A bit data at a position specified by an address is selected, a one-word data in which the selected bit data is stored at a predetermined position is generated, and a first bit aligner for transferring the data to the CPU is read from the memory by the memory address. At a position specified by the bit address of the one-word data, Storing the data, and having a second bit aligners to be transferred to memory.

Further, in order to achieve the above object, the present invention provides a CPU for executing a predetermined operation, a memory for storing a plurality of data, a CPU and a first data bus, and a memory and a second data bus. A bit aligner that is connected and selects 1-bit data from data read out of the memory in word units to generate data in word units, a CPU and a first address bus, and a memory and a second address bus. An information processing apparatus, comprising: an address conversion circuit that is connected to generate an address for reading data in word units from a memory based on an address output from a CPU; and a bypass unit that directly connects the CPU and the memory. The address conversion circuit controls the bit so that the CPU can access the bit based on a predetermined bit of the address output from the CPU. Along with selecting the aligner, CPU
Is transferred to a bit aligner as a bit address of a predetermined address of the address output from the bit line.

[0010]

FIG. 1 shows the overall configuration of an information processing apparatus. The information processing device includes a bit processing device 101 that performs bit processing, and a memory 102. Furthermore,
The bit processing device 101 includes a CPU 103, an address conversion circuit 1
04, a read bit aligner 105, and a write bit aligner 106.

The CPU 103 and the address conversion circuit 104 are connected by a long word address bus 110,
The U103, the read bit aligner 105, and the write bit aligner 106 are 4 byte wide data buses 121 and 12.
2 and 123, the memory 102 and the address conversion circuit 104 are connected by a long word address bus 111, and the memory 102 and the read bit aligner 1 are connected.
05, the write bit aligner 106 is connected to data buses 120, 124 and 125 having a 4-byte width.
The address conversion circuit 104 is connected to the read bit aligner 105 and the write bit aligner 106 by an address bus 112.

Next, an outline of the operation of the address conversion circuit 104 will be described.

FIG. 2 shows a processor address 201 output from the CPU 103 and an address 202 converted by the address conversion circuit 104. As shown in FIG. 2, the processor address 20 output from the CPU 103
1 is a long word address, word, byte,
There is no bit address indicating the bit. Therefore, the address conversion circuit 104 assigns the upper 5 bits of the processor address to the bit address, and combines the remaining bits with the 5 bits having the logical level “0” to form a long word address for memory access.

That is, the upper 5 bits (A) of the processor address are added as a bit address to the lower part of the processor address, and the upper 5 bits that originally had (A) are set to the logical level "0". By this conversion, an address can be specified up to a bit address.

FIG. 3 shows the concept of the memory space based on the converted address. The processor address output from the CPU 301 is equally divided into 32 by the upper 5 bits A described in FIG. Each of the 32 equally divided address spaces is a space designated by B described in FIG. The converted address is compressed to 1/32 of the entire processor address space, and the address space width becomes B. The bit address is related to the 0-31 space of the processor address divided into 32 equal parts, the 0th bit when accessed from the 0 space, the 1st bit when accessed from the 1st space,..., 31 spaces When accessed from 3
Can access the first bit.

Next, the operation of the information processing apparatus shown in FIG. 1 for reading data from the memory 102 based on the flowchart of FIG. 4 will be described.

First, when a bit read request is generated by executing a program in the CPU 103, the CPU 103 outputs a long word processor address. The processor address output from the CPU 103 is input to the address conversion circuit 104 via the address bus 110.

The address conversion circuit 104 performs the processing of FIG. 2 described above to generate a bit address and a long address for memory access from the processor address. The generated bit address is input to the read bit aligner via the address bus 112, and the generated long address for memory access is input to the memory 102 via the address bus 111.

The memory 102 receiving the long word address for memory access outputs the corresponding 4-byte data to the data bus 125, and outputs the 4-byte data via the data bus 120 to the read bit aligner 105. Is input to

The read bit aligner 105 shifts the data specified by the bit address out of the 4-byte data read from the memory, and
Output to Specifically, the read bit aligner 10
5 receives the 4-byte data 501 read from the memory as shown in FIG. 5 and, when the bit address sent from the address conversion circuit 104 designates the n-th bit, The n-th bit data of the 4-byte data 501 read from the memory is shifted to the 0-bit data D0, and the data 502 output from the read bit aligner 105 is generated.

Thus, the read bit aligner 1
The data shifted in 05 is transmitted to data buses 121 and 122.
Is transmitted to the CPU 103 via the CPU and stored in a register in the CPU 103. FIG. 5 shows the internal register 503 of the CPU 103.

As described above, the configuration in which the CPU 103 accesses with a longword processor address has been described.
A function of generating a bit address inside the U103 and shifting the designated bit data in the same manner as the read bit aligner 105 is provided so that predetermined data is stored in the internal register.

Next, the operation of the information processing apparatus shown in FIG. 1 when writing data will be described with reference to the flowchart of FIG.

When a bit write request is generated by executing a program in the CPU 103, the CPU 103 outputs a long word processor address to the address bus 110 and 4-byte data including bit data to be written to the memory to the data bus 122. Note that the 4-byte data output from the CPU 103 is the data 701 in FIG. 7, and the bit data to be written to the memory is stored in D0.

The processor address output from the CPU 103 is input to an address conversion circuit 104. The address conversion circuit 104 performs the processing of FIG. 2 described above, and generates a bit address and a long word address for memory access from the processor address. The generated bit address is input to the write bit aligner 106 via the address bus 112, and the generated long word address for memory access is input to the memory 102 via the address bus 111. The memory 102 receiving the long word address for memory access outputs the corresponding 4-byte data to the data bus 125, and the output 4-byte data is input to the write bit aligner 106 via the data bus 120. You. On the other hand, the 4-byte data output from the CPU 103 is also input to the write bit aligner 106.

The write bit aligner 106 stores the 4-byte data 701 sent from the CPU 103 as shown in FIG.
Is written in the position specified by the bit address of the 4-byte data 702 read from the memory 102 to generate data 703 for writing to the memory. The generated 4-byte data 703 for writing to the memory is written to the memory 102 via the data buses 124 and 125 at the position specified by the long word address for memory access.

If the memory 102 can be accessed in 1-bit units, it is possible to write data with bit addresses after direct address conversion.

Next, the circuit configuration of each section will be described.

FIG. 8 shows the configuration of the address conversion circuit 104. This address conversion circuit 104
The processor address output from U103 is transferred to address bus 11
Input via 0. The address bus 110 is divided into respective signal lines in the circuit, and n to n-4 signal lines corresponding to the upper 5 bits of the processor become the address bus 112 and output address bits. The line and the signal line fixed to the low level become the address bus 111 and output a long word address for memory access.

FIG. 9 shows the structure of the read bit aligner 105.

The read bit aligner 105 inputs 4-byte data from the memory via the data bus 120 and a bit address via the address bus 112, and
The byte data is output to the data bus 121.

The bit address input via the address bus 112 is decoded into signals 0 to 31 by a 5-bit full decoder. In this signal, only one of the signal lines is always asserted, and the information of the bit data input to the input AND gate connected to the asserted signal line is shifted to the D0 bit. The other bits D1 to D31 are fixed at low level and logically fixed to "0". Thus, the 4-byte data shifted to the D0 bit is output. In addition, this D1
Since D31 is input to the register of the CPU 103 as it is and bit-operated, it is not meaningful, so that it need not be logically "0".

FIG. 10 shows a write bit aligner circuit 1
FIG. 6 shows the configuration of FIG.

The write bit aligner circuit 106 inputs 4-byte data from the memory via the data bus 120, 4-byte data from the CPU 103 via the data bus 123, and a bit address via the address bus 112. , And outputs 4-byte data including the rewritten bit data to the data bus 124.

The bit address input via the address bus 112 is decoded into signals 0 to 31 by a 5-bit full decoder. As for this signal, only one signal is always asserted. Only the selector of the asserted signal outputs the value of D0 which is the write bit data output from the CPU 103, and the outputs of the other selectors are read from the memory. The value of the output bit data is output. Thus, the information of D0 can be written at the bit position specified by the bit address. Note that the bit data D1 to D31 from the CPU 103 are not connected anywhere, and these data do not affect the data output from the data bus 124.

FIG. 11 shows another embodiment.

FIG. 11 shows the configuration of the information processing apparatus. The information processing device includes a bit processing device 101 for performing bit processing and a memory 102. The bit processing device 101 includes a CPU 103, an address conversion circuit 104, a read bit aligner 105, and a write bit aligner 1.
06.

The CPU 103 and the address conversion circuit 104 are connected by a long word address bus 110,
The U103 and the write bit aligner 106 are connected by data buses 122 and 123 each having a 4-byte width.
The address conversion circuit 104 is connected to a long word address bus 111, and the memory 102, the read bit aligner 105, and the write bit aligner 106 are connected to a 4-byte data bus 120. The address conversion circuit 104 is connected to the read bit aligner 105 and the write bit aligner 106 by an address bus 112.

Further, in this information processing apparatus, the CPU 301 and the read bit aligner are connected to the data buses 121 and 122 via the selector 1112, and the memory 102 and the write bit aligner 106 are connected via the selector 1113. ing. The selector 1112 is the read bit aligner 1
05 and the output of the memory 102. The selector 1113 can select 4 bytes of data output from the CPU 103 and 4 bytes of data output from the write bit aligner 106. ing. Each of the selectors 1112 and 1113 is controlled by the address conversion circuit 104.

FIG. 12 shows the processor address output from the CPU 103 and the address converted by the address conversion circuit 104.

The difference from the processor address shown in FIG. 2 is that it includes bit (C). The meaning of this bit (C) is “0” when the address conversion circuit 104
Generates a bit address and a long address for memory access. When "1", the address conversion circuit 10
In step 4, the bit address and the long address for memory access are not generated, and the signal 1111 is asserted.
That is, when the bit (C) is “0”, the CPU 103 performs bit access, and when the bit (C) is “1”, the CPU 103 accesses the main memory by a normal read instruction.

When the bit (C) is "0", the address conversion circuit 104 assigns a plurality of upper bits (A) to a bit address, and the bits (A),
(C) is set to the logical level “0”, and a long address for memory access is generated in combination with the remaining bit (B).

As described above, the information processing apparatus can switch between bit access and normal read access by an instruction from the CPU.

The bit access is shown in FIGS.
This is no different from the operation described with reference to FIG.

The contents described above are merely examples, and the present invention is not limited to this. For example, for convenience of description, the read bit aligner 105 and the write bit aligner 1
However, these may be configured on one circuit, that is, on the same semiconductor substrate.

Further, the bit processing device 101 and the memory 10
2 are described separately, but they may be arranged on the same semiconductor substrate.

[0047]

According to the present invention, in a CPU that cannot perform memory access of less than a byte, high-speed bit-unit access can be performed without replacing existing instructions and without requiring special memory access by software. Can be executed.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of an information processing apparatus to which the present invention has been applied.

FIG. 2 is a diagram illustrating an operation of an address conversion circuit.

FIG. 3 is a diagram for explaining the concept of address conversion.

FIG. 4 is a flowchart showing an operation of the information processing apparatus when the CPU reads data.

FIG. 5 is a diagram showing a data configuration of each unit in the information processing apparatus.

FIG. 6 is a flowchart showing the operation of the information processing apparatus when the CPU writes data.

FIG. 7 is a diagram for explaining the operation of the write bit aligner.

FIG. 8 is a diagram showing a configuration of an address conversion circuit.

FIG. 9 is a diagram showing a configuration of a read bit aligner.

FIG. 10 is a diagram showing a configuration of a write bit aligner.

FIG. 11 is a diagram showing a configuration of another information processing apparatus to which the present invention has been applied.

FIG. 12 is a diagram illustrating an operation of an address conversion circuit.

[Explanation of symbols]

101: bit processing device, 102: memory, 103: C
PU, 104: address conversion circuit, 105: read bit aligner, 106: write bit aligner, 11
0, 111, 112 ... address bus, 120, 121,
122, 123, 124, 125 ... data bus.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Atsushi Ito 46-1 Tomioka, Nakajo-cho, Kitakanbara-gun, Niigata Prefecture Industrial Machinery Division, Hitachi, Ltd.

Claims (5)

[Claims] A CPU for executing a predetermined operation; a memory for storing data; a memory address for reading a plurality of bits of data stored in the memory from an address output from the CPU; And an address conversion circuit for generating a bit address for designating 1-bit data of the plurality of bits of data read by the information processing apparatus. 2. The address conversion circuit according to claim 1, wherein the address conversion circuit separates an address output from the CPU, sets one of the addresses as the bit address, and adds predetermined bit data to the other to obtain the memory address. An information processing apparatus characterized by the above-mentioned. A CPU for executing a predetermined operation; a memory for storing data; a memory address for reading one word of data from the memory; and a memory address for reading one word of data from the memory address. An address conversion circuit for generating a bit address for designating bit data from an address output from the CPU; and an address conversion circuit designated by the bit address from one word data read from the memory by the memory address. Selecting the bit data at the position, generating one word data storing the selected bit data at a predetermined position,
A first bit aligner to be transferred to the CPU; and predetermined bit data stored in a position specified by the bit address of one-word data read from the memory by the memory address, and transferred to the memory. And a second bit aligner that performs the operation. 4. A CPU for executing a predetermined operation; a memory for storing a plurality of data; a CPU and a first data bus connected to the memory and a second data bus; A bit aligner for selecting 1-bit data from the data read in step 1 and generating data in word units, the CPU and the first address bus, the memory and the second
An address conversion circuit that is connected by an address bus and generates an address for reading data in word units from the memory based on an address output from the CPU; and a bypass unit that directly connects the CPU and the memory. The address conversion circuit selects the bit aligner based on a predetermined bit of an address output from the CPU so that the CPU can access the bit, An information processing apparatus for transferring a predetermined bit of an output address to the bit aligner as the bit address. 5. The address conversion circuit according to claim 4, wherein the address conversion circuit selects the bypass means based on a predetermined bit of an address output from the CPU so that the CPU can access in word units. Characteristic information processing device.