JPH11328962A - Semiconductor integrated circuit device - Google Patents

Abstract

(57) [Abstract] [Problem] To achieve low power consumption and high device reliability,
Provided is a semiconductor integrated circuit device in which an internal circuit is operated by high-speed operation and a step-down voltage, and an output signal is transmitted in synchronization with a clock signal. Provided is a semiconductor integrated circuit device having a level shift circuit with logic having a simple configuration. SOLUTION: An internal circuit which receives a power supply voltage supplied from an external terminal and is operated by a stepped down voltage,
An output circuit for outputting a signal to be output formed by the internal circuit through an external terminal in accordance with a timing signal, wherein a signal to be output formed by the internal circuit is output to the external circuit by a level shift circuit. The signal is converted to a signal level corresponding to the voltage level supplied from the terminal, and the output circuit outputs the level-converted signal using a timing signal of a voltage level corresponding to the power supply voltage supplied from the external terminal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to an output system circuit in a semiconductor memory such as a dynamic RAM (random access memory) in which an internal circuit is operated at a step-down voltage, and used therefor. The present invention relates to a technology that is effective when used in a level shift circuit with logic.

[0002]

2. Description of the Related Art In a highly integrated semiconductor memory, a method of operating an internal circuit at a step-down voltage lower than an external power supply voltage has been widely used in order to secure reliability of a fine device and reduce power consumption. An example of a dynamic RAM having such a step-down circuit is disclosed in Japanese Patent Application Laid-Open No. 9-270191.
There is an official gazette.

[0003]

When the internal circuit is operated with the step-down voltage as described above, in the output circuit, a level shift or level conversion (amplification) operation is performed in the preceding stage, and the input / output interface is set to a desired specification. It is necessary to match. In this case, if the output circuit performs an output operation in accordance with a timing signal such as a clock signal, the speed is reduced by the level shift or level conversion operation. For example, a synchronous D that obtains an output signal synchronized with a clock signal
In a RAM or the like, since the delay time tAC of the signal output timing with respect to the clock signal is required to be as small as about 5 ns, the time spent for the level conversion cannot be ignored. In the case where the step-down voltage is further reduced for the purpose of low power consumption and high reliability of the element with the progress of the miniaturization of the device, the time spent for level conversion is further increased. In a semiconductor integrated circuit device in which an internal circuit is operated,
Signal delay in the level shift (conversion) operation is an important issue.

An object of the present invention is to provide a semiconductor integrated circuit device which realizes high-speed operation while achieving low power consumption and high device reliability. Another object of the present invention is to provide a semiconductor integrated circuit device in which an internal circuit is operated by a step-down voltage and an output signal is transmitted in synchronization with a clock signal. Still another object of the present invention is to provide
An object of the present invention is to provide a semiconductor integrated circuit device having a level shift circuit with logic having a simple configuration. The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0005]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application. That is, an internal circuit that receives a power supply voltage supplied from an external terminal and operates at a stepped-down voltage, and an output circuit that outputs a signal to be output formed by the internal circuit through an external terminal according to a timing signal. In the semiconductor integrated circuit device provided, a signal to be output formed in the internal circuit is converted into a signal level corresponding to a voltage level supplied from the external terminal by a level shift circuit, and the signal is output from the external terminal by the output circuit. The level-converted signal is output using a timing signal having a voltage level corresponding to the supplied power supply voltage.

The following is a brief description of an outline of another typical invention disclosed in the present application. That is, an internal circuit that receives a power supply voltage supplied from an external terminal and operates at a stepped down voltage,
As a logic unit that performs logical processing of a first signal formed by the internal circuit and a second signal corresponding to a power supply voltage supplied from an external terminal, performs a switch operation complementarily in response to the first signal. A pair of first and second N-channel MOSFETs, and the first and second N-channel MOSFETs;
First and second P-channel MOSFETs provided between a drain of an OSFET and a power supply voltage supplied from an external terminal and having a gate and a drain cross-connected to each other
And a third N-channel MOSFET connected in series (or in parallel) with the drain of which is connected to the output terminal of the pair of N-channel MOSFETs, receiving the second signal at the gate; Two cross-connected P-channel MOSFETs whose gates receive two signals have a drain connected to the output terminal and a third P-channel MOSFET connected in parallel (or in series).

[0007]

FIG. 1 is a schematic layout diagram showing one embodiment of a dynamic RAM to which the present invention is applied. In the figure, the main part of each circuit block constituting the dynamic RAM to which the present invention is applied is shown so that it can be understood. Are formed on one semiconductor substrate.

In this embodiment, although not particularly limited, the memory array is divided into four as a whole. A power supply circuit including an input / output interface circuit composed of an address input circuit, a data input / output circuit, a bonding pad array, a step-down circuit, and the like are provided in a central portion 14 in the longitudinal direction of the semiconductor chip. Column decoder regions 13 are arranged in portions of both sides of the central portion 14 in contact with the memory array.

As described above, in each of the four memory arrays divided into two on the left and right and two on the upper and lower sides with respect to the longitudinal direction of the semiconductor chip, the main row decoder is disposed at the upper and lower central parts in the longitudinal direction. An area 11 is provided. Main word driver regions 12 are formed above and below the main row decoder, and drive the main word lines of the vertically divided memory array.

The above-mentioned memory cell array (sub-array) 15
Are formed so as to be surrounded by the sense amplifier region 16 and the sub-word driver region 17 with the memory cell array 15 interposed therebetween, as shown in the enlarged view. An intersection between the sense amplifier area and the sub-word driver area is an intersection area (cross area) 18. The sense amplifiers provided in the sense amplifier region 16 are configured by a shared sense method, and except for the sense amplifiers arranged at both ends of the memory cell array, complementary bit lines are provided on the left and right around the sense amplifier. Selectively connected to the complementary bit lines of the memory cell array.

As described above, the memory arrays divided into four on the left and right sides in the longitudinal direction of the semiconductor chip are arranged in groups of two. In the two memory arrays thus arranged in pairs, the main row decoder region 11 and the main word driver 12 are arranged in the center. The main word driver 12 generates a selection signal of a main word line extended so as to penetrate the one memory array. The main word driver 12 is also provided with a driver for selecting a sub-word, and extends in parallel with the main word line to form a sub-word selection line signal, as described later.

Although not shown, one memory cell array (sub-array) 15 shown as an enlarged view has 256 sub-word lines and 256 pairs of complementary bit lines (or data lines) orthogonal thereto. In the one memory array, 16 memory cell arrays (sub-arrays) 15 are provided in the bit line direction. Therefore, about 4K sub-word lines are provided as a whole, and 8 sub-word lines are provided in the word line direction. A total of about 2K lines are provided. Since eight such memory arrays are provided as a whole, the memory array has a total storage capacity of 8 × 2K × 4K = 64 Mbits.

The one memory array is divided into eight in the main word line direction. A sub-word driver (sub-word line driving circuit) 17 is provided for each of the divided memory cell arrays 15. The sub-word driver 17 is divided into の 長 of the length of the main word line, and forms a sub-word line selection signal extending in parallel with the length. In this embodiment, in order to reduce the number of main word lines, in other words, to reduce the wiring pitch of the main word lines, there is no particular limitation. Are arranged four sub-word lines. In order to select one sub-word line from among the sub-word lines divided into eight in the main word line direction and four in the complementary bit line direction, a sub-word selection driver is used. Be placed. This sub-word selection driver is extended in the arrangement direction of the sub-word drivers.
A selection signal for selecting one of the sub-word selection lines is formed.

Focusing on the one memory array, 1
One sub word line is selected from all eight memory cell arrays allocated to the main word lines. As described above, 2K (20
Since the memory cell of 48) is provided, 2048/8 = 256 memory cells are connected to one sub-word line.

As described above, one memory array has a storage capacity of 4K bits in the complementary bit line direction. However, if as many as 4K memory cells are connected to one complementary bit line, the parasitic capacitance of the complementary bit line increases, and a signal level that is read out cannot be obtained due to the capacitance ratio with a fine information storage capacitor. To
It is also divided into 16 in the complementary bit line direction. That is,
The complementary bit line is divided into 16 by the sense amplifier 16 indicated by a thick black line. Although not particularly limited, the sense amplifier 16 is configured by a shared sense method, and except for the sense amplifiers 16 arranged at both ends of the memory array, complementary bit lines are provided on the left and right around the sense amplifier 16, and the left and right sides are provided. Are selectively connected to the complementary bit lines.

FIG. 2 is a schematic layout diagram for explaining a dynamic RAM to which the present invention is applied. FIG. 1 shows a schematic layout of the entire memory chip and a layout of one memory array divided into eight. This figure illustrates the embodiment of FIG. 1 from another point of view. That is, as in FIG. 1, the memory array is divided into four parts in the left-right direction and up and down in the longitudinal direction (word line direction). The memory array (Array) is divided into 8
A plurality of bonding pads and address buffers, a control circuit, a predecoder, a timing control circuit, and other indirect peripheral circuits (Bonding Pad & peripheral Circuit) are provided at the central portion in the longitudinal direction.

Each of the eight memory arrays has a storage capacity of about 8 Mbits.
As one of them is shown enlarged, a sub-array divided into eight in the word line direction and divided into sixteen in the bit line direction is provided. On both sides of the sub-array in the bit line direction, sense amplifiers (Sence Amplifiers) are arranged in the bit line direction. A sub-word driver (Sub-Word driver) is provided on both sides of the sub-array in the word line direction.
Driver) is placed.

The one array is provided with a total of 4096 word lines and 2048 pairs of complementary bit lines.
As a result, the storage capacity is about 8 Mbits in total. As described above, 4096 word lines are divided into 16 sub-arrays and arranged, so that one sub-array is provided with 256 word lines (sub-word lines). In addition, since 2048 pairs of complementary bit lines are divided into eight sub-arrays as described above, one sub-array is provided with 256 pairs of complementary bit lines.

At the center of the two arrays, a main row decoder, an array control circuit and a main word driver are provided. The array control circuit includes a driver for driving a first sub-word selection line. A main word line extending so as to penetrate the eight divided sub-arrays is arranged in the array. The main word driver drives the main word line. Like the main word line, the first sub-word select line is also connected to
It is extended so as to penetrate the divided sub-array. Above the array, a Y decoder (YDecoder) and a Y select line driver (YSdriver) are provided.

FIG. 3 is a schematic layout diagram showing one embodiment of a sub-array and its peripheral circuits in a dynamic RAM according to the present invention. In FIG. 4, four sub-arrays SBARY arranged at hatched positions in the memory array shown in FIG. 2 are shown as representatives. In FIG. 3, a region where the sub-array SBARY is formed is shaded to distinguish a sub-word driver region, a sense amplifier region, and a cross area provided therearound.

The subarray SBARY is divided into the following four types. That is, when the extending direction of the word line is the horizontal direction, the first sub-array SBA
RY has 256 sub-word lines SWL and 256 complementary bit line pairs. Therefore, the above 2
The 256 sub-word drivers SWD corresponding to the 56 sub-word lines SWL are connected to the left and right of the sub-array by one.
It is divided into 28 pieces and arranged. The 256 sense amplifiers SA provided corresponding to the 256 pairs of complementary bit lines BL are arranged alternately in addition to the above-described shared sense amplifier system, and are divided into 128 pieces above and below the sub-array. Placed.

Second sub-array SBAR arranged at the upper right
Although Y is not particularly limited, the regular sub word line SWL
Is provided with eight spare (redundant) word lines in addition to 256, and the complementary bit line pairs are composed of 256 pairs. Therefore, the 264 sub-word drivers SWD corresponding to the above-mentioned 256 + 8 sub-word lines SWL are divided and arranged on the left and right of the sub-array in units of 132. As described above, 128 sense amplifiers are vertically arranged. That is, 128 pairs of complementary bit lines of the 256 pairs formed in the upper and lower sub-arrays SBARY arranged above and below the right side are commonly connected to the sense amplifier SA interposed therebetween via the shared switch MOSFET. .

A third sub-array SBAR arranged at the lower left
Y is composed of 256 sub-word lines SWL in the same manner as the right adjacent sub-array SBARY. 1 as above
28 sub-word drivers are divided and arranged. 256 of the subarray SBARY arranged on the lower left and right sides
The 128 sub-word lines SWL are commonly connected to the 128 sub-word drivers SWD formed in the region sandwiched between them. The subarray SBARY arranged at the lower left as described above is provided with four pairs of spare (redundant) bit lines 4RED in addition to 256 pairs of normal complementary bit lines BL. Therefore, the 260 sense amplifiers SA corresponding to the 260 pairs of complementary bit lines BL are divided and arranged in 130 units above and below the subarray.

Fourth subarray SBAR arranged at the upper left
Y has 256 regular sub-word lines SWL and eight spare sub-word lines as in the right adjacent sub-array SBARY. In addition to the 256 normal complementary bit line pairs as in the lower adjacent sub-array, the spare Are provided, and the sub-word drivers are divided into 132 units each on the left and right sides, and the sense amplifier SA is
Are divided and arranged.

The main word line MWL is extended in the horizontal direction as described above, one of which is exemplarily shown as a representative. The column selection line YS is extended in the vertical direction so that one of them is exemplified as a representative. A sub-word line SWL is arranged in parallel with the main word line MWL, and a complementary bit line BL (not shown) is arranged in parallel with the column selection line YS. In this embodiment, although not particularly limited, in the memory array of 8 Mbits as shown in FIG. 2, eight sub arrays are formed in the bit line direction with the above four sub arrays as one set of basic units. Four sets of subarrays are configured in the direction. Since one set of sub-arrays is composed of four,
In an M-bit memory array, 8 × 4 × 4 = 128 sub-arrays are provided. Since eight 8M-bit memory arrays are provided in the entire chip, 128 × 8 = 1024 subarrays are formed in the entire memory chip.

For the above four sub-arrays, 8
The sub-word select lines FX0B to FX7B are extended so as to penetrate four sets (eight) of sub-arrays, similarly to the main word line MWL. Then, the sub word select line FX
Four lines consisting of 0B to FX3B and four lines consisting of FX4B to FX7B are separately extended on the upper and lower sub-arrays. The reason why one set of sub-word selection lines FX0B to FX7B are allocated to the two sub-arrays and they are extended on the sub-arrays is to reduce the memory chip size.

That is, when the above-mentioned eight sub-word select lines FX0B to FX7B are allocated to each sub-array and are formed in the wiring channels on the sense amplifier area, the short-side direction as in the memory array of FIG. 32
As many as 256 sense channels are required for each sense amplifier. On the other hand, in the above-described embodiment, the wiring itself is connected to the upper and lower sub-arrays by the eight sub-word select lines FX0B to FX0B.
By allocating 7B in common and arranging them so that they are mixed on the sub-array in parallel with the main word line, it can be formed without providing a special wiring-dedicated area.

In the first place, one main word line is provided for eight sub-word lines on the sub-array, and a sub-word selection line is used to select one of the eight sub-word lines. Is necessary. Sub-word line S formed according to the pitch of the memory cells
Main word line MWL by one of eight WLs
Is formed, the main word line MWL
Have a gentle wiring pitch. Therefore, it is relatively easy to form the above-mentioned sub-word selection line between the main word lines by using the same wiring layer as the main word line MWL, with only a slight sacrifice in the looseness of the wiring pitch. .

The sub-word driver SWD of this embodiment
Is obtained by using a selection signal supplied through the sub-word selection line FX0B and the like and a selection signal obtained by inverting the selection signal.
A configuration for selecting one sub-word line SWL is adopted. The sub-word driver SWD is configured to simultaneously select the sub-word lines SWL of the sub-arrays arranged on the left and right of the sub-word driver SWD. Therefore, as described above, for the two sub-arrays sharing the FX0B or the like, the four sub-word selection lines are allocated and supplied to 128 × 2 = 256 sub-word drivers. That is, focusing on the sub-word selection line FX0B, it is necessary to supply a selection signal to as many as 256 ÷ 4 = 64 sub-word drivers SWD for two sub-arrays.

If the one extending in parallel with the main word line MWL is a first sub-word selection line FX0B,
The six sub-word selection line driving circuits FXD which are provided in the upper left cross area and receive the selection signal from the first sub-word selection line FX0B are arranged in the above-mentioned vertical direction.
A second sub-word selection line FX0 that supplies a selection signal to four sub-word drivers is provided. The first sub-word selection line FX0B extends in parallel with the main word line MWL and the sub-word line SWL, while the second sub-word selection line has a column selection line YS and a complementary bit line BL which are orthogonal thereto. The sub word driver area is extended in parallel. Similarly to the eight first sub-word selection lines FX0B to FX7B, the second sub-word selection lines FX0 to FX7 also have even numbers FX0, 2, 4, 6
And odd word FX1, 3, 5, 7 and subword drivers SW provided on the left and right of subarray SBARY.
D.

The sub word select line driving circuit FXD is
In the same drawing, as shown by a triangle, two pieces are distributed above and below one cross area. That is, as described above, in the upper left cross area, the sub-word selection line driving circuit arranged on the lower side operates the first sub-word selection line F
Two sub-word selection line driving circuits FXD corresponding to X0B and provided in the cross area in the left middle part are disposed above the lower left cross area in correspondence to the first sub-word selection lines FX2B and FX4B. The sub-word selection line driving circuit corresponds to the first sub-word selection line FX6B.

In the upper central cross area, a lower sub word select line driving circuit corresponding to the first sub word select line FX1B is provided, and two sub word select line drivers provided in the central middle cross area are driven. Circuit FXD
Correspond to the first sub-word selection lines FX3B and FX5B, and the sub-word selection line driving circuit disposed above the cross area at the lower center corresponds to the first sub-word selection line FX7B. In the upper right cross area, the lower sub word select line drive circuit corresponds to the first sub word select line FX0B, and two sub word select line drive circuits provided in the right middle cross area. FXD is the first sub-word select line FX2B
And the sub-word selection line driving circuit disposed above the cross area at the lower right of FIG. 4 corresponds to the first sub-word selection line FX6B. Thus, in the sub-word driver provided at the end of the memory array,
Since there is no sub-array on the right side, only the left sub-word line SWL is driven.

As in this embodiment, the sub-word selection line FX is provided in the gap of the pitch of the main word line MWL on the sub-array.
In the configuration in which B is arranged, a special wiring channel can be made unnecessary, so that arranging eight sub-word selection lines in one sub-array does not increase the size of the memory chip. However, the formation of the sub-word select line driving circuit FXD as described above increases the area of the cross region, which hinders high integration. That is, in the cross area, a switch circuit IOSW provided corresponding to the main input / output line MIO and the local input / output line LIO, a power MOSFET driving a sense amplifier, a shared switch MOS
Driving circuit for driving FET, precharge MOS
This is because there is no area allowance because peripheral circuits such as a drive circuit for driving the FET are formed. For this reason, in the embodiment of FIG. 3, the upper and lower sub-arrays share the sub-word select line driving circuit FXD to suppress an increase in area.

Among the cross areas, those arranged in the extension direction A of the second sub-word selection lines FX0 to FX6 corresponding to the even numbers have internal voltages which are made constant with respect to the sense amplifiers as described later. An N-channel power MOSFET Q16 for supplying VDL, an N-channel power MOSFET Q15 for supplying an overdrive power supply voltage VDD, and an N-channel power MOSFET Q14 for supplying a circuit ground potential VSS to the sense amplifier. Is provided.

In the above-mentioned cross areas, those arranged in the extending direction B of the odd-numbered second sub-word select lines FX1 to FX7 include an inverter circuit for turning off the MOSFETs for precharging and equalizing bit lines. Although not particularly limited, an N-channel type power MOSFET for supplying the circuit ground potential VSS to the sense amplifier is provided. This N-channel type power MOSFET supplies a ground potential to the common source line (CSN) of the N-channel type MOSFET amplifying MOSFETs constituting the sense amplifier from both sides of the sense amplifier row. That is, for the 128 or 130 sense amplifiers provided in the sense amplifier area, the N-channel type power MOSFET provided in the cross area on the A side and the N-channel power MOSFET provided in the cross area on the B side are provided. The ground potential is supplied by both of the channel type power MOSFETs.

As described above, the sub word line drive circuit SWD
Selects the sub-word lines of the sub-array on both the left and right sides with the center as the center. On the other hand, two left and right sense amplifiers are activated corresponding to the sub-word lines of the two selected sub-arrays. That is, when the sub-word line is set to the selected state, the address selection MOSFET is turned on and the charge of the storage capacitor is combined with the bit line charge, so that the sense amplifier is activated to return to the original charge state. This is because a write operation needs to be performed. Therefore, except for the one corresponding to the subarray at the end, the power MOSFET is used to activate the sense amplifiers on both sides of the power MOSFET.
On the other hand, the sub-word line driving circuit S provided on the right or left side of the sub-array provided at the end of the sub-array group
In WD, only the sub-word line of the sub-array is selected, so that the power MOSFET activates only one sense amplifier group corresponding to the sub-array.

The sense amplifier is of a shared sense type, and among the subarrays arranged on both sides of the shared amplifier, the shared switch MOSFET corresponding to the complementary bit line on the side where the subword line is not selected is turned off. As a result, the read signal of the complementary bit line corresponding to the selected sub-word line is amplified, and a rewrite operation of returning the storage capacitor of the memory cell to the original charge state is performed.

FIG. 4 is a circuit diagram of a simplified embodiment from the address input to the data output centering on the sense amplifier section of the dynamic RAM according to the present invention. In the figure, a sense amplifier 16 sandwiched between two sub-arrays 15 from above and below and a circuit provided in the intersection area 18 are exemplarily shown, and others are shown as block diagrams. The circuit blocks indicated by the dotted lines are indicated by the above-mentioned reference numerals.

The dynamic memory cell is typically exemplified by one provided between the sub-word line SWL provided in the one sub-array 15 and one of the complementary bit lines BL and BLB. Is shown in The dynamic memory cell has an address selection MOS
It comprises an FET Qm and a storage capacitor Cs. The gate of the address selection MOSFET Qm is connected to the sub word line S
The drain of the MOSFET Qm is connected to the bit line BL, and the source is connected to the storage capacitor Cs. The other electrode of the storage capacitor Cs is shared and supplied with the plate voltage VPLT. MOS above
A negative back bias voltage VBB is applied to the substrate (channel) of the FET Qm. The selection level of the sub-word line SWL is a high voltage VPP higher than the high level of the bit line by the threshold voltage of the address selection MOSFET Qm.

When the sense amplifier is operated at the internal step-down voltage VDL, the high level amplified by the sense amplifier and given to the bit line is equal to the internal voltage VD
The level is set to L level. Therefore, the high voltage VPP corresponding to the word line selection level is set to VDL + Vth + α. A pair of complementary bit lines BL and BLB of the sub-array provided on the left side of the sense amplifier are arranged in parallel as shown in the figure, and are appropriately crossed as necessary to balance the bit line capacitance. . The complementary bit lines BL and BLB are connected to the shared switch MOSFET Q1.
And Q2 are connected to the input / output node of the unit circuit of the sense amplifier.

The unit circuit of the sense amplifier is composed of N-channel type amplifying MOSFETs Q5, Q6 and P-channel type amplifying MOSFETs Q7, Q8, whose gates and drains are cross-connected to form a latch. The sources of the N-channel MOSFETs Q5 and Q6 are connected to a common source line CSN. The sources of the P-channel MOSFETs Q7 and Q8 are connected to a common source line CS.
Connected to P. Power switch MOSFETs are connected to the common source lines CSN and CSP, respectively. Although not particularly limited, an N-channel type amplification MOS
Common source line C to which the sources of FETs Q5 and Q6 are connected
An operating voltage corresponding to the ground potential is applied to SN by an N-channel type power switch MOSFET Q14 provided in the cross area 18.

Although not particularly limited, the common source line CSP to which the sources of the P-channel type amplification MOSFETs Q7 and Q8 are connected is connected to the N-channel type power MO for overdrive provided in the cross area 18.
An SFET Q15 and an N-channel power MOSFET Q16 for supplying the internal voltage VDL are provided.
The power supply voltage VDD supplied from an external terminal is used for the overdrive voltage, although there is no particular limitation. Alternatively, in order to reduce the dependency of the operation speed of the sense amplifier on the power supply voltage VDD, the boosted voltage VPP is applied to the gate, the drain is connected to the power supply voltage VDD, and the voltage is slightly lowered from the source with respect to the power supply voltage VDD. The voltage may be obtained.

The N-channel type power MOSFET
The sense amplifier overdrive activation signal SAP1 supplied to the gate of Q15 is
Activation signal SAP supplied to the gate of SFET Q16
2, and SAP1 and SAP2 are set to a high level in time series. Although not particularly limited, the above SA
The high level of P1 and SAP2 is a signal of the boosted voltage VPP level. That is, the boost voltage VPP is about 3.8 V
Therefore, the N-channel MOSFET Q15,
Q16 can be sufficiently turned on. MOS
After the FET Q15 is turned off, the MOSFET Q16 is turned on, and a voltage corresponding to the internal voltage VDL is output from the source side.

An equalizing MOSF for short-circuiting the complementary bit line is provided at the input / output node of the unit circuit of the sense amplifier.
ETQ11 and switch MOSFETs Q9 and Q10 for supplying half precharge voltage VBLR to complementary bit lines
Is provided. These MOs
The precharge signal PCB is commonly supplied to the gates of the SFETs Q9 to Q11. This precharge signal PCB
Although not shown, an inverter circuit is provided in the cross area to speed up the fall of the driver circuit. In other words, prior to the word line selection timing at the start of the memory access, the MOSFETs Q9 to Q11 constituting the precharge circuit are switched at high speed through inverter circuits distributed in each cross area.

In the cross area 18, in addition to the circuit shown in FIG. 4, if necessary, a half precharge circuit for the common source lines CSP and CSN of the sense amplifier and a half precharge circuit for the local input / output line LIO are provided. , Shared distributed signal lines SHR and SHL are also provided.

The unit circuit of the sense amplifier is connected to the similar complementary bit lines BL and BLB of the lower sub-array 15 via shared switch MOSFETs Q3 and Q4. The switch MOSFETs Q12 and Q13 constitute a column switch circuit, and are turned on when the selection signal YS is set to a selection level (high level).
Input / output nodes and local input / output lines LIO1 and LIO1B, LIO2, LIO2B of the unit circuit of the sense amplifier
And so on. For example, when the sub-word line SWL of the upper sub-array is selected, the upper shared switch MOSFETs Q1 and Q2 of the sense amplifier are kept on and the lower shared switch MOSFET
Q3 and Q4 are turned off.

As a result, the input / output node of the sense amplifier is connected to the upper complementary bit lines BL and BLB to amplify the small signal of the memory cell connected to the selected sub-word line SWL. Circuit (Q
12 and Q13) through the local input / output lines LIO1, L
Communicate to IO1B. The local input / output lines LIO1, L
IO1B is connected to main input / output lines MIO and MIOB to which input terminals of the main amplifier 61 are connected via a switch circuit IOSW including N-channel MOSFETs Q19 and Q20 provided in the cross area 18. Although not shown in the figure, the MOSFETs Q19, Q2
By using a so-called analog gate provided with a P-channel type MOSFET in parallel with 0, it is possible to further increase the speed. In addition, MOSFETs Q19 and Q2
If the boosted voltage VPP is used for the gate voltage of 0, the on-resistance can be reduced and the speed can be increased. Although not shown in the figure, the output terminals of the write amplifier are also connected to the main input / output lines MIO and MIOB.

Although not particularly limited, the column switch circuit connects two pairs of complementary bit lines BL, BLB to two pairs of local input / output lines LIO1, LI in response to one selection signal YS.
O1B is connected to LIO2 and LIO2B. Therefore,
In the sub-array selected by the operation of selecting one main word line, a total of four pairs of complementary bit lines are selected by the two pairs of column switch circuits provided corresponding to the pair of sense amplifiers provided on both sides thereof. Therefore, simultaneous reading / writing of 4 bits can be performed by selecting one YS.

The address signal Ai is supplied to the address buffer 5
1 is supplied. The address buffer operates in a time-division manner to receive the X address signal and the Y address signal.
The X address signal is supplied to the predecoder 52, and a selection signal for the main word line MWL is formed via the main row decoder 11 and the main word driver 12. Since the address buffer 51 receives the address signal Ai supplied from the external terminal, it is operated by the power supply voltage VDD supplied from the external terminal, and the predecoder is operated by the step-down voltage VPERI.
The main word driver 12 is operated by the boost voltage VPP. Column decoder (driver) 53
Receives the Y address signal supplied by the time division operation of the address buffer 51 and forms the column selection signal YS.

The main amplifier 61 has a step-down voltage VPE
The signal is output from the external terminal Dout (or DQ) through the output buffer 62 operated by the RI and operated by the power supply voltage VDD supplied from the external terminal. A write signal input from an external terminal Din (or DQ) is taken in through an input buffer 63, and is written to the main input / output lines MIO and MIOB through a write amplifier included in the main amplifier 61 in FIG. Supply. The input section of the output buffer is provided with a level shift circuit as described below and a logic section for outputting the level-shifted signal to be output in synchronization with the timing signal.

FIG. 5 is a circuit diagram showing one embodiment of the output buffer of the dynamic RAM according to the present invention. FIG. 1 also shows circuit blocks showing the overall operation of the dynamic RAM. That is, the decoder is operated with the step-down voltage VPERI, and a decode signal having a signal amplitude corresponding to the step-down voltage VPERI is formed. The main word driver is operated with the boost voltage VPP. As described above, the memory array outputs a read signal having a signal amplitude corresponding to the operation voltage VDL of the sense amplifier. As described above, the sense amplifier transitions to VD
Although it is overdriven at D or a high voltage close thereto, it finally operates at the operating voltage VDL. The main amplifier is operated by the step-down voltage VPERI and forms a read signal MOB corresponding to the step-down voltage VPERI. Here, MOB means that the logic "1" is at a low level and the logic "0" is at a high level, and the signal of the opposite phase is represented by MO.

In the output buffer, the output signal MOB of the main amplifier is output from the external power supply voltage V
The signal is converted (amplified) to a voltage level corresponding to DD. This amplified signal MOH is supplied to one input of the NAND gate circuit G1. The signal MOH is inverted by an inverter circuit N1 and supplied to one input of a NAND gate circuit G2. These NAND gate circuits G1
And the other input of G2 are supplied with a data output timing signal DOC having a signal level corresponding to the power supply voltage VDD. The output MOSFETs QP and QN have a large gate capacitance because they are formed in a relatively large size in order to obtain a large load driving capability. Such output MOS
In order to drive the FETs QP and QN at high speed, the output signals of the gate circuits G1 and G2 are sequentially output to the inverter circuit N
2 through N4.

FIG. 6 shows a potential distribution diagram of a signal level corresponding to the operating voltage of each circuit of the dynamic RAM. That is, the address input is the low voltage TTL
(LVTTL) and a low-amplitude signal such as VIH and VIL. The address buffer is connected to the power supply voltage VDD.
And the ground potential VSS of the circuit, and the output of the first stage circuit is V
The level is converted to a level such as DD and VSS.

Since the internal logic circuits such as the address latch and the address decoder circuit are operated by the step-down voltage VPERI, they have signals such as VPERI and VSS.
The word line (main word line, sub word line) selection signal is a boosted voltage such as VPP, and the non-selection level is VS.
It is set to the ground potential like S. Since the sense amplifier is set to the voltage VDL lower than the step-down voltage VPERI, the bit line potential is set to the corresponding high level and low level. The local input / output line LIO and the main input / output line MIO are also set to signal levels corresponding to the step-down voltage VDL. The selection level of the column selection signal YS is set to a high level corresponding to the step-down voltage VPERI.
The output signal of the main amplifier is also the above-described step-down voltage VPE.
This is an output signal corresponding to RI. Therefore, level conversion from VDL to VPERI is performed by the main amplifier.

In the level shift circuit LS, the high level corresponding to the step-down voltage VPERI is set to the power supply voltage VDD.
Level conversion (amplification) to a high level corresponding to. Therefore, a signal corresponding to the power supply voltage VDD is generated inside the output buffer. In response to such different signal levels in each circuit block, the clock system has a
Divided into types. A clock-system input signal corresponding to the above LVTTL is supplied, the level of which is converted by a first-stage circuit, and a high-amplitude clock ICLK corresponding to the power supply voltage VDD is supplied.
C and clock signals ICLKA and ICLKB corresponding to the reduced voltage VPERI. The clock signals ICLKA and ICLKB are used for address input and internal circuits. The high amplitude clock ICLKC is used for controlling the output timing of the output buffer.

Although not particularly limited, the power supply voltage VDD supplied from the external terminal is set to 3.3 V, the step-down voltage VPERI supplied to the internal circuit is set to 2.5 V, and the operating voltage VDL of the sense amplifier is set. Is set to 2.0V. Then, the word line selection signal (boosted voltage)
It is set to 3.8V. Bit line precharge voltage VBL
R is set to 1.0 V corresponding to VDL / 2, and the plate voltage VPLT is also set to 1.0 V. And the substrate voltage V
BB is set to -1.0V.

FIG. 7 is a circuit diagram showing one embodiment of the clock system circuit. The clock signal CLK supplied from the external terminal passes through the first-stage circuit operated by the power supply voltage VDD, and then receives the clock signals ICLKA to ICCLK.
Logical processing is performed by three types of circuits corresponding to LKC.

Internal clock signals ICLKA and ICLKB
Is a signal of the VDD level formed by the first stage circuit,
Clock signal ICLKA for input buffer control and clock signal ICLKB for internal logic control through a drive circuit such as an inverter circuit operated by the step-down voltage VPERI
Is formed. On the other hand, the internal clock signal ICLKC for controlling the output circuit is output as a high-amplitude clock through a drive circuit such as an inverter circuit operated by the power supply voltage VDD. It should be noted that the internal clocks ICLKA to ICLKC actually correspond to the external clock signal CL.
K is not output by changing the level as it is in the inverter chain, but is subjected to logic processing corresponding to each operation mode and operation timing and is generated for the input buffer control, internal logic control, and output circuit control. Can be

As in the embodiment shown in FIG. 6, the decoders, memory arrays, main amplifiers and the like use the step-down voltages VPERI and VDL in order to lower the voltage and ensure the reliability of the fine device. The read signal MOB from the main amplifier has a signal amplitude corresponding to the step-down voltage VPERI, but the clock signal DOC uses a high amplitude corresponding to the power supply voltage VDD. Therefore, the read signal MOB
Is to perform level conversion (shift) by the level shift circuit LS and perform logical processing with the timing signal DOC. Normally, the signal MOB is formed prior to the timing signal DOC. Therefore, even if the level shift circuit LS is inserted, the signal delay there should not be seen as a delay of Dout. Can be. The path from the clock signal DOC does not require a level shift circuit, so that the access time tAC until Dout is determined can be shortened.

FIG. 8 is a circuit diagram showing another embodiment of the output buffer of the dynamic RAM according to the present invention. In this embodiment, a case where an output latch function is added is shown. The signal MOE is a latch signal. When the signal MOE is at a high level, the output signal M of the main amplifier is output.
O is transmitted to MOL, and when signal MOE is at a low level, MOL is held by a latch circuit including two inverter circuits N8 and N9 whose inputs and outputs are cross-connected. Although not particularly limited, the signal amplitude of the signal MOE is also set to the VDD amplitude.

This embodiment is suitable for circuits around the output of a synchronous DRAM. As is well known, a synchronous DRAM requires a latch circuit for CAS latency control. It is the path from the switch circuit controlled by the signal MOE to the output terminal Dout that determines the clock access time tAC. In this case, a VDD amplitude signal is supplied from a clock system to a gate signal of an analog gate composed of an N-channel type switch MOSFET Q20 and a P-channel type switch MOSFET Q21. Transmit the amplitude signal.

The switch MOSFETs Q20 and Q21
Since the signal amplitudes of the source and drain paths of the above are VPERI amplitudes, a fine device suitable for low voltage can be used. On the other hand, the gate thickness is set so that there is no problem even if the word line boosted voltage VPP or the power supply voltage VDD is applied with one kind of gate thickness tOX, so that the VDD amplitude signal is directly applied to the gate. Can be applied. If you do this,
No level conversion is required in the signal path from the signal MOE. Therefore, the clock access time can be shortened. The access time of the word system and the column system can be controlled by using a level shift circuit with logic composed of gate circuits G3 and G4 for the signals from the memory array and the main amplifier series as in the prior art. At the same time to obtain the VDD amplitude. As a result, the simplification of the circuit can also be realized.

FIG. 9 is a circuit diagram showing one embodiment of a level shift circuit with logic according to the present invention. FIG.
9A shows a NAND gate circuit corresponding to the gate circuit G3 of FIG. 8, and FIG. 9B shows a NOR gate circuit corresponding to the gate circuit G4 of FIG.

In FIG. 9A, the reduced voltage VPERI
, The low-amplitude main amplifier output signal MOL corresponding to N
The gate of the channel type MOSFET Q33 is connected to the source of the N-channel type MOSFET Q31. The gate of the MOSFET Q31 has the step-down voltage VPE
An RI is provided. The pair of MOSFETs Q31 and Q
33, between the drain and the power supply voltage VDD, a P-channel MO having a gate and a drain cross-connected to each other.
SFETs Q30 and Q32 are provided.

In order to implement NAND logic, an N-channel MOSFET Q35 whose drain is connected to the output terminal MIX is provided with an N-channel MOSFET Q35 in series with the output terminal MI.
P-channel MOSFET with drain connected to X
Q32 is provided with a P-channel MOSFET Q34 in parallel. These N-channel MOSFE
An output timing signal D corresponding to the power supply voltage VDD is provided at the gates of the TQ35 and the P-channel MOSFET Q34.
OC is supplied. Note that MOSFETs Q33 and Q35
May be changed up and down.

The operation of this circuit is as follows. The output signal MOL of the main amplifier is at a high level (VPER
In the case of I), the N-channel MOSFET Q31 is turned off and the N-channel MOSFET Q33 is turned on. Therefore, when the timing signal DOC is at a low level, the P-channel MOSFET Q
Irrespective of the latching operation by Q30 and Q32, the output terminal MI is turned on by the P-channel MOSFET Q34 which is turned on by the low level of the timing signal DOC.
X is set to a high level such as the power supply voltage VDD.

When the timing signal DOC changes from a low level to a high level, the P-channel MOSFET
When TQ34 is off, N-channel MOSFET Q
35 is turned on. Therefore, the above signal MOL
Is high level, the output terminal MIX is changed from high level to low level through the MOSFETs Q33 and Q35. If the signal MOL is low level, N
Since the channel type MOSFET Q31 is in the ON state and the N-channel type MOSFET Q33 is in the OFF state, the P-channel type MOSFET Q32 whose gate is supplied with the low level of the signal MOL through the MOSFET Q31 in the ON state causes the output terminal MIX to output from the output terminal MIX. A high level such as the power supply voltage VDD is continuously output.

In FIG. 9B, the reduced voltage VPERI
Is connected to the gate of the N-channel MOSFET Q33 and the source of the N-channel MOSFET Q31 in the same manner as described above. The reduced voltage VPERI is supplied to the gate of the MOSFET Q31. The pair of MOSFEs
P-channel MOSFETs Q30 and Q32 whose gates and drains are cross-connected to each other are provided between the drains of TQ31 and Q33 and the power supply voltage VDD.

In order to implement NOR logic, an N-channel MOSFET Q33 whose drain is connected to the output terminal MIX is connected in parallel to an N-channel MOSFET M33.
An OSFET Q35 'is provided, and a P-channel MOSFET Q3 having a drain connected to the output terminal MIX.
2, a P-channel MOSFET Q34 'is provided in series. These N-channel MOSFETs
An output timing signal DOC corresponding to the power supply voltage VDD is supplied to the gates of Q35 'and the P-channel MOSFET Q34'. Note that MOSFETs Q32 and Q3
The connection may be reversed from 4 ′.

The operation of this circuit is as follows. If the output signal MOL of the main amplifier is low level (0 V), the N-channel MOSFET Q31 is turned on,
N-channel type MOSFET Q33 is turned off. Therefore, when the timing signal DOC is at the high level, the output terminal MIX is turned on by the N-channel MOSFET Q35 'which is turned on by the high level of the timing signal DOC, regardless of the latch operation by the P-channel MOSFETs Q30 and Q32. To a low level like the ground potential VSS.

When the timing signal DOC changes from the high level to the low level, the P-channel MOSFET
When TQ34 'is ON, N-channel MOSFET
Q35 'is turned off. Therefore, the signal M
If OL is low level, N-channel MOSFET Q3
1 is turned on, and the low level of the signal MOL is supplied to the gate of the P-channel MOSFET Q32 to be turned on. Therefore, the output terminal MIX is controlled by the MOSFETs Q32 and Q34 'turned on.
Is changed from a low level to a high level. If the signal MOL is at a high level, an N-channel type MO
When the SFET Q31 is turned off, the N-channel MOSFET
Since the ETQ 33 is turned on, the output terminal MIX
Output a low level like the ground potential VSS.

Such a level shift circuit with logic is shown in FIG.
In this case, the level shift circuit and the logic function can be configured by the same circuit, so that the circuit can be simplified.
Since the number of logic stages inserted in the signal transmission path is reduced as described above, the speed can be increased. Further, if the level shift circuit with the NAND function of FIG. 9A is used for the gate circuits G1 and G2 of FIG. 5, the LS which is merely a level shift circuit can be omitted, so that the output circuit of FIG. The area can be increased.

That is, the timing signal DO as described above
In addition to the output of the signal in synchronization with C, the first input signal having a low amplitude as described above is generally used also when obtaining an output signal whose level is converted by taking the logic of two signals having different levels. By combining the above and the high-amplitude second input signal as described above, a logical output of a logical sum or a logical product can be performed together with the level conversion.

FIG. 10 is a schematic layout diagram of an embodiment of a synchronous DARM (dynamic RAM) to which the present invention is applied. The configurations of the memory array and the sub-array are basically the same as the embodiment of FIG. However, in order to further reduce the area, the main row decoder 11 and the main word driver 12 are collectively provided at the central portion in the longitudinal direction of the chip, and the entire chip is divided into four parts by the peripheral circuit region 14 as described above. Each is assigned to banks 0 to 3. And a synchronous DRAM designated by a command.
Are as follows.

(1) Mode register set command (M
o) A command for setting a mode register included in the input circuit, CSB, RASB, CASB, W
The command is designated by EB = low level, and the data to be set (register set data) are A0 to Ai.
Given through. Here, CSB is a chip select signal, RASB is a row address strobe signal, CASB is a column address strobe signal, WEB is a write enable signal, and B at the end of each signal name is low level active. Indicates that it is a level.

The register set data is not particularly limited, but has a burst length, a CAS latency, a write mode, and the like. Although not particularly limited, the settable burst length is 1, 2, 4, 8, and full page, the settable CAS latency is 1, 2, 3, and the settable write modes are burst write and Single light.

The above-described CAS latency indicates how many cycles of the internal clock signal should be spent from the fall of CASB to the output operation of the output buffer in the read operation specified by a column address read command described later. is there. Internal operation time for data reading is required until the read data is determined,
This is to set it according to the operating frequency of the internal clock signal. For example, when using a high-frequency internal clock signal, the CAS latency is set to a relatively large value, and when using a low-frequency internal clock signal, the CAS latency is set to a relatively small value.

(2) Row address strobe / bank active command (Ac) This corresponds to a row address strobe instruction and A12, A1.
3 is a command for enabling selection of four memory banks by CSB, RASB = low level, CASB,
WEB = instructed by high level, at this time
The address signals A11 to A0 excluding the bits are used as row address signals, and
13 is taken in as a memory bank selection signal. The fetch operation is performed in synchronization with the rising edge of the internal clock signal as described above. For example, when the command is specified, a word line in the memory bank specified by the command is selected, and the memory cells connected to the word line are electrically connected to the corresponding complementary data lines.

(3) Column address read command (Re) This command is a command necessary for starting the burst read operation and a command for giving an instruction of the column address strobe. CSB, CASB =
Instructed by low level, RASB, WEB = high level, the address supplied at this time is taken in as a column address signal. The fetched column address signal is supplied to the column address counter as a burst start address. In the burst read operation designated thereby, the memory bank and the word line in the memory bank are selected in the row address strobe / bank active command cycle, and the memory cell of the selected word line is supplied with the internal clock signal. Are sequentially selected in accordance with the address signal output from the column address counter and are successively read out. The number of data to be continuously read is the number specified by the burst length. The start of reading data from the output buffer is performed after waiting for the number of cycles of the internal clock signal defined by the CAS latency.

(4) Column Address Write Command (Wr) When a burst write is set in the mode register as a mode of the write operation, this is a command necessary to start the burst write operation, and the mode of the write operation When single write is set in the mode register, the command is a command necessary to start the single write operation. Further, the command gives an instruction of a column address strobe in single write and burst write. The command is CSB, CAS
Instructed by B, WEB = low level and RASB = high level, the address supplied at this time is taken in as a column address signal. The fetched column address signal is supplied to the column address counter as a burst start address in burst write. The procedure of the burst write operation instructed in this way is performed in the same manner as the burst read operation. However, there is no CAS latency in the write operation, and the capture of write data is started from the column address / write command cycle.

(5) Precharge command (Pr) This is a command to start a precharge operation for the memory bank selected by the upper two-bit address signal. CSB, RASB, WEB = low level, C
Instructed by ASB = high level.

(6) Auto-refresh command This command is a command required to start auto-refresh, and includes CSB, RASB, and CAS.
Instructed by B = low level, WEB, CKE (clock enable) = high level.

(7) Burst stop in full page command This command is required to stop the burst operation for a full page in all memory banks, and is ignored in burst operations other than the full page. This command is CSB, WEB = low level, RASB, CAS
B = indicated by high level.

(8) No operation command (No
p) This is a command for instructing that no substantial operation is performed. CSB = low level, RASB, CASB, WE
Indicated by the high level of B.

FIG. 11 is a waveform chart for explaining the operation of the synchronous DRAM to which the present invention is applied. FIG. 2 shows a case where the burst length BL = 2 and the CAS latency CL = 2 as an example. The above BL
= 2 and CL = 2 are set in the mode register as described above. As described above, BL = 2 means that reading / writing is performed from two column switches in two continuous cycles, and CL = 2 means that output data is output from the output terminal DQ two cycles after the read command. Output.

In response to a bank active command, a row-related address signal is fetched from an address input terminal (not shown) and decoded to obtain a sub-word line SW.
L is brought to a selection level such as VPP. This allows
A minute read signal appears on the complementary bit lines BL and BLB. Since the sense amplifier is activated by the operation timing signal, the small read signal of the complementary bit lines BL and BLB is amplified to a high level like VDL and a low level like VSS, and the sub-word line SWL is selected. Rewriting (refresh) to the memory cell is performed.

A read command is input after two cycles of bank active, a column address signal (not shown) is fetched, and a column selection signal YS1 rises.
As a result, the main input / output lines MIO and MIOB are precharged to the VDL level until immediately before the column selection, and 100 to 15 bits are determined according to the bit line information of the YS selection.
A voltage difference of 0 mV is obtained and amplified by a main amplifier activated by a signal MAE to form an output signal MO. Since the output signal MO of the main amplifier is a low-amplitude signal corresponding to the step-down voltage VPERI as described above, the level is shifted at the input portion of the output buffer to the VDD level as in the embodiment of FIG. 5 or FIG. Convert,
It is output in synchronization with the output timing signal DOC. When BL = 2, the clock C following the read command
The Y-system address is switched in synchronization with LK, and the output signal MO of the main amplifier is formed correspondingly.

The access time from the bank active command until the first output signal DQ is determined is tRACe
q, the access time from the read command to the determination of the output signal DQ is tAAeq, and the access time from the clock signal CLK to the determination of the output signal DQ is tAC. Since the present invention uses a high-amplitude signal of the VDD level for the latency control signal MOE and the output control signal DOC, the time required for level conversion can be omitted, and as a result, the access time tAC can be reduced. Then, by the control using the high-amplitude signal as described above, the current flowing through the MOSFET driven thereby can be increased, and the signal delay there can be reduced, thereby contributing to an increase in speed. Therefore, the cycle of the clock signal CLK can be shortened accordingly, and the speed of the synchronous DARM can be increased.

The embodiment shown in FIG. 5 and the embodiment shown in FIG. 8 both output signals (MOB, MOL) having a small amplitude corresponding to the internal low potential (VPERI) to the external voltage (VD
This is effective for speeding up when converting into a large-amplitude signal (MOH, S1) corresponding to D) and outputting the signal (Dout) to the outside. The common points in these embodiments are as follows. That is, before the timing signal (DOC) for outputting data to the outside becomes active, a signal corresponding to the low potential (VPERI) is applied to the external voltage (VDD).
D) corresponding to a timing signal (DO) for outputting data to the outside.
C) becomes active after the signal (Do)
Since the time for converting the signal level is not included in the period until ut) is output, high-speed output is possible.

In particular, the present invention is effective when the low-amplitude output signal from the main amplifier reaches the output circuit or its vicinity and is output to the outside at high speed in response to the internal timing signal. Since the main amplifier and the output circuit are often connected via relatively long wiring, it is better to transmit the output signal from the main amplifier to the output circuit or its vicinity with low amplitude, to reduce power consumption Effective for

FIG. 12 is a circuit diagram of another embodiment of the level shift circuit with logic according to the present invention. The circuit of this embodiment is a modified example of the circuit shown in FIG. 9B, and a MOSFET Q36 is added. Signal M
A MOSFET Q36 is provided to cut an undesired current generated when OL is at a low level and the timing signal DOC changes to a high level. That is,
A MOSFET Q36 is provided to prevent an undesired current from flowing from the power supply VDD to the signal MOL via the MOSFETs Q30 and Q31.

FIG. 13 is a circuit diagram showing another embodiment of the level shift circuit with logic according to the present invention. The circuit of this embodiment is a two-input NAN shown in FIG.
This is a modification of the D circuit, and has three inputs (IN1, IN2, IN
3) Constituting a NAND circuit. That is, MOSFETs Q37 and Q3 for receiving the timing signal IN3
8 has been added.

FIG. 14 is a circuit diagram showing another embodiment of the level shift circuit with logic according to the present invention. The circuit of this embodiment is a modification of the two-input NOR circuit shown in FIG.
An OR circuit is configured. That is, the timing signal I
MOSFETs Q39 and Q40 for receiving N3 are added.

The effects obtained from the above embodiment are as follows. That is, (1) an internal circuit that receives a power supply voltage supplied from an external terminal and operates at a stepped-down voltage, and an output that outputs a signal to be output formed by the internal circuit through an external terminal according to a timing signal. In the semiconductor integrated circuit device provided with a circuit, the signal to be output formed by the internal circuit corresponds to a power supply voltage while reducing power consumption and increasing the reliability of the element by using the step-down voltage. The level conversion operation is made invisible by the output circuit using a timing signal having a voltage level corresponding to the power supply voltage supplied from the external terminal by the output circuit. Therefore, the effect that the operation can be speeded up can be obtained.

(2) Of the input circuit, an input circuit for receiving a clock signal supplied from the external terminal and a clock distribution circuit for generating a clock signal supplied to the output circuit are supplied from the external terminal. By setting the power supply voltage to the operating voltage, the output signal can be output at a high speed corresponding to the clock signal because there is no level conversion in the path for generating the internal clock signal.

(3) Since the input circuit is operated by the power supply voltage supplied from the external terminal, an effect that the input / output interface can correspond to the power supply voltage can be obtained.

(4) The logic section for transmitting the signal to be output in accordance with the timing signal included in the output circuit and the level shift circuit are complemented in correspondence with the signal to be output formed in the internal circuit. First and second N-channel MOSs that perform a switching operation
FET and the first and second N-channel type MOSFs
First and second P-channel MOSFETs provided between a drain of the ET and a power supply voltage supplied from an external terminal and having a gate and a drain cross-connected to each other; N-channel type M
A third N-channel MOSFET connected in series (or in parallel) with a drain connected to the output terminal of the OSFET, and a cross-connected P-channel MOSFET
A third P-channel type M connected in parallel (or in series) with the SFET whose drain is connected to the output terminal
The use of the level shift circuit with logic including the OSFET has an effect that the circuit can be simplified.

(5) As the level shift circuit with logic, a signal to be output formed by the internal circuit is supplied to the gate of the first N-channel MOSFET, and the gate of the second N-channel MOSFET is supplied to the gate of the first N-channel MOSFET. The gate is supplied with the internal step-down voltage, the source is supplied with a signal to be output formed by the internal circuit, and the drain of the first N-channel MOSFET is connected to the output terminal. This has the effect of simplifying the circuit and reducing the number of signal wirings because the signal to be output can be formed by a single-ended amplifier circuit.

(6) An address selection MOSFET having a gate connected to a word line, one source and drain connected to a bit line crossing the word line, and the other source and drain connected to a storage node of a storage capacitor.
A dynamic memory cell consisting of: an amplification MOSFET of a sense amplifier that amplifies a minute voltage according to the information charge of the storage capacitor read to the bit line;
A memory array including a precharge MOSFET for applying a precharge voltage to the bit line, a column switch MOSFET for selecting the bit line, a decoder for forming a signal for selecting the word line and the bit line, and a selection through the column switch In a dynamic RAM including a main amplifier that reads stored information of a memory cell, a first operating voltage formed by the step-down circuit is supplied to the decoder and the main amplifier. , Formed by the step-down circuit,
By supplying the second operating voltage lower than the first operating voltage, low power consumption and high reliability are achieved, and high-speed operation is realized by providing the output buffer as described above. The effect that it can be obtained is obtained.

(7) The word line includes a main word line and a plurality of sub-word lines commonly assigned to the main word line, and connects the gates of the address selection MOSFETs of the dynamic memory cell. One of the plurality of sub-word lines is selected by a sub-word driver receiving the signal of the main word line and the signal of the sub-word selection line, and the sub-word driver is also included in the memory array, thereby achieving high integration. Thus, an effect that a high capacity dynamic RAM can be obtained can be obtained.

(8) Low power consumption and high reliability are achieved by using an internal circuit that receives a power supply voltage supplied from an external terminal and operates at a stepped down voltage. As a logic unit for performing a logical process of one signal and a second signal corresponding to a power supply voltage supplied from an external terminal, a pair of first and second pairs that perform a switching operation complementarily in response to the first signal N-channel type M
OSFET and the first and second N-channel type MOs
First and second P-channel MOSFETs provided between a drain of an SFET and a power supply voltage supplied from an external terminal and having a gate and a drain cross-connected to each other; A pair of N-channel MOs
A third N-channel MOSFET connected in series with an SFET having a drain connected to the output terminal
And the second signal is received by the gate and is cross-connected to P
Since the channel type MOSFET is configured with the third P-channel type MOSFET connected in parallel with the drain connected to the output terminal, the logic function and the level conversion operation can be performed with a simple circuit. The effect is obtained.

(9) First N-channel MOS
The first signal is supplied to the gate of the FET and the second N
The step-down voltage is supplied to the gate of the channel type MOSFET, the first signal is supplied to the source, and the first signal is supplied to the source.
By connecting the drain of the N-channel MOSFET to the output terminal, the effect of simplifying the circuit and reducing the number of signal wirings can be obtained because the signal to be output can be formed by a single-ended amplifier circuit. Can be

The invention made by the present inventor has been specifically described based on the embodiment. However, the invention of the present application is not limited to the above embodiment, and various modifications can be made without departing from the gist of the invention. Needless to say. For example, in the dynamic RAM shown in FIG. 1 or FIG. 10, the configurations of the memory array, the sub-array, and the sub-word driver can adopt various embodiments, and may be a word shunt system without using a sub-word driver.

FIG. 9A shows a level shift circuit with logic.
In (B), N-channel MOSFETs Q31 and Q31
The configuration may be such that complementary input signals MO and MOB are supplied to the 33 gates. The clock signal is the power supply voltage VD.
Instead of the D level itself, a slight step-down may be performed to the extent that level conversion is not necessary in the subsequent stage. For example, such a slight step-down can be easily realized by using the source side voltage of the N-channel MOSFET in which the boosted voltage VPP is applied to the gate and the power supply voltage VDD is applied to the drain.

As the device for outputting data corresponding to the clock signal, any device can be used as long as it performs the same operation as that of the dynamic RAM. That is, the present invention includes an output circuit that performs an output operation in response to a timing signal or an internal circuit that operates by an internal voltage down converter, and converts the output to a level corresponding to an external power supply voltage and outputs the converted signal. Widely used in semiconductor integrated circuit devices.

[0106]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, an internal circuit that receives a power supply voltage supplied from an external terminal and operates at a stepped-down voltage, and an output circuit that outputs a signal to be output formed by the internal circuit through an external terminal according to a timing signal. In a semiconductor integrated circuit device provided with the above-described step-down voltage, a signal to be output formed in the internal circuit is converted into a signal level corresponding to a power supply voltage while reducing power consumption and increasing the reliability of elements by using the step-down voltage. And keep
The level conversion operation can be made invisible by causing the output circuit to output using a timing signal of a voltage level corresponding to the power supply voltage supplied from the external terminal, so that the operation can be speeded up. .

Upon receiving a power supply voltage supplied from an external terminal,
A low power consumption and high reliability are attained by using an internal circuit that can be operated at a voltage stepped down from the second circuit. A pair of first and second N-channel type Ms that perform a switching operation complementarily in response to the first signal signal as a logic unit that performs logical processing on a signal.
OSFET and the first and second N-channel type MOs
First and second P-channel MOSFETs provided between a drain of an SFET and a power supply voltage supplied from an external terminal and having a gate and a drain cross-connected to each other; A pair of N-channel MOs
A third N-channel MOSFET connected in series with an SFET having a drain connected to the output terminal
And the second signal is received by the gate and is cross-connected to P
By configuring the channel type MOSFET with the drain connected to the output terminal and the third P-channel type MOSFET connected in parallel, the logic function and the level conversion operation can be performed by a simple circuit. .

[Brief description of the drawings]

FIG. 1 is a schematic layout diagram showing one embodiment of a dynamic RAM to which the present invention is applied.

FIG. 2 is a schematic layout diagram for explaining a dynamic RAM to which the present invention is applied;

FIG. 3 is a schematic layout diagram showing one embodiment of a sub-array and its peripheral circuits in a dynamic RAM according to the present invention.

FIG. 4 is a circuit diagram showing a simplified embodiment from address input to data output centering on the sense amplifier section of the dynamic RAM according to the present invention.

FIG. 5 is a circuit diagram showing one embodiment of an output buffer of a dynamic RAM according to the present invention.

6 is a potential distribution diagram showing signal levels corresponding to operation voltages of respective circuits corresponding to the operation order of the dynamic RAM shown in FIG. 5;

FIG. 7 is a circuit diagram showing one embodiment of the clock system circuit of FIG. 6;

FIG. 8 is a circuit diagram showing another embodiment of the output buffer of the dynamic RAM according to the present invention.

FIG. 9 is a circuit diagram showing one embodiment of a level shift circuit with logic according to the present invention.

FIG. 10 is a schematic layout diagram showing an embodiment of a synchronous dynamic RAM to which the present invention is applied.

11 is a synchronous dynamic RAM of FIG.
FIG. 6 is a waveform chart for explaining an example of the operation of FIG.

FIG. 12 is a circuit diagram showing another embodiment of the level shift circuit with logic according to the present invention.

FIG. 13 is a circuit diagram showing another embodiment of the level shift circuit with logic according to the present invention.

FIG. 14 is a circuit diagram showing another embodiment of the level shift circuit with logic according to the present invention.

[Explanation of symbols]

10: memory chip, 11: main row decoder area,
12: Main word driver area, 13: Column decoder area, 14: Peripheral circuit, bonding pad area, 1
5 Meseli cell array (subarray), 16 Sense amplifier area, 17 Subword driver area, 18 Cross area (cross area), 51 Address buffer, 52
... Predecoder, 53 ... Decoder, 61 ... Main amplifier, 62 ... Output buffer, 63 ... Input buffer, LS ...
Level shift circuits, G1 to G4 gate circuits, N1 to N
13: Inverter circuit, QP: P-channel type output MO
SFET, QN ... N-channel type output MOSFET, Q
1 to Q35: MOSFET.

Claims (14)

[Claims] A step-down circuit for stepping down a power supply voltage supplied from an external terminal; an input circuit receiving an input signal supplied from an external terminal; an internal circuit operating with an internal voltage formed by the step-down circuit; An output circuit that outputs a signal through an external terminal according to a timing signal; and a level shift circuit that converts a signal to be output formed by the internal circuit into a signal level corresponding to a power supply voltage level supplied from the external terminal. Wherein the timing signal has a signal level corresponding to a power supply voltage level supplied from the external terminal, and the output circuit outputs a signal converted by the level shift circuit. Integrated circuit device. 2. The circuit according to claim 1, further comprising a timing signal generation circuit for forming the timing signal based on a clock signal supplied from an external terminal, wherein the input circuit and the timing signal generation circuit are connected to the external circuit. A semiconductor integrated circuit device wherein a power supply voltage supplied from a terminal is used as an operating voltage. 3. The semiconductor integrated circuit device according to claim 1, wherein the input circuit is operated by a power supply voltage supplied from an external terminal. 4. The level shift circuit according to claim 1, wherein the level shift circuit is constituted by a level shift circuit with logic, and the level shift circuit with logic is formed by the internal circuit. A first and a second N, which comprise a pair that performs a switching operation complementarily in accordance with a signal to be output.
A channel type MOSFET, and first and second N-channel type MOSFETs provided between a drain of each of the first and second N-channel type MOSFETs and a power supply voltage supplied from an external terminal. P channel type M
An OSFET, a third N-channel MOSFET M connected to the gate of the N-channel MOSFET receiving the timing signal and having an output terminal connected to the drain of the pair of N-channel MOSFETs;
OSFET and the cross-connected P-channel type MO
A semiconductor integrated circuit device comprising a third P-channel MOSFET connected in parallel with one of the SFETs having a drain connected to an output terminal. 5. The level shift circuit according to claim 1, wherein the level shift circuit is configured by a level shift circuit with logic, and the level shift circuit with logic is formed by the internal circuit. A first N-channel MOSFET receiving a signal to be output at its gate; a second N-channel MOSFET receiving the internal step-down voltage at its gate and receiving at its source the signal to be output formed by the internal circuit; First and second P-channel MOSFETs provided between a drain of the first and second N-channel MOSFETs and a power supply voltage supplied from an external terminal, and having a gate and a drain cross-connected to each other; A third N-channel type M which receives the timing signal at its gate and is connected in series with the first N-channel type MOSFET. An OSFET and a third P-channel MOSFET connected in parallel with the cross-connected P-channel MOSFET whose drain is connected to the output terminal.
A semiconductor integrated circuit device comprising an SFET. 6. The internal circuit according to claim 1, wherein the gate is connected to a word line, and one of the source and the drain intersects the word line. A dynamic memory cell comprising an address selection MOSFET connected to the bit line and having the other source and drain connected to the storage node of the storage capacitor; and a micro memory cell according to the information charge of the storage capacitor read to the bit line. A memory array including an amplification MOSFET of a sense amplifier for amplifying a voltage, a precharge MOSFET for applying a precharge voltage to the bit line, and a column switch MOSFET for selecting the bit line; and a signal for selecting the word line and the bit line. And a pre-decoder and a decoder forming the A first operating voltage formed by the step-down circuit is supplied to the predecoder, the decoder, and the main amplifier; and the step-down circuit is supplied to an amplification MOSFET of the sense amplifier. And a second operating voltage lower than the first operating voltage is supplied to the semiconductor integrated circuit device. 7. The dynamic memory according to claim 6, wherein the word line comprises a main word line and a plurality of sub-word lines commonly assigned to the main word line. A gate of an address selection MOSFET of a cell is connected; one of the plurality of sub-word lines is selected by a sub-word driver receiving a signal of the main word line and a signal of a sub-word selection line; A semiconductor integrated circuit device, wherein a driver is also included in the memory array. 8. A step-down circuit for stepping down a power supply voltage supplied from an external terminal, an input circuit receiving an input signal supplied from an external terminal, an internal circuit operated by an internal voltage formed by the step-down circuit, An output circuit operable with a power supply voltage supplied from the external terminal to output a signal to be output formed in an internal circuit through the external terminal, the output circuit comprising: a first signal formed by the internal circuit; And a logic unit for performing a logic process on a second signal corresponding to a power supply voltage supplied from an external terminal, wherein the logic unit comprises a pair of a pair that performs a complementary switching operation in response to the first signal. First and second N-channel MOSFETs and such first and second N-channel MOSFETs
First and second P-channel MOSFETs provided between a drain of an OSFET and a power supply voltage supplied from an external terminal and having a gate and a drain cross-connected to each other; A third N-channel MOSFET connected in series with one having a drain connected to the output terminal of the pair of N-channel MOSFETs;
ET and a third P-channel MOSFET connected in parallel with the cross-connected P-channel MOSFET whose drain is connected to the output terminal among the cross-connected P-channel MOSFETs receiving the second signal at the gate. Semiconductor integrated circuit device. 9. The N-channel MOSFET according to claim 8, wherein the first signal is supplied to a gate of the first N-channel MOSFET.
The step-down voltage is supplied to the gate of the ET, the first signal is supplied to the source, and the first N-channel type MO is supplied.
A semiconductor integrated circuit device comprising a drain of an SFET connected to the output terminal. 10. A step-down circuit for stepping down a first voltage supplied from a first terminal, an input circuit receiving an input signal supplied from a second terminal, and operating with a second voltage formed by the step-down circuit. An internal circuit; and an output circuit for outputting a signal to be output formed by the internal circuit through a third terminal in accordance with a timing signal. The signal is converted to a signal level corresponding to one voltage level and supplied to the output circuit. The output circuit receives a timing signal of a voltage level corresponding to the first voltage, and outputs a signal passed through the level shift circuit. A semiconductor integrated circuit device. 11. The input circuit according to claim 10, wherein the timing signal is formed according to a clock signal supplied from a fourth terminal, and an input of the input circuit receiving the clock signal supplied from the fourth terminal. And a clock distribution circuit for generating a clock signal to be supplied to the output circuit, wherein the first voltage is used as an operation voltage. 12. The semiconductor integrated circuit device according to claim 10, wherein the input circuit is operated by a first voltage. 13. The level shift circuit according to claim 10, wherein the logic unit included in the output circuit and the level shift circuit are configured by a level shift circuit with logic, and the level shift circuit with logic is formed by the internal circuit. First and second N pairs of a pair that perform a switching operation complementarily in response to a signal to be output
A first and second N-channel MOSFETs provided between a drain of the first and second N-channel MOSFETs and a first voltage supplied from a first terminal, and having a gate and a drain cross-connected to each other; 2 P-channel type M
An OSFET, and a third N-channel MOSFET connected to one of the pair of N-channel MOSFETs having a drain connected to an output terminal, the gate receiving the timing signal.
ET and the cross-connected P-channel MOSFET
A semiconductor integrated circuit device comprising a third P-channel MOSFET connected to a transistor having a drain connected to an output terminal of T. 14. An output circuit that operates by receiving a first power supply voltage, and an internal circuit that operates by receiving a second power supply voltage lower than the first power supply voltage, wherein the output circuit is formed by the internal circuit. A pair of first and second N-channel MOSFETs that perform a switching operation in a complementary manner in response to the supplied signal, drains of the first and second N-channel MOSFETs, and a first power supply voltage are supplied. And a second P-channel MOSFET having a gate and a drain cross-connected to each other.
An output terminal; a third N-channel MOSFET which receives the timing signal of the first power supply voltage level at its gate, and is connected in series with one of the pair of N-channel MOSFETs whose drain is connected to the output terminal. And a third P-channel MOSFET that receives the timing signal at its gate and that is connected in parallel with the cross-connected P-channel MOSFET whose drain is connected to the output terminal. A semiconductor integrated circuit device characterized by the above-mentioned.