JPH11339467A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a semiconductor apparatus which can make a DRAM and a logic circuit in one chip, test a self refresh circuit in a short time, optimize a self refresh cycle by trimming and relieve failures. SOLUTION: At the time of a self test, an internal self refresh control signal as an output of a self refresh circuit is output to a row selection control signal. In the drawing, the row selection control signal is input to a selector 312. Since a self test signal is 'H', the row selection control signal is output from the selector 312 and input to a selector 313. Since a DRAM test signal is 'H', an A input is selected at the selector 313, whereby the row selection control signal is input to a tristate buffer 317. With the self test signal being 'H', an IO control signal (1) is turned to 'H' and the row selection control signal is output to an external input/output terminal (0).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which a memory requiring refresh, that is, a dynamic random access memory (hereinafter abbreviated as DRAM) and a logic circuit are integrated into one chip.

[0002]

2. Description of the Related Art In a DRAM in which a memory cell is formed by a capacitor, after a certain period of time, data stored in the memory cell as charges is lost due to a leak current. Therefore, it is necessary to perform a refresh operation in order to rewrite and maintain the data held in the memory cell. A refresh operation in a DRAM is performed by selecting a row line (word line) for one row in a memory matrix composed of a plurality of rows and columns included in a memory cell, and then reading out all memory cells on the word line. This is realized by sequentially performing the operation of performing amplification and rewriting on all the word lines.

[0003] The refresh operation of the DRAM includes a refresh operation interrupted during a random access operation such as reading / writing of data from / to a memory cell, and a period during which the DRAM is in a data holding mode without a random access operation, for example, by a battery. There is a refresh operation performed during the backup period.

The former, that is, the refresh operation performed by interrupting during the access operation, has two methods. One is a RAS-only refresh method in which a row address for refresh is given from an external refresh address counter, and refreshing is performed during a period from a fall to a rise of a row address strobe signal / RAS. The other is an auto-refresh method in which a refresh request signal is supplied from the outside and a row address is switched from an external address to a refresh address counter built in the DRAM to perform refresh. At present, the auto refresh method uses a column address strobe signal /
CAS, row address strobe signal / RAS in order of Lo
A CAS-before-RAS refresh (hereinafter abbreviated as CBR refresh), which performs w-level “L” and performs refresh between the fall and the rise of the row address strobe signal / RAS, is a standard specification.

In the latter case, that is, in the refresh operation in the data holding mode, external refresh is performed by using the output of a built-in refresh address counter as a row address in response to a refresh request signal automatically generated by an internal timer. There is a self-refresh method in which refresh is continuously performed at a constant cycle without applying a control signal. At present, as a self refresh method, a row address strobe signal / RAS and a column address strobe signal / CA are used in CBR refresh.
CBR self-refresh is a standard specification, in which a self-refresh operation is started by keeping both S at "L" for 100 μsec or more.

[0006]

However, according to the above-mentioned conventional configuration, a signal for checking the self-refresh circuit for generating a refresh request signal at the time of self-refresh is not output to the external terminal. To detect circuit failure, write data to the memory, then enter self-refresh mode, and wait for more than the time that data held in the memory cell will leak and be lost if not refreshed. In order to test whether the data has been lost, the test time becomes longer, the pulse width of the refresh request signal cannot be checked, and the refresh cycle during self-refresh cannot be checked. Of the refresh cycle by trimming Optimization is the pulse width or refresh period and a problem that can not be had a problem that it is impossible to make the pulse width or period by trimming at the time of non-standard in the standard. In view of the above conventional problems, the present invention is a semiconductor device in which a memory requiring refresh, that is, a DRAM and a logic circuit are integrated into one chip, and the test of the self refresh circuit can be performed in a short time. An object of the present invention is to provide a semiconductor device capable of optimizing a self-refresh cycle by trimming and relieving a defective product.

[0007]

SUMMARY OF THE INVENTION In order to solve this problem, a semiconductor device according to the present invention comprises a memory having a memory cell which needs to be refreshed for storing data, and a self-refresh control signal. Oscillating means for supplying an oscillating clock having a fixed period, signal generating means for supplying an internal self-refresh control signal for refreshing the memory cell based on the oscillating clock, By providing a signal output means for outputting a control signal to an external terminal, a refresh cycle at the time of self-refresh can be checked.

Thus, a test of the self-refresh circuit can be performed in a short time, and a semiconductor device capable of optimizing a self-refresh cycle by trimming and relieving a defective product can be realized.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a semiconductor device according to a first embodiment of the present invention will be described with reference to the drawings.

FIG. 1 shows a configuration of a semiconductor device according to the first embodiment of the present invention. In FIG. 1, a memory cell and a peripheral circuit 3 are a memory array composed of a plurality of memory cells and a block composed of peripheral circuits, a logic unit 4 is a block composed of a microcomputer or logic, and a refresh counter 224 is a Counter circuit for generating a row address at the time of refresh, 210 to 210
214, 230, 231 are inverter circuits;
Reference numeral 18 denotes a D flip-flop (hereinafter abbreviated as DFF), and selectors 201 to 208 and 229 select the B input when the S input is "H". Row address latch 225, column address latch 226, byte address latch 227
Is a circuit that latches an input signal at the rising edge of the clock (2) when the EN input is “H”. The test decode circuit 228 is a circuit that decodes a plurality of external test input terminals and determines a test mode of the DRAM 2.

FIG. 2 is a configuration diagram of the memory cell array and the peripheral circuit 3 of FIG. Memory cells M01 to MN2m
Is a storage element for storing 1-bit data in a capacity. The memory cell array 300 is storage means having memory cells M01 to MN2m of N rows × 2m columns.
The memory cell array 300 reads and writes data by using word lines WL1 to N, which are N row selection lines, and bit lines (1) to 2m, / bit lines (1) to 2m, which are 2m pairs of bit pairs. Is executed. The row selection circuit 301 receives a row selection control signal, and selects a word line WL based on the received row address.
This is row selection means for applying a pulse to the selected word line WL. The sense amplifiers SA1 to SA2m are amplifying means for amplifying a minute voltage difference between the bit lines and the / bit lines, and Pch transistors T01 to T0 (2m) and T11.
To T1 (2m) are bit lines according to a row selection control signal,
A switching means for applying a precharge voltage to the / bit line to precharge each bit line and / bit line. Pch transistors T21 and T2 (2 m)
Is switching means for equalizing each bit line and / bit line according to a row selection control signal. Nch
Transfer gates TG01 to TG0 (2m), TG
11 to TG1 (2m) are switching means for connecting the bit lines and / bit lines amplified by the sense amplifiers to the main bit lines and / main bit lines of the main amplifiers MA0 to MA.

FIG. 3 is a circuit diagram of the self-refresh circuit 2 shown in FIG.
It is a detailed explanatory view of 50. In FIG. 3, the oscillation circuit 25
1 indicates that the received self refresh control signal is "H"
In the case of (1), it is an oscillating means for supplying the clock CLK1. The two-frequency dividers 268, 269, and 270 are frequency dividing means for sequentially dividing the frequency of the received clock CLK1 and supplying the frequency-divided clocks CLK2, CLK4, and CLK8, respectively. The selector 271 selects the divided clock CLK8 when the clock selection signal is “H”, and selects the divided clock CLK8 when the clock selection signal is “L” to divide the clock. It is a selection unit for supplying the signal CKO. One shot pulse generation circuit 274
According to the rising edge of the received frequency-divided signal CKO,
This is a pulse generation unit for generating a set pulse SETP having a predetermined pulse width. Set reset circuit 2
Reference numeral 75 denotes a signal generation unit for supplying a self-refresh signal SRO in accordance with the received set pulse SETP and reset pulse RSTP.

The first delay circuit 276 is a delay means for supplying a reset pulse RSTP obtained by delaying the received internal self-refresh signal for a predetermined time to the reset terminal of the set / reset circuit 275.

The operation of the DRAM 2 incorporated in the semiconductor device 1 according to the first embodiment during a data read test will be described below. At the time of testing, a signal is input from an external input terminal to test the DRAM 2 alone.

First, an operation of selecting an input signal during a data read test will be described with reference to FIG. In FIG. 1, when the data read test mode is set by the external test input terminal, the DRAM test signal is set to the high level by the test decode circuit 228, so that the selector 201 to the selector 208 select the B input. . Therefore, the external input terminal (1) is input to the clock (2), the external input terminal (2) is input to the / self-refresh control signal (2), and the / auto-refresh control signal (2) is input to the / auto-refresh control signal (2). , External input terminal (3)
, An external input terminal (4) is input to the / row selection control signal (2), an external input terminal (5) is input to the / column selection control signal (2), and a / write control signal (2)
, An external input terminal (6) is input, and an external input terminal (7) is input to both the row address 2 and the column address (2).

Here, as an address input of the DRAM,
The row address (2) and the column address (2) are both input from the external input terminal (7), which are shared in order to reduce the number of external terminals at the time of the test. A multiplexed address signal is supplied to an external input terminal (7), and is separated into a row address and a column address in the DRAM 2.

The read operation at the time of testing the DRAM 2 will be described with reference to the timing charts of FIGS. 1, 2 and 4.

A read operation in the page mode during a data read test of the DRAM 2 will be described with reference to a timing chart of FIG. 4 and FIGS. At time t0 in FIG. 4, since the / self-refresh control signal (2) is at the high level, the internal self-refresh control signal which is the output of the self-refresh circuit is at the low level and the / auto-refresh control signal (2), as will be described later. Is clocked by the DFF 215 of FIG.
The internal auto-refresh control signal synchronized with
ow level // row selection control signal (2) to DFF2 in FIG.
16, the internal row selection control signal synchronized by the clock (2) is at the low level, so that the row selection control signal output from the OR circuit 222 is at the low level, and Pc
h transistors T01 to T0 (2 m), T11 to T1 (2
m), T21 and T2 (2m) are turned on, and the bit line (1)
２2 m, / bit lines (1) 〜2 m are precharged and equalized to Ｖ Vdd.

At time t1 in FIG. 4, when the row selection control signal (2) falls from the High level to the Low level, the row selection control signal rises from the Low level to the High level, and the Pch transistors T01 to T0 (2
m), T11-T1 (2m), T21-T2 (2m) are OF
F, bit lines (1) to 2 m, / bit lines (1) to 2
m, the precharge and equalization are stopped, and at the rising edge of the clock (2) at time t1, the latch enable signal of the row address latch 225, which is the output signal of the inverter 214, is at the high level. The address (2) is latched by the clock (2) and a row address is output. Internal self-refresh control signal and internal auto-refresh control signal are Low
Therefore, the output of the NOR circuit 221 / the internal refresh control signal becomes High level, and the row address (3) which is the B input of the selector 229 is selected and output to the row address.

In FIG. 2, since the row selection control signal is at the high level, the row line WLn selected by the row address goes to the high level, and the delay circuit (2) -303 enables the sense amplifier enable. The level goes high after a delay from time t1, the sense amplifiers SA1 to SA2m are activated, and the data of the memory cell connected to WLn is read to bit lines (1) to 2m and / bit lines (1) to 2m. Issued and sense amplifier SA1
ＳＡSA2m.

Since the internal refresh control signal is at the high level, the row selection control signal is at the high level. In this embodiment, the row address (0), which is one bit in the row address, is at the low level. AND circuit 30
As shown in FIG. 4, the gate enable (0), which is the output of the output of the AND circuit 307, becomes High level with the delay time of the delay circuit (3) -304 delayed from the rise of the row selection control signal. Since a certain gate enable (1) is at a low level, the odd-numbered transistors TG01, TG11, TG03, TG13, TG0
5, TG15 ... TG0 (2m-1), TG1 (2m-
1) is turned on, and the odd-numbered sense amplifiers S1, S3,
S5: The output of S (2m-1) is the main amplifier MA1
When the voltage difference between the main bit line and the / main bit line, which are input to 〜MAm and output from the sense amplifier, becomes large, the differential amplification of the main amplifiers MA1 to MAm starts, as shown in FIG. So that the main amplifiers MA1 to MAm
Thus, MOUT1 to MOUTm are output.

At time t2, since both the row selection control signal (2) and the column selection control signal (2) are at the low level, the outputs of the inverters 211 and 212 in FIG.
Level, the output of the AND gate 219 becomes High.
Since the level becomes the h level, the column address latch 226 is latch-enabled, and at time t2, the column address (2) is latched at the rising edge of the clock, and the column address is output. Similarly, byte address latch 227
Also latches the byte address (1) at the rise of the clock and outputs the byte address. As shown in FIG. 2, the column selection circuit 302 outputs m of MOUT1 to MOUTm.
The data output signal of 8k bits selected by the column address (3) from the bit data is output to the data selection circuit 308.
And the data selection circuit 308 selects the 8-bit test data from the 8 k-bit data output signal based on the byte address, and outputs the test data (7: 0).
Is output as The test data (7: 1) of the test data (7: 0) is output to the selector 309, and the test data (0) is output to the selector 312. D
Since the RAM test signal is at a high level, the output of the inverter 314 is at a low level.
Reference numeral 09 denotes the A-input test data (7: 1) which is output to the tri-state buffer 310. At time t2, the / row selection control signal (2) and the / column selection control signal (2) are at the low level, and the / write control signal 2 is at the high level.
Since the level is at the high level, the AND circuit 220 goes to the high level, and the timing generation circuit 223 sets the output control signal to the high level at the timing shown in FIG. 4 by the output of the AND circuit 220 and the clock (2). Output control signal is High level, inverter 31
4 is at a low level, the IO control signal (1) output from the OR circuit 315 becomes a high level,
The test data (7: 1) is output to the external input / output terminal (7: 1).

Since the self test signal is at a low level,
The selector 312 outputs test data (0), which is an A input, to the selector 313. The output of inverter 314 is L
Since the level becomes the low level, the selector 313 outputs the test data (0), which is the output of the selector 312, which is the A input, to the tri-state buffer 317. As described above, since the IO control signal (1) is at the high level and the self-test signal is at the low level, the IO control signal (0) output from the OR circuit 316 is at the high level. Output to the input / output terminal (0). The test data (7: 0) is supplied to an external input / output terminal (7:
0) is output at the timing shown in FIG.

At times t3, t4 and t5, time t2
At the rise of the clock (2), the / row selection control signal (2) and the / column selection control signal (2) are both at the low level and the / write enable signal is at the high level, as in the case of (1). As shown in the timing chart of FIG. 4, the data of the memory cell selected by the latched column address and byte address are sequentially output to the external input / output terminals (7:
Read it out to 0). At time t6, since the / row selection control signal (2) and / column selection control signal (2) are at the high level, the output of the AND circuit 220 goes to the low level, so that the output control signal goes to the low level, and the IO control signal Since (0) and (1) become Low level, the output of the external input / output terminal (7: 0) becomes high impedance.

Next, the operation at the time of the self test for testing the self refresh operation will be described below. First, the operation of the self-refresh circuit of FIG. 3 will be described with reference to the timing chart of FIG.

During a period from time 0 to t0, the / row selection control signal (2) and the / auto refresh control signal (2) are initialized to "H" by the external input terminal, and the / self refresh control signal (/ 2) When “H” is supplied, the self-refresh control signal becomes “H” and N
Since one input of the AND circuit 257 becomes "L", the output signal S4 thereof becomes "H", and the PMOS transistor 254 turns on, so that the signal S1 of the input of the inverter 11 becomes "H". Therefore, the oscillation capacitor 2
The signals S0 and S3 at both ends of 59 and 260 are forcibly initialized to "H", that is, the power supply voltage Vdd, and the oscillation is stopped. When the self-refresh control signal is "L"
Therefore, the frequency-divided clocks CLK2, CLK4, and CLK8 output from the two-frequency dividers 268, 269, and 270 are all initialized to "L".

Here, at time t0, when the self-refresh control signal is set to "H" by the external input terminal (2) and supplied, the DRAM 2 enters the self-refresh mode. In this case, signal S3 at time t0
Of the NAND circuit 257 at time t0.
Signal S4, which is the output of NAND circuit 257, becomes "L" because the self-refresh control signal, which is one input of the self-refresh signal, becomes "H". Therefore, the oscillation clock CLK1 output from the inverter 267 rises from "L" to "H".
269, 270, the divided clocks CLK2, C
LK4 and CLK8 rise from "L" to "H".
Therefore, when the self-refresh control signal rises from “L” to “H” at time t0, fuse 27
In a state where 3 is not disconnected, CLK4 is selected and output to CKO since the S input of the selector 271 is "H". The one-shot pulse generation circuit 274 generates one set pulse SETP in response to the rising edge of the received divided clock CLK4 and generates a set / reset circuit 275.
Is set. Then, the set reset circuit 275
The generated set pulse SETP is reset by the reset pulse RSTP delayed by the delay circuit 1-276. As a result, the set / reset circuit 27
5 supplies a self row selection control signal having a predetermined pulse width equal to the delay time of the delay circuit (1) -276. Hereinafter, the set reset circuit 275 supplies an internal self-refresh control signal at the cycle of the divided clock CLK4 in accordance with the received set pulse SETP.

In FIG. 1, since the / auto refresh control signal (2) and the / row selection control signal (2) are initially set to "H", the outputs of the DFFs 215 and 216 become "L". Two of the three inputs of the OR circuit 222 become “L”. Therefore, the OR circuit 222
Supplies the internal self-refresh control signal as it is as a row selection control signal. As described above, the time t
0, the internal self-refresh control signal is "H"
, The DRAM 2 starts the first refresh operation. When the row selection control signal becomes "H", the DRAM 2 of FIG. 3 operates as follows. That is, “H” is applied to the word line WLn selected by the row address (address value A) output from the refresh counter 224, and all the memory cells MN on the word line WLn are applied.
1 to MN2m are selected, and the data of each of the memory cells MN1 to MN2m is read out as a minute signal to the 2m pair of bit lines and / bit lines. Then, the minute signal is differentially amplified by each of the 2m sense amplifiers SA1 to SA2m, and data is rewritten in each memory cell 80 by the amplified signal. Thus, a refresh operation is performed on one word line WLn.

Hereinafter, the operation of the oscillation circuit 251 will be described with reference to FIG. In the oscillation circuit 251 of FIG. 3, the PMOS transistor 254 is turned off at time t0 of FIG.
As a result, the signal C1 is disconnected from the power supply voltage Vdd, and the signal S4 becomes "L", so that the oscillation capacitors C1 and C2 start discharging. Therefore,
The signal level of the signal S0 decreases from the power supply voltage Vdd according to the time constant RC of the oscillation resistor R1 (resistance value R) and the oscillation capacitors C1 and C2 (total capacitance C), and the time t1
And becomes equal to the threshold voltage Vth of the inverter 255. That is, at time t1, the inverter 255
Is inverted from "L" to "H", and the signal S3 output from the inverter 256 is inverted from "H" to "L". As a result, the signal level of the signal S0 changes to −Vth, and the signal S4 output from the NAND circuit 14 is inverted from “L” to “H”, that is, Vdd. Therefore, from time t1, the oscillation capacitors C1 and C2 start charging. Then, the signal level of signal S0 rises according to time constant RC, and reaches threshold voltage Vth at time t2.
Is inverted from "H" to "L", and the signal S3 output from the inverter 256 is inverted from "L" to "H". As a result, the signal level of signal S0 changes to Vdd + Vth, and NAND circuit 257
Is output from "H" to "L", that is, 0.
Invert to V. Therefore, from time t2, the oscillation capacitor C1 starts discharging. Here, as shown in FIG. 5, the signal level of the signal S1 is different from the signal level of the signal S0 by the forward voltage V of the protection diodes 252 and 253.
It is clamped at the potential obtained by adding f.

The oscillating circuit 10 repeats the above oscillating operation and supplies the oscillating clock CLK1 at a cycle determined according to the time constant RC, as shown in FIG. Therefore, at time t3 after the elapse of the period T1 after the oscillation circuit 10 starts oscillating at time t1, the frequency-divided clock CLK4 output from the two-frequency divider 269 rises. Therefore, at time t3, the one-shot pulse generation circuit 2
Reference numeral 74 sets the set / reset circuit 275, and the internal self-refresh control signal output from the set / reset circuit 275 rises. Thereby, the DRAM 2
Starts a second refresh operation at time t3 by an internal self-refresh control signal, that is, a row selection control signal. At this time, as shown in FIG. 5, the count value of the refresh counter 224 is counted up from A at time t0 to A + 1, and the refresh operation for the word line Wn + 1 is performed. Thereafter, at time t4 after a lapse of the period T2 from time t3, the frequency-divided clock CLK4 output from the frequency divider 269 rises, and the third refresh operation is started by the row selection control signal as described above. After that, the external input terminal (2)
Until the self-refresh control signal is set to "L", the refresh operation is repeated at intervals of T2 from time t4. At the time of the self-test, the internal self-refresh control signal is output as the row selection control signal as described above,
The row selection control signal is output to the external input / output terminal (0). The operation will be described with reference to FIG. In FIG. 2, a row selection control signal is input to a selector 312.
Since the self test signal is “H”, the selector 31
2, a row selection control signal is output and input to the selector 313. Since the DRAM test signal is "H", the input A is selected by the selector 313. Therefore, the row selection control signal is input to the tri-state buffer 317. Since the self test signal is "H", the IO control signal (1 )But,
"H" and the row selection control signal is applied to the external input / output terminal (0)
Is output to

According to the present embodiment as described above, FIG.
As described above, if the semiconductor device 1 is set to the self-refresh test mode of the DRAM 2 by the external test input terminal, the row selection signal can be output to the external input / output terminal (0). By measuring the self-refresh cycle using the signal of the external input / output terminal (0), if the cycle cannot be remedied by trimming, it is determined to be defective. Good products can be relieved, and the test of the self-refresh circuit 250 can be performed in a short time.

If the self-refresh cycle is longer than the standard, the fuse 264 shown in FIG.
By shortening the oscillation cycle of No. 1 and shortening the self-refresh cycle, the cycle can be within the standard. If the self-refresh cycle is shorter than the standard, the self-refresh cycle may be lengthened by cutting the fuse 265 or the fuse 266 in FIG. 3 to increase the oscillation cycle of CLK1, or by cutting the fuse 273. By setting the S input of the selector 271 to "L" and selecting CLK8, the self-refresh cycle can be lengthened and any one of the methods can be selected, and the refresh cycle can be within the standard. Even when the self-refresh cycle is within the standard, the cycle setting can be trimmed to the maximum of the standard so that the current value at the time of the self-refresh is minimized. Further, by measuring the pulse width by the signal of the external input / output terminal (0) during the self-refresh test, if the pulse width is in a range that cannot be remedied by trimming, it is determined to be a defective product. The delay value of the first delay circuit 276 is relieved by trimming.

As described with reference to FIG. 2, the circuit configuration for outputting a row selection control signal at the time of a self-refresh test to the external input / output terminal (0) for outputting test data 0 at the data read test of the DRAM 2 By sharing the external input / output terminal (0) with the data (0) and the row selection control signal, the number of external terminals during the DRAM test can be reduced.

[0034]

According to the present invention, there is provided a semiconductor device in which a memory and a logic circuit are integrated into one chip, and for supplying an oscillation clock having a fixed cycle when a self-refresh control signal is input. Oscillating means, signal generating means for supplying an internal self-refresh control signal for refreshing a memory cell based on the oscillation clock, and signal output means for outputting the internal self-refresh control signal to an external terminal. With this configuration, the self-refresh circuit including the oscillation unit and the signal generation unit can be tested by the method of measuring the period and pulse width of the signal of the external terminal.

As a result, a test of the self-refresh circuit can be performed in a short time, and a semiconductor device capable of optimizing a self-refresh cycle by trimming and relieving a defective product can be realized.

According to the present invention, the signal output means includes:
At the time of the data read test from the memory, the test data is output to the external terminal. At the time of the self refresh test,
By employing a circuit configuration for outputting the internal self-refresh control signal to an external terminal, a self-refresh test can be performed without increasing the number of external terminals for a DRAM test.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a semiconductor device according to the present invention.

FIG. 2 is a configuration diagram of a memory cell array and its peripheral circuits in a semiconductor device according to the present invention.

FIG. 3 is a configuration diagram of a self-refresh circuit in the semiconductor device according to the present invention;

FIG. 4 is a read timing chart in a page mode during a data read test of a DRAM.

FIG. 5 is an operation timing chart at the time of a DRAM self-refresh test.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Semiconductor device 2 DRAM 3 Memory cell array and peripheral circuit 4 Logic part 201-208, 229 Selector 210-214, 230, 231 Inverter 215-218 D flip-flop 219 2-input AND circuit 220 3-input AND circuit 221 232 2-input OR Circuit 222 Three-input OR circuit 223 Timing generation circuit 224 Refresh counter 225 Row address latch 226 Column address latch 227 Byte address latch 228 Test decode circuit 250 Self-refresh circuit 251 Oscillator circuit

Claims (2)

[Claims] 1. A semiconductor device integrated into one chip, comprising: a memory having a memory cell requiring refresh for storing data; and an oscillation clock having a constant cycle when a self-refresh control signal is inputted. Oscillating means for supplying
Signal generating means for supplying an internal self-refresh control signal for refreshing the memory cell based on the oscillation clock, and signal output means for outputting the internal self-refresh control signal to an external terminal. Characteristic semiconductor device. 2. The semiconductor device according to claim 1, wherein said signal output means outputs test data to an external terminal during a data read test from a memory, and said internal self refresh control signal during a self refresh test. Output to an external terminal.