JPH11345221A - Multiprocessor system - Google Patents

Abstract

(57) [Summary] [PROBLEMS] The internal storage resources of ROM, RAM, and I / O in a slave unit connected to a master unit have a dual-port configuration, and can be directly accessed from the master unit via an external data bus. To provide a simple multiprocessor system. SOLUTION: A dual port ROM 15, a dual port RAM as internal resources in a slave unit 12 are provided.
16, using a dual port I / O device 17, one of these ports is connected to the internal data bus 18 to enable access from the slave processor, and the other port is directly connected to the external data bus 14 to allow for the actual operation and During debugging, the master processor 11 can read and write data from and to the internal resources.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory and an I / O (Inpu) in a slave unit connected to a master unit.
t / Output: a multiprocessor system in which the device has a dual port configuration.

[0002]

2. Description of the Related Art A conventional multiprocessor system will be described with reference to FIG. FIG. 2 is a block diagram of a conventional multiprocessor system. As shown in FIG. 2, the master processor 11 in the master unit 10 and the slave processor 13 in the slave unit 12 are electrically connected by an external data bus 14. The slave processor 13 operates under the control of the master processor 11.

[0003] RO, which is provided in the slave unit 12 and is an internal resource used by the slave processor 13,
M (Read Only Memory) 25, R
AM (Random Access Memory) 2
6, the storage elements and devices such as the I / O device 27 are electrically connected to each other by an internal data bus 18 in the slave unit 12, and are transmitted from the slave processor 13 via the internal data bus 18. Access. Therefore, in order to externally access the above-mentioned storage elements and devices in the slave unit 12 during actual use of the present multiprocessor system, it is necessary to go through the slave processor 13. In debugging 12, a dedicated debugging device (not shown) had to be separately prepared.

[0004]

In the above example of the conventional device, the internal resource in the slave unit 12, ROM
In debugging, storage devices and devices such as the RAM 25, the I / O 27, and the like must know the status using a debugging device dedicated to the slave unit. In this case, the slave processor 13 had to be active. Furthermore, in a multiprocessor system, when there are a plurality of slave units,
Separate debugging devices are required for each slave unit, and when a single debugging device is used, all the slave units cannot be debugged at the same time. Also, in a multiprocessor system, during actual operation other than the above-described debugging, the storage elements and devices in the slave unit are accessed from outside the slave unit such as the master unit, and the contents are read or further modified. It was impossible to do.

The present invention has been made in view of such circumstances, and has a ROM, a RAM, an I / O in a slave unit.
By using a dual-port type, the ROM and RA can be transmitted from the master processor via an external bus.
Since the M and I / O can be accessed, their programs and data can be changed during actual operation, and the states of the ROM, RAM, and I / O can be changed during debugging regardless of the operation / non-operation of the slave processor. It is an object of the present invention to provide a multiprocessor system capable of performing a debugging process by knowing the information.

[0006]

According to the first aspect of the present invention,
In a multiprocessor system having a master unit including a master processor and a slave unit electrically connected to the master processor via an external bus and including a slave processor operating under the control of the master processor, The multiprocessor system is characterized in that the storage unit and the input / output unit provided are directly electrically connected to the external bus so as to be accessible from both the master processor and the slave processor. According to a second aspect of the present invention, in the multiprocessor system according to the first aspect, the storage unit and the input / output unit are dual-port elements or devices. According to a third aspect of the present invention, in the multiprocessor system according to the second aspect, the storage unit includes a first storage unit that stores an execution program, and a second storage unit that stores processing data. The first storage unit is made of an element that can be electrically rewritten via the external bus.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A multiprocessor system according to one embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of a multiprocessor system according to the first embodiment. In FIG. 1, the same components as those in FIG. 2 according to the related art described above are denoted by the same reference numerals, and the description will not be repeated. In the present embodiment, the slave unit 12
As the internal storage resources, a dual-port type having two different data ports and capable of inputting and outputting data from each port is used. As shown in FIG. 1, a dual port ROM 15 is used as a ROM for storing execution programs and fixed data, a dual port RAM 16 is used as a RAM for storing rewrite data, and a dual port I / O device 17 is used as an input / output device.

These dual port ROM 15, dual port RAM 16, dual port I / O device 17
Is a dual port type as described above. One port is directly electrically connected to the external data bus 14, and the other port is connected to the internal data bus 18. As a result, the master processor 11 via the external data bus 14
Can access the internal resources of these slave units, and within the slave unit 12,
The slave processor 13 accesses using the internal data bus 18.

As a result, data can be read from and written to the internal resources of the slave unit from the outside of the slave unit via the external data bus 14 regardless of the operation / non-operation of the slave processor. Debugging is possible without using a special debugging device. In other words, during debugging, regardless of the operation of the slave processor, the dual port ROM 1
5) Using the external data bus to rewrite the execution program from the master processor to the changed execution program allows the slave processor to operate with the updated program, and by repeating this process, the debugging process can proceed efficiently and promptly. Becomes

Also, not only during debugging but also during actual operation, regardless of the operation of the slave processor, data can be read and written directly from the master processor to the internal resources in the slave unit. Free time such as waiting for access to these resources is eliminated, and the throughput of the master processor is improved. Further, the slave processor does not need to perform an additional process of externally managing an access request for an internal resource in the slave unit, thereby improving the processing efficiency of the slave processor.

Although the above embodiment has been described on the assumption that there is one slave unit, the present invention is not limited to this example, and a plurality of slave units are connected in parallel to an external data bus. The present invention is also applicable to such cases, and the effects of the present invention can be sufficiently exhibited in such cases.

[0012]

As described above, according to the multiprocessor system of the present invention, the following effects can be obtained. 1. By reading and writing data directly from the master processor to the internal resources of the slave unit via the external data bus, programs and data can be changed from the master processor during the actual operation of the multiprocessor system. Overall flexibility is improved. 2. The load on both the master processor and the slave processor for managing access requests when accessing the internal resources of the slave unit is reduced, and the throughput is improved. 3. Similarly, a special debug device is not required when debugging the slave unit, and the internal resources in the slave unit can be accessed directly from the master processor for debugging, thereby saving the resources required for debugging. , Improving the debugging efficiency.

[Brief description of the drawings]

FIG. 1 is a block diagram of a multiprocessor system according to an embodiment of the present invention.

FIG. 2 is a block diagram of a conventional multiprocessor system.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 ... Master unit 11 ... Master processor 12 ... Slave unit 13 ... Slave processor 14 ... External data bus 15 ... Dual port ROM 16 ... Dual port RAM 17 ... Dual port I / O device 18 ... Internal data bus 25 ... ROM 26 ... RAM 27 ... I / O equipment

Claims (3)

[Claims] 1. A multiprocessor system comprising: a master unit including a master processor; and a slave unit including a slave processor electrically connected to the master processor via an external bus and operating under the control of the master processor. The storage unit and the input / output unit provided in the slave unit are directly electrically connected to the external bus so as to be accessible from both the master processor and the slave processor. Processor system. 2. The multiprocessor system according to claim 1, wherein said storage section and said input / output section are dual-port elements or devices. 3. The storage unit includes a first storage unit that stores an execution program, and a second storage unit that stores processing data, wherein the first storage unit is connected to the external bus via the external bus. 3. The multiprocessor system according to claim 2, wherein the multiprocessor system comprises a dynamically rewritable element.