JPH11345842A - Lead frame for semiconductor device - Google Patents

Lead frame for semiconductor device

Info

Publication number
JPH11345842A
JPH11345842A JP10153374A JP15337498A JPH11345842A JP H11345842 A JPH11345842 A JP H11345842A JP 10153374 A JP10153374 A JP 10153374A JP 15337498 A JP15337498 A JP 15337498A JP H11345842 A JPH11345842 A JP H11345842A
Authority
JP
Japan
Prior art keywords
lead frame
semiconductor device
chip
bump
bumps
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10153374A
Other languages
Japanese (ja)
Inventor
Yasuro Terui
康郎 照井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Instruments Inc
Original Assignee
Seiko Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Instruments Inc filed Critical Seiko Instruments Inc
Priority to JP10153374A priority Critical patent/JPH11345842A/en
Publication of JPH11345842A publication Critical patent/JPH11345842A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H10W72/07321—Aligning
    • H10W72/07327—Aligning involving guiding structures, e.g. spacers or supporting members
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/726—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

(57)【要約】 【課題】 フリップチップ実装に用いられる半導体装置
用リードフレームにおいて、搭載したチップの位置ずれ
を防ぎ、接続信頼性や歩留りを向上させる様にするこ
と。 【解決手段】 半導体装置用リードフレームのインナー
リード先端の、半導体チップのバンプが接触する部分に
バンプの高さ以下の深さの窪みを設け、その中にバンプ
をはめ込むような状態でチップを搭載するようにした。
(57) [Problem] To provide a semiconductor device lead frame used for flip-chip mounting, in which a mounted chip is prevented from being displaced, and connection reliability and yield are improved. SOLUTION: A recess having a depth equal to or less than the height of the bump is provided at a portion of the tip of an inner lead of a lead frame for a semiconductor device where the bump of the semiconductor chip contacts, and the chip is mounted in such a manner as to fit the bump into the recess. I did it.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は半導体チップとリー
ドフレームとを半導体チップ表面のバンプを介してフリ
ップチップ実装技術を用いて接続する半導体装置用リー
ドフレームに関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a lead frame for a semiconductor device in which a semiconductor chip and a lead frame are connected to each other by using a flip chip mounting technique via bumps on the surface of the semiconductor chip.

【0002】[0002]

【従来の技術】従来の半導体チップとリードフレームと
をフリップチップ実装技術を用いて接続する半導体装置
では、半導体チップはバンプを介して平坦なインナーリ
ード先端に搭載された後、次工程にて加熱処理等により
一括接続されていた。
2. Description of the Related Art In a conventional semiconductor device in which a semiconductor chip and a lead frame are connected by using a flip-chip mounting technique, the semiconductor chip is mounted on the tip of a flat inner lead via a bump and then heated in the next step. They were connected collectively by processing.

【0003】[0003]

【発明が解決しようとする課題】しかしながら従来の実
装の場合、チップはリードフレーム上に搭載されてから
一括接続されるまでの間、インナーリード上にフラック
ス等を介して仮固定されているだけであった。そのため
リードフレーム上へのチップの搭載工程中もしくは次の
接続工程が終了するまでの間に、リードフレームに加え
られる振動等により、搭載されたチップが搭載当初の位
置からずれるという現象が生じ、その結果、製造される
半導体装置の歩留りが低下するという問題点があった。
However, in the case of the conventional mounting, the chip is temporarily fixed on the inner lead via a flux or the like during a period from being mounted on the lead frame to being connected collectively. there were. Therefore, during the process of mounting the chip on the lead frame or until the next connection process is completed, the phenomenon that the mounted chip shifts from the initial mounting position due to vibration applied to the lead frame occurs. As a result, there is a problem that the yield of the manufactured semiconductor device is reduced.

【0004】本発明の目的は、上述の問題点を解消する
ためになされたものである。
[0004] An object of the present invention is to solve the above-mentioned problems.

【0005】[0005]

【課題を解決するための手段】本発明に係わる半導体装
置リードフレームでは、上述した問題点を解決するため
に、表面に複数のトランジスタ及びハンダや導電性接着
剤からなるバンプが形成された半導体チップとそれらの
バンプを介して電気的、機械的に接続を確保する前記半
導体装置用リードフレームにおいて、インナーリード上
のバンプが接続される部分に、深さがバンプの高さ以下
の窪みを形成した。
In order to solve the above-mentioned problems, a semiconductor device lead frame according to the present invention has a semiconductor chip having a surface formed with a plurality of transistors and bumps made of solder or conductive adhesive. And the semiconductor device lead frame that electrically and mechanically secures the connection via the bumps, in the portion where the bumps on the inner leads are connected, a recess having a depth equal to or less than the height of the bump is formed. .

【0006】[0006]

【発明の実施の形態】以下にこの本発明の実施例を図面
に基づいて説明する。図1は、リードフレーム1に設け
たインナーリード2の先端部分に、搭載する半導体チッ
プのバンプの配置に対応するように、窪み3が形成され
ている半導体装置用リードフレームを示している。
Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a lead frame for a semiconductor device in which a depression 3 is formed at the tip of an inner lead 2 provided on a lead frame 1 so as to correspond to the arrangement of bumps of a semiconductor chip to be mounted.

【0007】図2では、半導体チップ搭載後のチップ及
びインナーリードの断面図を示している。インナーリー
ド2のチップ搭載側に設けられた窪み3に、半導体チッ
プ4上のバンプ5がはまり込む事により、搭載されたチ
ップの仮固定の強度が増す。窪みの形状及び大きさは、
搭載されるバンプの形状により任意に変更可能である。
ハンダを用いたバンプのように半球状の場合は凹面鏡状
の、また金や導電性接着剤製バンプのように直方体状や
円柱状のバンプの場合には直方体状や円筒状の窪みが望
ましい。窪みの開口部の大きさはいずれの場合もバンプ
の大きさ以上が望ましい。窪みの深さは、バンプの高さ
以上になるとチップの搭載時にチップ底面がインナーリ
ードに接触してしまう可能性が有るのでバンプの高さ以
下とする。
FIG. 2 is a sectional view of the chip and the inner leads after the semiconductor chip is mounted. The bumps 5 on the semiconductor chip 4 fit into the recesses 3 provided on the chip mounting side of the inner leads 2, thereby increasing the strength of the temporarily mounted chip. The shape and size of the depression are
It can be arbitrarily changed depending on the shape of the mounted bump.
In the case of a hemispherical shape such as a bump using solder, a concave mirror shape is preferable, and in the case of a rectangular or columnar bump such as a bump made of gold or a conductive adhesive, a rectangular or cylindrical hollow is preferable. In any case, the size of the opening of the depression is desirably equal to or larger than the size of the bump. If the depth of the depression is greater than the height of the bump, the bottom surface of the chip may come into contact with the inner lead during mounting of the chip.

【0008】[0008]

【発明の効果】以上のように本発明に関わる半導体装置
用リードフレームは、インナーリード上に、搭載する半
導体チップ上につけられたバンプに対応した位置、大き
さ、形に応じた窪みを設けてあるので、インナーリード
上に半導体チップを仮固定すると窪みの内部にバンプが
はまり込む。そのため単に平面上にバンプを載せたイン
ナーリードに比べて仮固定の強度が上がり、次工程で本
固定されるまでの間に発生する、半導体チップの位置ズ
レに起因する接続不良の発生を抑え、歩留りを向上させ
る効果が有る。
As described above, the lead frame for a semiconductor device according to the present invention is provided with depressions corresponding to the positions, sizes and shapes corresponding to the bumps formed on the semiconductor chip to be mounted on the inner leads. Therefore, when the semiconductor chip is temporarily fixed on the inner leads, the bumps fit into the recesses. Therefore, the strength of the temporary fixing is increased as compared with the inner lead in which the bump is simply placed on the flat surface, and the occurrence of a connection failure due to a misalignment of the semiconductor chip occurring until the final fixing in the next process is suppressed, This has the effect of improving the yield.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の半導体装置用リードフレーム平面図を
示す。
FIG. 1 is a plan view of a lead frame for a semiconductor device of the present invention.

【図2】本発明の半導体装置用リードフレームにチップ
を搭載した状態の断面図である。
FIG. 2 is a sectional view showing a state in which a chip is mounted on a lead frame for a semiconductor device of the present invention.

【符号の説明】[Explanation of symbols]

1 リードフレーム 2 インナーリード 3 接続用窪み 4 半導体チップ 5 バンプ電極 DESCRIPTION OF SYMBOLS 1 Lead frame 2 Inner lead 3 Connection recess 4 Semiconductor chip 5 Bump electrode

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 表面に複数のトランジスタ及びハンダや
導電性接着剤からなるバンプが形成された半導体チップ
とそれらのバンプを介して電気的、機械的に接続を確保
する半導体装置用リードフレームにおいて、インナーリ
ード上のバンプが接続される部分に、深さがバンプの高
さ以下の窪みが形成されている事を特徴とする半導体装
置用リードフレーム
1. A semiconductor device having a plurality of transistors and bumps made of solder or a conductive adhesive formed on a surface thereof, and a semiconductor device lead frame for ensuring electrical and mechanical connection through the bumps. A lead frame for a semiconductor device, wherein a recess having a depth equal to or less than the height of the bump is formed in a portion where the bump on the inner lead is connected.
JP10153374A 1998-06-02 1998-06-02 Lead frame for semiconductor device Pending JPH11345842A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10153374A JPH11345842A (en) 1998-06-02 1998-06-02 Lead frame for semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10153374A JPH11345842A (en) 1998-06-02 1998-06-02 Lead frame for semiconductor device

Publications (1)

Publication Number Publication Date
JPH11345842A true JPH11345842A (en) 1999-12-14

Family

ID=15561071

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10153374A Pending JPH11345842A (en) 1998-06-02 1998-06-02 Lead frame for semiconductor device

Country Status (1)

Country Link
JP (1) JPH11345842A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101091896B1 (en) * 2004-09-04 2011-12-08 삼성테크윈 주식회사 Flip chip semiconductor package and manufacturing methode thereof
JP2018029138A (en) * 2016-08-18 2018-02-22 トレックス・セミコンダクター株式会社 Semiconductor device
JP2020021809A (en) * 2018-07-31 2020-02-06 エイブリック株式会社 Semiconductor device
JP2022078697A (en) * 2020-11-13 2022-05-25 ローム株式会社 Semiconductor device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101091896B1 (en) * 2004-09-04 2011-12-08 삼성테크윈 주식회사 Flip chip semiconductor package and manufacturing methode thereof
JP2018029138A (en) * 2016-08-18 2018-02-22 トレックス・セミコンダクター株式会社 Semiconductor device
JP2020021809A (en) * 2018-07-31 2020-02-06 エイブリック株式会社 Semiconductor device
JP2022078697A (en) * 2020-11-13 2022-05-25 ローム株式会社 Semiconductor device

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