JPH113848A - Semiconductor device manufacturing equipment - Google Patents
Semiconductor device manufacturing equipmentInfo
- Publication number
- JPH113848A JPH113848A JP9154063A JP15406397A JPH113848A JP H113848 A JPH113848 A JP H113848A JP 9154063 A JP9154063 A JP 9154063A JP 15406397 A JP15406397 A JP 15406397A JP H113848 A JPH113848 A JP H113848A
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- resist coating
- semiconductor device
- removal
- lots
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Landscapes
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
- Photosensitive Polymer And Photoresist Processing (AREA)
- Weting (AREA)
Abstract
(57)【要約】
【課題】半導体製造におけるフォト工程前処理の酸化膜
除去に関し、酸化膜除去からレジスト塗布にかかる時間
を統一し、自然酸化膜の膜厚をウェハ間またロット間で
一定に保つことで寸法ばらつきを低減すること。
【解決手段】酸化膜除去ユニットをレジスト塗布コータ
ーに組み込むことにより酸化膜除去からレジスト塗布ま
でかかる時間を統一し、自然酸化膜の膜厚をロット間で
一定に保つことで寸法ばらつきを低減する。基板を酸化
膜除去ユニット1に入れ酸化膜除去した後、ベークプレ
ート2に入れ乾燥させる。その後レジスト塗布コーター
3、プレベークプレート4によってレジスト塗布工程の
処理を終了させる。尚、各ユニットはすべて枚葉処理で
ある。
(57) [Summary] Regarding oxide film removal in photo process pretreatment in semiconductor manufacturing, unify the time from oxide film removal to resist coating, and keep the thickness of natural oxide film constant between wafers and lots. To reduce dimensional variation by maintaining. A time required from removal of an oxide film to application of a resist is unified by incorporating an oxide film removal unit into a resist coating coater, and dimensional variation is reduced by keeping the thickness of a natural oxide film constant between lots. After the substrate is placed in the oxide film removing unit 1 to remove the oxide film, it is placed in the bake plate 2 and dried. Thereafter, the resist coating process is completed by the resist coating coater 3 and the pre-bake plate 4. Each unit is a single-wafer processing.
Description
【0001】[0001]
【発明の属する技術分野】本発明は半導体製造における
フォト工程前処理の酸化膜除去に関する。[0001] 1. Field of the Invention [0002] The present invention relates to removal of an oxide film in a pre-processing of a photo process in semiconductor manufacturing.
【0002】[0002]
【従来の技術】従来の半導体製造におけるフォト工程前
処理の酸化膜除去は次工程のレジスト塗布機と別の単体
機で処理を行っていた。2. Description of the Related Art Conventionally, removal of an oxide film in a pre-process of a photo process in semiconductor manufacturing has been performed by a single unit separate from a resist coating machine in the next process.
【0003】[0003]
【発明が解決しようとする課題】しかし、前述の従来技
術ではレジスト塗布装置とは別になっているため酸化膜
除去をした後ウェハ間またロット間でレジスト塗布まで
の時間が異なるため、「シリコンウェーハ表面のクリー
ン化技術」の第8節図−5に示されている様に自然酸化
膜がウェハごとまたロットごとに違う膜厚で付き、図1
に説明する様に寸法ばらつきの要因になるという問題を
有する。そこで本発明は酸化膜除去からレジスト塗布ま
でかかる時間を統一し、自然酸化膜の膜厚をウェハ間ま
たロット間で一定に保つことで寸法ばらつきを低減する
半導体製造装置を提供することを目的とする。However, in the above-mentioned prior art, since the time until the resist coating is different between wafers or lots after removing the oxide film because it is separate from the resist coating apparatus, the "silicon wafer" As shown in Figure 8-5 in Section 8 of "Surface Cleaning Technology", a native oxide film is attached with a different film thickness for each wafer and for each lot.
As described in the above, there is a problem that it causes a dimensional variation. Accordingly, an object of the present invention is to provide a semiconductor manufacturing apparatus which unifies the time required from oxide film removal to resist coating and reduces dimensional variations by keeping the thickness of a natural oxide film constant between wafers or lots. I do.
【0004】[0004]
【課題を解決するための手段】請求項1記載の半導体製
造装置は、レジスト塗布前に酸化膜除去を行うためのユ
ニットを組み込んだ構成からなることを特徴としてい
る。上記手段を用いた半導体製造装置を使用することに
より、酸化膜除去をインラインでできることからウェハ
間またロット間での自然酸化膜が一定になり寸法ばらつ
きが低減できるという効果を有する。請求項2記載の半
導体製造装置は、レジスト塗布前に酸化膜除去を行うた
めのユニットにディップ槽を用いたことを特徴としてい
る。上記手段を用いた半導体製造装置を使用することに
より、酸化膜除去をインラインでできることからウェハ
間またロット間での自然酸化膜が一定になり寸法ばらつ
きが低減できるという効果を有する。請求項3記載の装
置は請求項1記載の装置で酸化膜除去に無水弗酸を使う
ためのチャンバーを用いたことを特徴としている。上記
手段を用いた半導体製造装置を使用することにより、酸
化膜除去をインラインでできることからウェハ間またロ
ット間での自然酸化膜が一定になり寸法ばらつきが低減
できるという効果を有する。請求項4記載の装置は請求
項1記載の装置で酸化膜除去にスピンナーを用いたこと
を特徴としている。上記手段を用いた半導体製造装置を
使用することにより、酸化膜除去をインラインでできる
ことからウェハ間またロット間での自然酸化膜が一定に
なり寸法ばらつきが低減できるという効果を有する。According to a first aspect of the present invention, there is provided a semiconductor manufacturing apparatus having a structure in which a unit for removing an oxide film before applying a resist is incorporated. By using a semiconductor manufacturing apparatus using the above-described means, an oxide film can be removed in-line, so that a natural oxide film is constant between wafers or lots, and the dimensional variation can be reduced. A semiconductor manufacturing apparatus according to a second aspect is characterized in that a dip tank is used as a unit for removing an oxide film before applying a resist. By using a semiconductor manufacturing apparatus using the above-described means, an oxide film can be removed in-line, so that a natural oxide film is constant between wafers or lots, and the dimensional variation can be reduced. An apparatus according to a third aspect is characterized in that a chamber for using anhydrous hydrofluoric acid for removing an oxide film is used in the apparatus according to the first aspect. By using a semiconductor manufacturing apparatus using the above-described means, an oxide film can be removed in-line, so that a natural oxide film is constant between wafers or lots, and the dimensional variation can be reduced. An apparatus according to a fourth aspect is characterized in that a spinner is used for removing an oxide film in the apparatus according to the first aspect. By using a semiconductor manufacturing apparatus using the above-described means, an oxide film can be removed in-line, so that a natural oxide film is constant between wafers or lots, and the dimensional variation can be reduced.
【0005】[0005]
【発明の実施の形態】以下、本発明の実施形態を図面に
基づいて説明する。Embodiments of the present invention will be described below with reference to the drawings.
【0006】(実施例1)図2(a)、図2(b)は請
求項1記載の発明に係る半導体装置の製造装置の第1の
実施例の構成を示す図である。その構成を説明すると1
は酸化膜除去ユニット、2はベークプレート、3はレジ
スト塗布コーター、4はプレベークプレートである。ま
た各ユニットはすべて枚葉処理である。従来は3のレジ
スト塗布コーターと4のプレベークプレートしかない
が、1と2のユニットを塗布前に組み込むことにより、
インラインで酸化膜除去とレジスト塗布ができるように
なり、さらに基板9は枚葉処理のためレジスト塗布前の
酸化膜の厚さがウェハごとさらにロットごと一定とな
る。なおこの構成で3の前にHMDS処理を加えても良
い。(Embodiment 1) FIGS. 2A and 2B are diagrams showing a configuration of a first embodiment of a semiconductor device manufacturing apparatus according to the present invention. The structure is described as follows.
Denotes an oxide film removing unit, 2 denotes a bake plate, 3 denotes a resist coating coater, and 4 denotes a pre-bake plate. Each unit is a single-wafer processing. Conventionally, there are only 3 resist coating coaters and 4 pre-baked plates, but by incorporating 1 and 2 units before coating,
The removal of the oxide film and the application of the resist can be performed in-line, and the thickness of the oxide film before the application of the resist is constant for each wafer and for each lot because the substrate 9 is subjected to single-wafer processing. In this configuration, HMDS processing may be added before step 3.
【0007】(実施例2)図3は請求項2記載の発明に
係る半導体装置の製造装置の第2の実施例の構成を示す
図であり、実施例1の構成を示す図2の1の酸化膜除去
ユニットの内容を示すものである。その構成を説明する
と酸化膜除去ユニットは弗酸水溶液の入ったディップ槽
5とリンス用の純水が入ったディップ槽6から成り、す
べて基板9は枚葉式で処理される。この構成から実施例
1と同様の作用が得られる。(Embodiment 2) FIG. 3 is a diagram showing the configuration of a second embodiment of the semiconductor device manufacturing apparatus according to the second aspect of the present invention. It shows the contents of the oxide film removing unit. Explaining the structure, the oxide film removing unit includes a dip tank 5 containing a hydrofluoric acid aqueous solution and a dip tank 6 containing pure water for rinsing, and all the substrates 9 are processed in a single wafer type. With this configuration, the same operation as in the first embodiment can be obtained.
【0008】(実施例3)図4は請求項3記載の発明に
係る半導体装置の製造装置の第3の実施例の構成を示す
図であり、実施例1の構成を示す図2の1の酸化膜除去
ユニットの内容を示すものである。その構成を説明する
と酸化膜除去ユニットは無水弗酸ガス7をウェハの入っ
たチャンバーに入れ酸化膜除去した後、純水6でリンス
し8から廃液を出す。この構成から実施例1と同様の作
用が得られる。(Embodiment 3) FIG. 4 is a view showing a configuration of a third embodiment of a semiconductor device manufacturing apparatus according to the third aspect of the present invention. It shows the contents of the oxide film removing unit. To explain the structure, the oxide film removing unit puts anhydrous hydrofluoric acid gas 7 into the chamber containing the wafer, removes the oxide film, rinses with pure water 6 and discharges waste liquid from 8. With this configuration, the same operation as in the first embodiment can be obtained.
【0009】(実施例4)図5は請求項4記載の発明に
係る半導体装置の製造装置の第4の実施例の構成を示す
図であり、実施例1の構成を示す図2の1の酸化膜除去
ユニットの内容を示すものである。その構成を説明する
と酸化膜除去ユニットはスピンナーを使って弗酸水溶液
5をウェハ上に滴下し酸化膜除去した後純水6にてリン
スする。この構成から実施例1と同様の作用が得られ
る。(Embodiment 4) FIG. 5 is a view showing the configuration of a fourth embodiment of the semiconductor device manufacturing apparatus according to the fourth aspect of the present invention. It shows the contents of the oxide film removing unit. Explaining the structure, the oxide film removing unit uses a spinner to drop a hydrofluoric acid aqueous solution 5 on a wafer, removes the oxide film, and then rinses with pure water 6. With this configuration, the same operation as in the first embodiment can be obtained.
【0010】[0010]
【発明の効果】以上述べたように、本発明の半導体装置
の製造装置によれば、フォト工程前処理の酸化膜除去装
置とレジスト塗布装置をインラインに組み込んだため、
酸化膜除去後からレジスト塗布までのウェハ間、ロット
間の時間差がなくなり、自然酸化膜の厚さを一定に保つ
ことができるため、寸法ばらつきの低減ができる。As described above, according to the semiconductor device manufacturing apparatus of the present invention, since the oxide film removing apparatus and the resist coating apparatus for the pre-processing of the photo process are incorporated in-line,
Since there is no time difference between wafers and lots between the removal of the oxide film and the application of the resist, the thickness of the natural oxide film can be kept constant, so that dimensional variations can be reduced.
【図1】自然酸化膜膜厚とそのときのパターン寸法。FIG. 1 shows a native oxide film thickness and a pattern size at that time.
【図2】本発明の構成を示すダイヤグラム図。FIG. 2 is a diagram showing a configuration of the present invention.
【図3】図2における酸化膜除去ユニットの一実施例を
示す断面図。FIG. 3 is a sectional view showing an embodiment of the oxide film removing unit in FIG. 2;
【図4】図2における酸化膜除去ユニットの一実施例を
示す断面図。FIG. 4 is a sectional view showing an embodiment of the oxide film removing unit in FIG. 2;
【図5】図2における酸化膜除去ユニットの一実施例を
示す断面図。FIG. 5 is a sectional view showing an embodiment of the oxide film removing unit in FIG. 2;
1.酸化膜除去ユニット 2.ベークプレート 3.レジスト塗布コーター 4.プレベークプレート 5.弗酸水溶液 6.純水 7.無水弗酸 8.廃液 9.基板 1. Oxide film removal unit 2. 2. Bake plate Resist coating coater 4. Pre-baked plate 5. Hydrofluoric acid aqueous solution 6. Pure water 7. 7. Hydrofluoric anhydride Waste liquid 9. substrate
Claims (4)
化膜除去のユニットをレジスト塗布装置の前に組み込む
ことにより前処理からレジスト塗布までの処理時間を統
一し、それによって処理ウェハ間またロット間の自然酸
化膜を一定に保つことにより寸法ばらつきを低減するこ
とを特徴とする半導体装置の製造装置。An integrated unit for removing an oxide film in a photo process pre-process in semiconductor manufacturing is integrated before a resist coating device to unify the processing time from the pre-process to the resist coating so that the processing time between processed wafers or between lots can be improved. An apparatus for manufacturing a semiconductor device, wherein a dimensional variation is reduced by keeping a natural oxide film constant.
プ槽を用いたことを特徴とする半導体装置の製造装置。2. A semiconductor device manufacturing apparatus according to claim 1, wherein a dip tank is used for removing an oxide film.
酸を使うためのチャンバーを用いたことを特徴とする半
導体装置の製造装置。3. An apparatus for manufacturing a semiconductor device according to claim 1, wherein a chamber for using hydrofluoric anhydride for removing an oxide film is used.
ナーを用いたことを特徴とする半導体装置の製造装置。4. An apparatus for manufacturing a semiconductor device according to claim 1, wherein a spinner is used for removing an oxide film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9154063A JPH113848A (en) | 1997-06-11 | 1997-06-11 | Semiconductor device manufacturing equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9154063A JPH113848A (en) | 1997-06-11 | 1997-06-11 | Semiconductor device manufacturing equipment |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH113848A true JPH113848A (en) | 1999-01-06 |
Family
ID=15576095
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9154063A Withdrawn JPH113848A (en) | 1997-06-11 | 1997-06-11 | Semiconductor device manufacturing equipment |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH113848A (en) |
-
1997
- 1997-06-11 JP JP9154063A patent/JPH113848A/en not_active Withdrawn
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Application deemed to be withdrawn because no request for examination was validly filed |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 20040907 |