JPH1141069A - CR oscillation circuit - Google Patents

Abstract

(57) [Problem] To provide a CR oscillation circuit capable of reducing the influence of an input offset voltage on an oscillation frequency and enabling highly accurate frequency setting. SOLUTION: A potential corresponding to a charge charged from an output terminal Out1 of a CR time constant circuit 2 is input to one input terminal of one OP amplifier circuit 3, and the other terminal is compared with the same. First reference potential V1, second reference potential V
2 was selectively input. As a result, the potentials V1 'and V2' actually compared with the output terminal Out1.
Are both shifted from the first and second reference potentials V1 and V2 to the lower potential side by the offset voltage Vo, so that the potential at the time of completion of the predetermined charge and discharge can be determined with the same vector shift, and the input offset voltage The influence on the oscillation frequency can be reduced. Thus, a CR oscillation circuit capable of setting a frequency with high accuracy is provided.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CR oscillation circuit.

[0002]

2. Description of the Related Art A conventional CR oscillation circuit has a configuration as shown in FIG. Reference numeral 51 denotes a reference power supply, and a power supply terminal V
The resistors r1, r2 and r3 are connected in series between DD and VSS, and the first reference potential V1 is connected from the connection point of the resistors r1 and r2.
From the connection point of the resistors r2 and r3 to the second reference potential V2
(Here, V2>V1> 0). 52 is a CR time constant circuit, and a buffer circuit 53
, And a capacitor c1 connected in series between the power supply terminal VSS and the power supply terminal VSS. The capacitor c1 is charged and discharged according to the output level of the buffer circuit 53. The connection point between the capacitor c1 and the resistor r4 is defined as an output terminal Out1. 54 and 55 are first and second OPs (Operationa
l) The first OP amplifier circuit 54 is an amplifier circuit.
The input terminal receives the reference potential V1, and the + input terminal receives the potential of the output terminal Out1 of the CR time constant circuit. Second OP
The amplifier circuit 55 receives the reference potential V2 at the + input terminal,
The input terminal receives the potential of the output terminal Out1. f1, f
Reference numeral 2 denotes a cascade-connected flip-flop circuit. The set input terminal S and the reset terminal R of the flip-flop circuit f1 are connected to a second OP amplifier circuit 55, respectively.
And the output of the first OP amplifier circuit 54 are applied,
The output terminal Q 'of the flip-flop circuit f2 is connected to the inverter 56. The output of the inverter 56 becomes the input of the buffer circuit 53, and the buffer circuit 53 thereby generates an oscillation output. Currently, CR like above
In general, the oscillation circuit integrates components other than the resistor r4 and the capacitor c1 and externally includes the resistor r4 and the capacitor c1.

The oscillating operation of this CR oscillation circuit is as follows. For example, if the CR time constant circuit 52 is performing the discharging operation at the timing t1 in FIG. 6A, the output of both the first OP amplifier circuit 54 and the second OP amplifier circuit 55 is “H”. As a result, the flip-flop circuits f1 and f2 hold their output states. When the discharge proceeds and the potential of the output terminal Out1 becomes lower than the reference potential V1 at the timing t2, the first OP amplifier circuit 54 inverts the output to "L". As a result, the output terminals Q and Q bar of the flip-flop circuit f1 are “L”,
It becomes "H" and the output terminals Q'Q 'bar of the flip-flop circuit f2 become "H" and "L", respectively. Accordingly, the output of the inverter 56 is set to “H”, the output of the buffer circuit 53 is set to “H”, and the CR time constant circuit 52 stops the discharging operation and starts the charging operation. Thereafter, the potential of the output terminal Out1 becomes higher than the reference potential V1 by charging, and the output of the first OP amplifier circuit 54 returns to “H”. However, the flip-flop circuits f1 and f2 hold the output state and charge. Operation continues. Further, at the timing t3 when the charging is completed, the potential of the output terminal Out1 is changed to the reference potential V.
When the voltage is higher than 2, the second OP amplifier circuit 55 inverts the output to “L”. As a result, the output terminals Q and Q bar of the flip-flop circuit f1 are “H”,
It becomes "L" and the output terminals Q'Q 'bar of the flip-flop circuit f2 become "L" and "H", respectively. As a result, the CR time constant circuit 52 stops the charging operation and starts the discharging operation. Immediately after this, the output terminal Out is charged by charging.
The potential of 1 becomes lower than the reference potential V2, and the output of the second OP amplifier circuit 55 returns to "H". However, the flip-flop circuits f1 and f2 hold their output states, and the discharging operation is continued. By repeating such a series of operations, the output terminal Out2 of the buffer circuit 53 is output from FIG.
An oscillation output as shown in Out2 of (a) is obtained.

[0004]

The operation of the CR oscillation circuit shown in FIG. 5 is ideally as described above, but actually, the first OP amplifier circuit 54 and the second OP amplifier circuit 55 have input offset characteristics. , Respectively, each of which is simply shown in FIG.
, The potential of the output terminal Out1 and the reference potential V
1, not V2. That is, due to the offset characteristics of the OP amplifier circuit, the input potential on the-input terminal side with respect to the + input terminal is, for example, the offset voltage V
It is lowered by o (here, it is lowered, but it may be raised on the contrary). For this reason, when the potential of the output terminal Out1 is input to the input terminal, the + input terminal, and the − input terminal of the opposite polarity in the first OP amplifier circuit 54 and the second OP amplifier circuit 55, respectively, FIG. As shown in the figure, the potential of the output terminal Out1 is
In No. 4, the potential is compared with the potential V1 'lower than the reference potential V1 by the offset voltage Vo, and in the second OP amplifier circuit 55, on the contrary, the potential is compared with the potential V2' higher than the reference potential V2 by the offset voltage Vo. For this reason, even if the first reference potential V1 is a predetermined discharge potential and the second reference potential V2 is a predetermined charge potential, no determination output is generated unless further discharge and charging are performed, and discharge completion and charge are completed. The judgment output of both completions will be delayed. For this reason, FIG.
Out2 showing the oscillation output waveform of Out of FIG.
As compared with an ideal waveform such as 2, the period becomes longer (the frequency is lower). As described above, it is difficult to control the offset voltage that affects the oscillation frequency of the CR oscillation circuit during integration, and this is one of the factors that make it difficult to set the frequency of the CR oscillation circuit.

[0005]

Therefore, in the present invention, C
A reference potential circuit for selectively outputting first and second reference potentials used for comparison in accordance with a potential level of a control signal for controlling a charge / discharge operation of an R time constant is provided, corresponding to a charge of the CR time constant circuit. The comparison circuit used to determine the level of the potential
A potential corresponding to the charge of the CR time constant circuit is input to one input, and first and second reference potentials selectively output are input to the other input, and these are compared. A control circuit for generating the control signal having two states having different potential levels based on the determination output is provided. Thereby, in the comparison operation deviated from the first and second reference potentials by the offset voltage, the respective vectors of the potentials actually referred to in the comparison operation are made the same, and the potentials at the time of completion of the predetermined charge and discharge are made the same vector. The effect of the input offset voltage on the oscillation frequency is reduced by making it possible to judge with the deviation of the oscillation frequency, thereby making it easy to set the frequency of the CR oscillation circuit.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A reference potential circuit for selectively outputting first and second reference potentials having different potential levels according to a potential level state of a control signal, a resistance element and a capacitance element, A CR time constant circuit that charges and discharges the capacitive element through the resistor and outputs a signal of a potential level corresponding to the charged charge according to the state of the potential level of the control signal, A comparison circuit that compares the potential level of the output of the reference potential circuit with the output of the reference potential circuit to generate a decision output, and generates the control signal having two states having different potential levels based on the decision output of the comparison circuit. It is preferable to configure a CR oscillation circuit including a control circuit that performs the control.

The control circuit switches the first and second reference potentials by the reference potential circuit by inverting and holding the state of the control signal every time the judgment output of the comparison circuit is inverted. It is also preferable to have a prohibition circuit for prohibiting the state inversion operation of the control signal for a specific time after the switching.

The control circuit includes a flip-flop circuit for inverting and holding the control signal, a delay circuit for delaying an output from the flip-flop circuit for the specific time, and a control circuit for controlling the output of the delay circuit and the comparison circuit. And a logic circuit for prohibiting the flip-flop circuit from performing an inversion holding operation based on the determination output.

[0009]

Next, a CR oscillation circuit according to an embodiment of the present invention will be described. First, the configuration of the present example will be described with reference to FIG. In this figure, components denoted by the same reference numerals as those in FIG. 5 are the same as those in FIG.

In FIG. 1, reference numeral 1 denotes a reference potential circuit;
A resistor r connected in series between the power supply terminals VSS and VDD
1, r2 and r3 and one terminal are respectively connected to a resistor r
1, a first terminal connected to a connection point with r2 and a connection point with resistances r2 and r3, and the other end connected to a common output terminal Out0.
It comprises a second transmission gate tr1, tr2. First and second transmission gates tr1,
tr2 passes the first reference potentials V1 and V2, respectively, and the output terminal Out0 selectively outputs the first reference potentials V1 and V2 according to a control signal described later.

Reference numeral 2 denotes a CR time constant circuit, which comprises a resistor r4 and a capacitor c1. The time constant circuit 2 has a charge / discharge operation controlled by a control signal described later, and an output terminal Out.
1 outputs a potential corresponding to the charge.

Reference numeral 3 denotes an OP amplifier circuit having a CR input at the + input.
The potential of the output terminal Out1 of the time constant circuit 2 is applied,
To the input, the first or second reference potential from the output terminal Out0 is applied, and ideally, the output is set to “H” every time the potential of the output terminal Out1 exceeds the potential of the output terminal Out0. Generates a judgment output. However, the OP amplifier circuit 3 generally has an offset voltage. Here, the OP amplifier circuit 3 has an input characteristic that lowers the input potential on the −input terminal side by, for example, the offset voltage Vo with respect to the + input terminal. In practice, each time the potential of the output terminal Out1 exceeds the potential lower than the potential of the output terminal Out0 by the offset voltage Vo, the judgment output “H” is output.
Shall occur.

Reference numeral 4 denotes a control circuit, and an inverter circuit i1
To i4, a flip-flop circuit f1, and a delay circuit d1
And a NAND gate na1 and a NOR gate no1. The flip-flop circuit f1 generates a control signal from the output terminal Q bar, and inverts and holds the control signal. This control signal is output from the terminal N1 bar, and is transmitted through the transmission gates tr1 and tr2 to the N-channel MO.
It is applied to the gates of the S transistor and the P channel MOS transistor. Also, this control signal is output from the inverter i1.
And output from its output terminal N1 to be applied to the gates of a P-channel MOS transistor and an N-channel MOS transistor at transmission gates tr1 and tr2, respectively. That is, the transmission signal tr is controlled by the control signal.
1 and tr2 are alternately opened and closed, and the first and second reference potentials V
1, the switching of V2 is performed. Delay circuit d1
Receives a control signal via inverters i1 and i2, and delays the control signal by a specific time T0. NAND gate na
1 and one input terminal of the NOR gate no1 receive the judgment output from the OP amplifier circuit 3 via the inverter circuit i3, and the other terminal receives the delay output from the delay circuit d1. The NAND gate na1 and the NOR gate no1 are for setting and resetting of the flip-flop circuit f1, respectively. Inverter i
4 through the reset terminal R of the flip-flop circuit f1.
Entered in the bar. These delay circuits d1, NAND
A gate na1, a NOR gate no1, an inverter i3,
i4 forms a prohibition circuit 40 that prohibits the state inversion operation of the control signal for a specific time after the switching of the first and second reference potentials V1 and V2.

Reference numeral 5 denotes a buffer circuit, and an inverter i
The outputs are set to “H” and “L” in response to the control signals via 1, i2 and i5. A resistor r4 and a capacitor c1 constituting a CR time constant circuit 2 are connected in series between the output terminal of the buffer circuit 5 and the power supply terminal VSS, and the capacitor c1 is charged and discharged according to the output level of the buffer circuit 5. .

In this embodiment, the CR time constant circuit 2
The above components other than the above are integrated on one chip, and a resistor r4 and a capacitor c1 are externally attached to this chip to form a CR time constant circuit 2.

Next, the operation of the present embodiment will be described with reference to the waveform diagrams of the respective terminals of FIG. 1 shown in FIGS.

In FIG. 2, the waveform of the output terminal Out1 of the CR oscillation circuit 2 and the inverter i1 which is the oscillation output
, That is, the oscillation output N1 for one cycle. FIG. 3 shows timings T1 to T2 and T3 to T3 in FIG.
This is for describing in detail the waveform of each terminal at T4, and the time axis is particularly enlarged in comparison with FIG.

First, the operation at timings T1 to T2 in FIG. 2, that is, charging of the capacitor c1 in the CR time constant circuit 2 proceeds, and the output terminal Out1 is at the potential V2 'lower than the second reference potential V2 by the offset potential Vo. The operation before and after the timing exceeding. At this time, the output of the output terminal Q bar of the flip-flop circuit f1, that is, the control signal is held at "L", the output of the buffer circuit 5 is set at "H", and the capacitor c1 is charged.

At timing T1, the output terminal N2 of the OP amplifier circuit 3 is at "L", the output terminal N3 of the inverter i3 is at "H", and the output terminal N4 of the delay circuit d1 is at "L". NAND gate na1, NOR gate no
1 receives the output of the output terminal N3 as one input, and receives the output of the output terminal N4 as the other input, and outputs "H" and "L" respectively here.
The output "L" of the NOR gate no1 is connected to the inverter i.
4 to “H”. As a result, the set terminal S bar and the reset terminal R bar of the flip-flop circuit f1 are both "H", and the flip-flop circuit f1 holds the control signal of the output terminal Q bar at "L". .

At timing T11, the capacitor c1
When the output terminal Out1 exceeds the potential V2 ', the output of the output terminal N2 of the OP amplifier circuit 3 becomes "H" and the output of the output terminal N3 of the inverter i3 becomes "L".
Becomes The NAND gate na1 disables the other input by the output “L” of the output terminal N4 of the delay circuit d1 that is input to one, and outputs “H” even if the output from the output terminal N3 becomes “L”. , Whereby the set terminal S bar is held at “H”. NO
The output of the R gate no1 is set to “H” when the output from the output terminal N3 is set to “L”. As a result, the reset terminal R1 becomes "L", the flip-flop circuit f1 inverts the output, and the output terminal Q becomes "H". As a result, the output from the output terminal N1 of the inverter i1 becomes "L", the second transmission gate tr2 is turned off, and the first transmission gate tr
1 turns on, and the output from the output terminal Out0 switches from the second reference potential V2 to the first reference potential V1. At the time of this switching, switching noise is added to the output of the output terminal Out0. In FIG. 3, for the sake of convenience, such noise is generated at the timing T12 which is later than the timing T11.
Shown as 1. Further, the control signal "H" from the output terminal Q bar changes the output of the buffer circuit 5 to "L" via the inverters i1, i2 and i5, thereby starting the discharge of the capacitor c1.

At the timing T12, the output N2 of the OP amplifier circuit 3 and the output N3 of the inverter i3 rapidly repeat "H" and "L" due to the influence of the noise n1. However, N which sets the flip-flop circuit f1
The AND gate na1 outputs the output N4 of the delay circuit d1, which is the other input, to the control signal Q bar for a specific time T0.
And the control signal Q bar is held at "L" for a specific time T0 after the control signal Q bar becomes "H", that is, the output N4 is held at "L". During this time, the input of the output N3 from the inverter i3 is invalidated. The output of the NOR gate or1 repeats "H" and "L", but the flip-flop circuit f
Since the resetting and holding are designated for 1, the output from the output terminal Q is held at "H".
As described above, OP due to noise at the time of switching the reference potential
The inversion of the control signal with respect to the inversion of the output N2 of the amplifier circuit 3 is prohibited, and parasitic oscillation due to noise is prevented.

At timing T13, a specific time T0 elapses from the switching of the reference potential, and the delay circuit d1
Output N4 also becomes "H". As a result, in the NAND gate na1, the input of the output N3 of the inverter i3 becomes valid. This timing is a timing set so that generation of noise due to switching of the reference potential can be regarded as being eliminated. The output terminal Out0 stably outputs the first reference potential V1, and the OP amplifier circuit The output N2 of No. 3 is stably at "H". For this reason,
Output N of inverter i3 in NAND gate na1
Even if the input of No. 3 is valid, there is no danger of being affected by noise. Conversely, in the NOR gate no1, the input of the output N3 of the inverter i3 becomes invalid, and the output becomes “L”.
And the reset terminal R of the flip-flop circuit f1 regardless of the output N2 of the OP amplifier circuit 3.
The bar is held at "H".

Next, the operation at timings T3 to T4 in FIG.
That is, the discharge of c1 progresses, and the output terminal Out1 becomes the first terminal.
Potential V lower than reference potential V1 by an offset potential Vo.
The operation before and after the timing exceeding 1 'will be described.

The discharge of the capacitor c1 progresses from the state of the timing T3 in the discharge operation state similar to the timing T13, and at the timing T31, the potential of the output terminal Out1 is the potential V1 'lower than the first reference potential V1 by the offset potential Vo. , The output N2 of the OP amplifier circuit 3 becomes "L". Thereby, the NAND gate na
The output potential of 1 becomes "L", that is, the potential of the set terminal S bar of the flip-flop circuit f1 becomes "L", the flip-flop circuit f1 is set, and the output terminal Q bar becomes "L". As a result, the first transmission gate tr1 is turned off, the second transmission gate tr2 is turned on, and the reference potential switches from the first reference potential V1 to the second reference potential V2. Also at the time of this switching, switching noise is applied to the output terminal Out0. Here, this is indicated by n2 at timing T32. The charging of the capacitor c1 is started by the control signal “L” from the output terminal Q bar.

Due to the influence of noise n2 at timing T32, the output N2 of the OP amplifier circuit 3 and the inverter i3
Output N3 rapidly repeats "H" and "L". However, the NOR gate no1 that resets the flip-flop circuit f1 until the specific time has elapsed since the switching of the reference potential disables the input of the output N3 of the inverter i3 by the output “H” of the output terminal N4 of the delay circuit d1. Have been. Thus, the inversion of the control signal is prohibited. Thereafter, at timing T33 when the specific time T0 expires after the switching of the reference potential, the output from the output terminal N4 becomes “L”, and the NOR gate no1 that resets the flip-flop circuit f1 receives the input of the output N3 of the inverter i3. Valid. Timing T4 after this
, The charging operation state is the same as at the timing T1.

By repeating the above operation, a waveform as shown in Out1 of FIG. 2 is output from the output terminal Out1.
From the output terminal N1, a waveform as indicated by N1 in the figure is obtained. In this example, a potential corresponding to the charge charged from the output terminal Out1 of the CR time constant circuit 2 is input to one input terminal of one OP amplifier circuit 3, and the other terminal is used for comparison with this. First reference potential V1, second reference potential V
2 was selectively input. As a result, the potentials V1 'and V2' actually compared with the output terminal Out1.
Are both shifted from the first and second reference potentials V1 and V2 to the lower potential side by the offset voltage Vo. This makes it possible to determine the potential at the time of completion of the predetermined charge and discharge with the same vector shift, thereby reducing the influence of the input offset voltage on the oscillation frequency. This facilitates setting of the frequency of the CR oscillation circuit, and provides a CR oscillation circuit capable of setting the frequency with high accuracy. Further, only one OP amplifier circuit is required, and the scale can be reduced and simplified.

Further, since the control signal is inhibited from being inverted in accordance with the judgment output of the OP amplifier circuit 3 from the switching of the reference potential to the expiration of the specific time, the influence of noise due to the switching of the reference potential is not affected. It enables stable oscillation operation.

Incidentally, in order to suppress the influence of such noise, it is possible to employ a configuration as shown in FIG. 4 without using the control circuit 4. In this figure, the output of the output terminal N3 of the inverter i3 is replaced with the output of the terminal N1 in FIG.
Inverter i3 is used instead of 1 bar output.
Is output to the inverter i5 via the inverter i6. Further, the CR time constant circuit 6 is connected to the output terminal Out0.
To absorb noise. However,
In this case, in order to effectively absorb noise, it is necessary to appropriately set the size of the resistor r5 and the capacitor c2 of the CR time constant circuit.

[0029]

According to the present invention, since one comparison circuit is used by switching its reference potential, the influence of the input offset voltage of the comparison circuit on the oscillation frequency can be reduced, and the CR oscillation circuit can be used. Frequency setting is easy. As a result, it is possible to provide a CR oscillation circuit capable of setting a frequency with high accuracy.

Further, by providing the inhibition circuit, it is possible to prevent parasitic oscillation accompanying switching of the reference potential. Therefore, a CR oscillation circuit capable of performing a stable oscillation operation can be provided.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram illustrating a configuration of a CR oscillation circuit according to an embodiment of the present invention.

FIG. 2 is a waveform chart for explaining the operation of FIG. 1;

FIG. 3 is a waveform chart for explaining the operation of FIG. 1;

FIG. 4 is an explanatory diagram for explaining another example of the present invention.

FIG. 5 is an explanatory diagram showing a configuration of a conventional CR oscillation circuit.

FIG. 6 is a waveform chart for explaining the operation of FIG. 5;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Reference potential circuit 2 CR time constant circuit 3 OP amplifier circuit (comparison circuit) 4 Control circuit 40 Prohibition circuit

Claims (3)

[Claims] 1. A control circuit comprising: a reference potential circuit for selectively outputting first and second reference potentials having different potential levels according to a potential level state of a control signal; a resistance element and a capacitance element; A CR time constant circuit that charges and discharges the capacitive element through the resistor according to the state of the signal potential level and outputs a signal of a potential level corresponding to the charge, and an output from the CR time constant circuit A comparison circuit for comparing the potential levels of the output from the reference potential circuit and the reference level circuit to generate a determination output; and a control for generating the control signal having two states having different potential levels based on the determination output of the comparison circuit. A CR oscillation circuit characterized by comprising a circuit. 2. The control circuit switches the first and second reference potentials by the reference potential circuit by inverting and holding the state of a control signal every time the determination output of the comparison circuit is inverted. 2. The CR oscillation circuit according to claim 1, further comprising a prohibition circuit for prohibiting a state inversion operation of the control signal during a specific time after the switching. 3. A control circuit comprising: a flip-flop circuit for inverting and holding the control signal; a delay circuit for delaying an output from the flip-flop circuit for the specific time;
3. The CR according to claim 2, further comprising: a prohibition circuit comprising a logic circuit for prohibiting an inversion holding operation of the flip-flop circuit based on an output of the delay circuit and a judgment output from the comparison circuit. Oscillator circuit.