JPH1145582A - Semiconductor integrated circuit - Google Patents

Abstract

(57) Abstract: A delay time of data transfer from a sense amplifier output to an output circuit and from an input circuit to a write buffer is reduced. A read selector is introduced between a sense amplifier and a read buffer, and a sub read data line is provided between the read selector and the read buffer.
Further, a write selector is introduced between the write buffer and the common data line, and a sub-write data line is provided between the write buffer and the write selector. As a result, the data bus is hierarchized, the load capacity connected to the data bus is reduced, and the delay time of data transfer from the output of the sense amplifier to the output circuit and from the input circuit to the write buffer can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data bus, a buffer for driving the data bus, and a semiconductor integrated circuit having a buffer for driving data on the data bus. More specifically, the present invention is suitable for a static RAM (Random Access Memory). Related to hierarchies of data buses.

[0002]

2. Description of the Related Art FIG. 2 shows a conventional example. A conventional circuit outputs an X decoder for decoding an X address, a Y decoder for decoding a Y address, and data held in a plurality of predetermined memory cells via a bit line based on the decoding of the decoder. A memory cell array having a plurality of memory cells for writing input data to predetermined memory cells via bit lines; and a sense amplifier for amplifying output data signals from the predetermined plurality of bit lines. A read buffer for transmitting the output of the sense amplifier to the read data bus, an output circuit for outputting the data of the read data bus, an input circuit for transmitting the input data to the write data bus, and transmitting the data of the write data bus to the read data bus. And a write buffer for transmitting to the bit line based on the decoding of the decoder. The pump and the writing buffer are controlled by a Read / Write control circuit, respectively, by a Read / Write control signal generated using a signal decoded by the Y decoder and a control signal. At this time, the Read and Write control signals include the information of the Y address.

A circuit having such a configuration is described in, for example, IEICE Transactionson Electronics Vovo.
l. E79-C no. 6 June 1996, pp. 735-742.

[0004]

As the memory capacity increases in the future, the number of write buffers, the number of sense amplifiers and the number of read buffers are increased in the conventional circuit.
Alternatively, the capacity can be increased by the following method.

In the conventional example (FIG. 2), there is a normal read Y selector between a memory array and a sense amplifier, and a normal write Y selector between a memory cell and a write buffer. And the common write data line (FIG. 3). Therefore, in order to increase the capacity of the memory, there is a method of increasing the number of bit lines connected to Y select.

However, a write buffer and
When the number of sense amplifiers and read buffers is increased, the load connected to the data bus increases, and the delay time of data transfer from the output of the sense amplifier to the output circuit and from the input circuit to the write buffer increases. Also, if the number of bit lines connected to the Y select is increased, the load connected to the common read data line and the common write data line increases,
The delay time of data transfer from the memory cell to the sense amplifier and data transfer from the write buffer to the memory cell increases. Therefore, in the conventional circuit, if the memory capacity is increased, the delay time of data transfer must be increased. In other words, it will be difficult to satisfy the demand for higher speed, which will be important with the increase in capacity in the future. From this, the delay time of data transfer from the sense amplifier output to the output circuit and from the input circuit to the write buffer, or the delay time of data transfer from the memory cell to the sense amplifier input and from the write buffer to the memory cell is reduced. Shortening is desired. For example, as compared with a cache memory using a 1-Mbit static RAM operating at a read cycle of 133 MHz, a high-speed cache memory having a capacity of more than 200 MHz with a capacity of 2 Mbits has been desired to have a speedup of 10% or more of the delay time.

Accordingly, an object of the present invention is to reduce the load capacitance by layering the data bus, reduce the delay time of data transfer from the output of the sense amplifier to the output circuit and from the input circuit to the write buffer, and reduce the memory capacity. It is an object of the present invention to provide a circuit which satisfies the demand for high speed even if the capacity is increased.

[0008]

In order to achieve the above object, a semiconductor integrated circuit according to the present invention includes a read selector between a sense amplifier and a read buffer.
A sub read data line is provided between the read selector and the read buffer. A write selector is introduced between the write buffer and the common data line, and a sub-write data line is provided between the write buffer and the write selector. As a result, the data bus is hierarchized, the load capacity connected to the data bus is reduced, and the delay time of data transfer from the output of the sense amplifier to the output circuit and from the input circuit to the write buffer can be reduced.

[0009]

Preferred embodiments of a semiconductor integrated circuit according to the present invention will be described below with reference to the accompanying drawings.

FIG. 1 is a circuit diagram showing an embodiment of a semiconductor integrated circuit according to the present invention. The circuit shown in FIG.
An X decoder for decoding address data, a Y decoder for decoding Y address data, and, based on the decoding of the decoder, outputting data held in a plurality of predetermined memory cells via bit lines, A memory cell array having a plurality of memory cells for writing input data to predetermined memory cells via bit lines; a sense amplifier for amplifying output data signals from the predetermined plurality of bit lines; A read selector for selecting one output from a plurality of outputs of the amplifier based on the decoding of the decoder, a read buffer for transmitting data of a sub read data line which is an output of the read selector to a read data bus, An output circuit for outputting the data on the read data bus and transmitting the input data to the write data bus An input circuit, a write buffer for transmitting the data of the write data bus to the sub-write data line, and a write selector for transmitting the data of the sub-write data line to the bit line based on the decoding of the decoder. The above-mentioned sense amplifier, read selector, and write selector are Read / W
The rite control circuit is controlled by Read and Write control signals generated using the signal decoded by the Y decoder and the control signal, respectively. Note that Read and Writ
The e control signal includes the Y address information.

In this system, the data bus can be hierarchized by introducing the sub read data line and the sub write data line, and the load capacity connected to the data bus can be reduced. As a result, the delay time of data transfer from the output of the sense amplifier to the output circuit and from the input circuit to the write buffer can be reduced.

For example, as shown in FIG. 4, when one Y address is input to the read / write control circuit, two sense amplifiers can be connected to the read selector, and the read buffer connected to the data bus is connected. Is half (n / 2) of the conventional (n). Similarly, two common write data line pairs are connected to the write selector, and the number of write buffers connected to the data bus is half (n / 2) of the conventional (n). Furthermore, Y
When two addresses are input to the read / write control circuit, the number of read and write buffers connected to the data bus is reduced to 1/4 of the conventional one.

However, if the number of input Y addresses is increased as it is, the load on the sub read data line and the sub write data line increases, and conversely, the delay time increases. That is, there is an optimal number of input Y addresses. However, the optimum value of the number of inputs differs depending on the memory capacity, chip configuration, and the like.

FIG. 5 shows a second embodiment of the semiconductor integrated circuit according to the present invention. As compared with the first embodiment (FIG. 1), a circuit for latching the sense amplifier output between the sense amplifier and the read selector is introduced. Also in this embodiment, the number of read and write buffers connected to the data bus can be reduced by increasing the number of input Y addresses to the read / write control circuit. Further, also in this case, there is an optimum number of input Y addresses that minimizes the delay time. The optimum value of the number of inputs differs depending on the memory capacity, chip configuration, and the like.

FIG. 6 shows a third embodiment of the semiconductor integrated circuit according to the present invention. The read data bus and the write data bus are common to the first embodiment (FIG. 1). Also in this embodiment, by increasing the number of input Y addresses to the read / write control circuit, the number of read and write buffers connected to a common data bus can be reduced. Further, also in this case, there is an optimum number of input Y addresses that minimizes the delay time. The optimum value of the number of inputs differs depending on the memory capacity, chip configuration, and the like.

FIG. 7 shows a fourth embodiment of the semiconductor integrated circuit according to the present invention. The common read data line and the common write data line are common to the first embodiment (FIG. 2). Also in this embodiment, by increasing the number of input Y addresses to the read / write control circuit, the number of read and write buffers connected to a common data bus can be reduced. Further, also in this case, there is an optimum number of input Y addresses that minimizes the delay time. The optimum value of the number of inputs differs depending on the memory capacity, chip configuration, and the like.

FIG. 8 shows an embodiment of the read selector and the read buffer in the first embodiment (FIG. 1). In the first embodiment (FIG. 1), the read selector has two sense amplifiers. This is the case when the connection is made (FIG. 4). That is, the number of read buffers is half that of the conventional case. In FIG. 8, the read selector includes two PMOSs (MP801 and MP802) and one NMO
S (MN 801). One of the inverted signal pair RY0B of the Read control signal generated by the Read / Write control circuit is input to the gate of MP801, the source is connected to the output of the sense amplifier SA0, and the drain is connected to the sub-read data line SR0. I have. The other of the pair of signal RY1B of the inverted signal of the read control signal generated by the read / write control circuit is input to the gate of MP802, the source is connected to the output of the sense amplifier SA1, and the drain is connected to the sub read data line SR0. I have. One of RY0B and the other R of the inverted signal pair of the read control signal are connected to the gate of MN801.
A signal obtained by taking AND logic of Y1B is input, the source is connected to the ground potential (GND), the drain is connected to the sub-read data line SR0, and the drain and MP801 and MP802 are common. Further, in order to operate the read data bus by the precharge logic, the read buffer is constituted by one NMOS (MN802). The sub read data line SR is connected to the gate of MN802.
0 is input, the source is connected to GND, and the drain is connected to the read data bus. The sense amplifier, the read selector, and the read buffer
Assuming that the read block is (RB (0)), n / 2 read blocks (〜RB (n / 2
-1)) exists. In the circuit having such a configuration, for example, when RY0B is selected and becomes Low, the output (for example, High) of the sense amplifier SA0 is set to the sub read data line S.
Output to R01. At this time, the input of MN801 is L
Since it is ow, the sub-read data line SR0 becomes High without being pulled by GND, and the read buffer MN802 turns ON. As a result, the read data bus is pulled to GND, and the data reaches the output circuit. When the read buffer MN802 turns on, the PMOS (MP803) precharging the read data bus
Is turned off so that the precharge control signal PR becomes High.
h. After the data arrives at the output circuit, the precharge control signal PR goes low and MP803 turns on,
The read data bus is precharged. At this time, R
Y0B is not selected (High), and MP801 is OF
F and MN 801 are turned on, and the sub read data line SR0
1 is disconnected from the output of the sense amplifier SA0 and is grounded to GND. As a result, the read buffer MN802 becomes O
It becomes FF, and no extra current flows from MP 803 to MN 801 and the read data bus is precharged.

For example, when the above embodiment is applied to a 2 Mbit cache SRAM using a 0.4 μm CMOS process, the number of the read blocks connected to the read data bus is reduced from the conventional 16 (= n) to half (= 8). n / 2). That is, the number of read buffers connected to the read data bus is reduced from 16 to eight, which is half the conventional value, and the delay time of data transfer from the output of the sense amplifier to the output circuit can be increased by about 0.2 ns and about 15%. In addition, 2 using this 0.4 μm CMOS process
In an M-bit cache SRAM, the number of read buffers connected to the read data bus was optimally eight due to layout restrictions.

FIG. 9 shows an embodiment of the write selector and the write buffer in the first embodiment (FIG. 1). In the first embodiment (FIG. 1), the write selector has a common write data line pair. This is the case where two are poking. That is, the number of write buffers is half that of the conventional case. In FIG. 9, the write selector includes four NMOSs (MN901, MN902, MN903, MN903).
904). The gate of MN901 is Read
/ W of one Write control signal pair generated by the Write control circuit
Y0 is input, the source is connected to one sub-write data line pair SW01, and the drain is connected to one common write data line pair CWD0. WY0 is input to the gate of MN902 and is common to the gate of MN901, and the source is the other S of the sub-write data line pair.
W01B, and the drain is connected to the other CWD0B of the common write data line pair. The gate of the MN 903 receives the other WY1 of the write control signal pair, the source is connected to SW01, and the drain is connected to one of the common write data line pair CWD1. MN90
WY1 is input to the gate of No. 4 and is shared with the gate of MN903, the source is connected to SW01B, and the drain is connected to the other CWD1B of the common write data line pair. The write buffer includes an inverter (INV901) and two NMOSs (MN905, MN905).
N906). The input of the INV 901 is connected to the write data bus. The gate of the MN 905 is connected to the output of the INV 901, the source is connected to the ground potential (GND), and the drain is connected to one of the sub-write data line pair SW 01, and is common to the sources of the MN 901 and MN 903. The gate of the MN 906 receives the write data bus and is common to the input of the INV 901, the source is connected to GND, and the drain is connected to the other SW01B of the pair of sub-write data lines and the MN 90
2. It is common with the source of MN904. further,
The high potential of the common write data line pair CWD0 and CWD0B is guaranteed by two PMOSs (MP901 and MP902), and three PMOSs (MP903 and MP903).
904, MP905). One of the common write data line pair CWD0 is input to the gate of the MP901, and the other of the common write data line pair CWD0B is connected to the drain. MP
The gate 902 has the other CW of the pair of common write data lines.
D0B is input, and the drain is connected to one of the common write data line pair CWD0. MP901, MP9
02 has a common source and is connected to the power supply voltage (Vdd). The source of MP903 and the drain of MP904 are connected to one of the common write data line pair CWD0, the drain of MP903 and the drain of MP905 are connected to the other CWD0B of the common write data line pair,
The sources of P904 and MP905 are connected to Vdd,
The gates of P903, MP904, and MP905 are connected to the equalization control signal EQ. Similarly, the common write data line pair CWD1 and CWD1B have two PMOSs.
(MP906, MP907) guarantees the High-side potential, and the three PMOSs (MP908, MP909,
MP910). One of the common write data line pair CWD1 is input to the gate of MP906, and the other is connected to the drain of the common write data line pair CWD1B. MP90
7 has the other of the common write data line pair CWD1
B is input, and the drain is connected to one of the common write data line pair CWD1. MP906, MP907
Are common and connected to Vdd. MP
The source of 908 and the drain of MP909 are connected to one of the common write data line pair CWD1, the drain of MP908 and the drain of MP910 are connected to the other CWD1B of the common write data line pair, and MP909, MP91
0 is connected to Vdd and MP908, MP90
9. The gate of MP910 is connected to the equalization control signal EQ. If the write buffer, the write selector, the equalizing PMOS, and the PMOS that guarantees the High potential are 1 write block (WB (0)), n / 2 write blocks (〜WB (〜) are used for n common write line pairs. n / 2-1)) exists. In a circuit having such a configuration, for example, when the write data bus goes low, the MN 904 turns off, the output of the INV 901 goes high, the MN 903 turns on, and one of the sub-write data line pair SW01 goes low. At this time, Wr
The ite control signal WY0 is selected (high)
Then, MN 901 and MN 902 are turned ON, and the common write data line pair (CWD0, CWD0B) and the sub write data line pair (SW01, SW01B) are connected. At this time, the equalization control signal EQ is High, and MP9
03, MP904 and MP905 are OFF
Equalization has been released. As a result, one of the common write data line pair CWD0 becomes Low, and the MN901
Is turned on, and the other CWD0B of the common write data line pair is held at High. After these data are written to the memory cells, the write control signal WY0 becomes non-selected.
(Becomes Low), CWD0, CWD0B and SW01, S
The connection of W01B is disconnected. At this time, the equalization control signal EQ becomes Low, and the MP903, MP904, MP
905 turns on, and the common write data line pair CWD0, CWD
WD0B is precharged to High and returns to the initial state.

For example, when the above embodiment is applied to a 2 Mbit cache SRAM using a 0.4 μm CMOS process, the number of write blocks connected to the write data bus is reduced from eighteen (= n) to eight (= n) in the related art. n / 2). That is, the number of write buffers connected to the write data bus is reduced from 16 to half, ie, eight, and the delay time of the data transfer from the input circuit to the write buffer is about 0.12 ns, which is about 15% faster. . In a 2 Mbit cache SRAM using this 0.4 μm CMOS process, the number of write buffers connected to the write data bus was optimally eight due to layout restrictions.

The preferred embodiment of the present invention has been described above. However, the present invention is not limited to the above-described embodiment, and various design changes can be made without departing from the spirit of the present invention. Of course.

[0022]

As is apparent from the above-described embodiment, according to the present invention, the number of read and write buffers connected to the data bus is reduced, thereby delaying the data transfer from the output of the sense amplifier to the output circuit. The time and the delay time of data transfer from the input circuit to the write buffer can be reduced.

[Brief description of the drawings]

FIG. 1 is a circuit configuration diagram showing one embodiment of a semiconductor integrated circuit according to the present invention.

FIG. 2 is a conventional circuit configuration diagram.

FIG. 3 is a circuit configuration diagram showing a part of the conventional circuit configuration shown in FIG. 2;

FIG. 4 is a circuit configuration diagram in FIG. 1 in which two sense amplifiers are connected to one read selector and two common write data line pairs are connected to one write selector.

FIG. 5 is a circuit configuration diagram showing a second embodiment of the semiconductor integrated circuit according to the present invention.

FIG. 6 is a circuit configuration diagram showing a third embodiment of the semiconductor integrated circuit according to the present invention.

FIG. 7 is a circuit configuration diagram showing a fourth embodiment of the semiconductor integrated circuit according to the present invention.

FIG. 8 is a circuit diagram showing one embodiment of a read selector and a read buffer shown in FIG. 1;

FIG. 9 is a circuit diagram showing an embodiment of a write selector and a write buffer shown in FIG. 1;

[Explanation of symbols]

MP801 to MP910: PMOS transistor, MN
801 to MN906 ... NMOS transistor, Vdd ...
Power supply voltage, GND: ground voltage, SA0 to SA1: sense amplifier, SR01: sub read data line, RY0B,
RY1B: Inversion signal of the read control signal, RB (0) to RB
(N / 2-1) read block, CWD0, CWD0
B, CWD1, CWD1B ... common write data line, S
W01, SW01B ... sub-write data lines, WY0, W
Y1 Write control signal, WB (0) to WB (n / 2-1) Write block.

Continuing from the front page (72) Inventor Kenichi Fukui 5-2-1, Kamizuhoncho, Kodaira-shi, Tokyo Inside the Semiconductor Division, Hitachi, Ltd. No. 1 Hitachi, Ltd. Semiconductor Division (72) Inventor Atsushi Hiraishi 5-20-1, Kamisumihonmachi, Kodaira-shi, Tokyo Incorporated Semiconductor Division, Hitachi Ltd. 5-20-1, Mizumotocho Nichichicho LSI Engineering Co., Ltd.

Claims (8)

[Claims] A decoder for decoding address data; outputting data held in a plurality of predetermined memory cells via a bit line based on the decoding by the decoder; and inputting data to a bit line. A memory cell array having a plurality of memory cells to be written to a predetermined memory cell via a memory cell array; a sense amplifier for amplifying output data signals from a plurality of predetermined bit lines; and a plurality of outputs of the sense amplifier. A read selector for selecting one output based on the decoding of the decoder, a read buffer for transmitting data of a sub read data line, which is an output of the read selector, to a read data bus, and a data of the read data bus. An input circuit for transmitting input data to a write data bus; A write buffer for transmitting scan of the data in the sub write data lines, the data of the sub write data line based on the decoding of the decoder, a semiconductor integrated circuit, characterized in that it comprises a write selector for transmitting the bit line. 2. The semiconductor integrated circuit according to claim 1, wherein said address decoder comprises an X decoder for decoding an X address and a Y decoder for decoding a Y address. 3. The semiconductor integrated circuit according to claim 1, wherein said read data bus and said write data bus are common. 4. The semiconductor integrated circuit according to claim 1, further comprising a circuit for latching a sense amplifier output between said sense amplifier and said read selector. 5. The read selector, wherein each gate is connected to an inverted signal of a decode signal based on the decode of the decoder, each source is connected to the sense amplifier output or the latch output, and each drain is the sub-read. Plural PMOSs connected to data line and common
And the gate is connected to a signal that takes AND logic for all of the signals input to the gates of the plurality of PMOSs,
5. The semiconductor integrated circuit according to claim 1, wherein a source is connected to the first power supply, and a drain is a first NMOS connected to the sub read data line. 6. A read buffer connected to the read selector has a gate connected to the sub read data line, a source connected to the first power supply, and a drain connected to a read data bus or a read / write common data. 6. The semiconductor integrated circuit according to claim 1, comprising a second NMOS connected to a bus. 7. The write selector according to claim 6, wherein the write selector includes a plurality of NMOs.
The plurality of NMOS pairs have a common gate, a decode signal based on the decoding of the decoder is connected, and a source pair is connected to the sub-write data line pair and are common to each other. 7. The semiconductor integrated circuit according to claim 1, wherein said drain pair is connected to a common data line pair connected to a plurality of bit line pairs. 8. A write buffer connected to the write selector, wherein a first inverter whose input is a write data bus or a data bus common to read and write, and a gate are connected to an output of the first inverter. ,
A third NMOS having a source connected to the ground potential and a drain connected to one of the sub-write data line pairs, a source connected to the first power supply, and a drain connected to the other of the sub-write data line pairs; 8. The semiconductor integrated circuit according to claim 1, comprising a fourth NMOS formed.