JPH1153252A - Memory control circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To eliminate the need to change settings of a synchronous DRAM (SDRAM) by a CPU and a bus master at each time and to omit an unnecessary resetting time by altering setting information according to externally indicated conditions and sending it out to the SDRAM, and optionally setting operation conditions of the SDRAM. SOLUTION: This memory control circuit 1 switches various settings that the SDRAM 2 requires automatically when the bus master 4 is switched. In concrete, a setting part which holds various setting information that the SDRAM 2 requires and a setting alteration detection part which detects the switching of the bus master 4 are provided corresponding to the bus master 4. Therefore, software on the side of the switched bus master 4 need not alter the setting information of various SDRAMs 2 that the SDRAMs 2 require at each time and the memory control circuit 1 need not operate the SDRAM 2 under complicated control.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory control circuit, and more particularly to a synchronous DRAM (hereinafter referred to as an SDRAM).
Alternatively, the present invention relates to a memory control circuit for setting operating conditions of a synchronous ROM (hereinafter, referred to as SROM).

[0002]

2. Description of the Related Art Conventionally, this type of memory control circuit has been known as an SD memory card.
The setting values required by the RAM can be easily set from the outside, and when the operating frequency of the CPU is changed, the SDRA
This is to obtain a stable operation without changing the type of M or changing the control circuit of the SDRAM.

For example, according to Japanese Patent Application Laid-Open No. 08-297606, as shown in FIG. 6, an image forming apparatus 70 including a memory control circuit includes an image storage unit 61 having an SDRAM and a set value required by the SDRAM. Setting means 62 for setting reading and writing, setting control means 63 for controlling reading / writing of SDRAM according to the above set values, and image forming means 66
, A ROM / RAM 67, external connection means 68, and control means 69 for the entire apparatus. Then, the external device 60
It is connected to the.

The image forming apparatus 70 stores or reads out the image information received via the external connection means 68 in the SDRAM of the image storage means 61 at a high speed.
At this time, it is necessary to make various settings in addition to the address to be read and written first.

That is, at the time of writing, an address position to be written first and various set values are set in the setting means 62, and these set values are re-stored in a predetermined internal register of the SDRAM of the image storage means 61 by the setting control means 63. After setting, start writing.

[0006] Similarly, at the time of reading, the setting means 62
And the image forming means 66 forms an image based on the read image information.

[0007]

The above-mentioned conventional memory control device has the following disadvantages.

The first problem is that when bus masters having different continuous access lengths and address orders at that time commonly use an SDRAM as a main storage device, various settings required by the SDRAM must be changed. So
Time is wasted.

The reason is that there is only one set of setting information of the setting means for the SDRAM and the S
The DRAM does not operate.

A second problem is to forcibly stop the SDRAM during continuous access as a method for solving the first problem, but in that case, complicated control is required.

The reason is that there is no means for automatically detecting that the bus master has been switched.

An object of the present invention is to provide a device to which different types of bus masters are connected efficiently and simply
An object of the present invention is to provide a memory control circuit which can improve the above-mentioned drawback by sharing a RAM.

[0013]

A memory control circuit according to the present invention is a memory control circuit for a memory device having a synchronous DRAM as a storage element. The memory control circuit holds setting information for setting operating conditions of the synchronous DRAM. The setting information is changed and transmitted to the synchronous DRAM according to the conditions instructed by the synchronous DRAM, and the operating conditions of the synchronous DRAM are arbitrarily set.

The memory control circuit according to the present invention is a memory control circuit for a memory device using a synchronous DRAM as a storage element, wherein the setting section holds setting information for setting operating conditions of the synchronous DRAM; The configuration includes a setting change detection unit that detects an external instruction signal indicating a change in information, and a setting control unit that changes the setting information in accordance with the instruction signal and sends it to the synchronous DRAM.

Further, in the memory control circuit according to the present invention, the setting section holds a plurality of sets of setting information for setting operating conditions of the synchronous DRAM.

Further, in the memory control circuit according to the present invention, the setting change detecting section detects a plurality of external instruction signals indicating a change in setting information.

Further, in the memory control circuit according to the present invention, the setting control section selects one of a plurality of sets of setting information held by the setting section in accordance with a detection result of the setting change detection section, and synchronizes the selected information with the synchronization. To the DRAM.

Further, in the memory control circuit of the present invention,
The synchronous DRAM may be a synchronous ROM.

That is, the memory control circuit of the present invention automatically switches various settings required by the SDRAM when the bus master switches. More specifically, it has a setting unit for separately holding various setting information required by the SDRAM corresponding to the corresponding bus master, and a setting change detection unit for detecting that the bus master has been switched.

Therefore, there is no need for the switched software on the bus master side to change various SDRAM setting information required by the SDRAM each time, or for the memory control circuit to operate the SDRAM with complicated control.

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention. In the figure, a memory control circuit 1
The CPU 3, a bus master 4 that operates differently from the CPU 3, an arbitration circuit 5 that arbitrates when the CPU 3 and the bus master 4 use the bus, and the SDRAM 2 are connected.

When the bus master 4 accesses the SDRAM, the bus request signal to the arbitration circuit 5 is made valid, and after confirming that the bus acknowledge signal from the arbitration circuit 5 becomes valid, the bus is used. Then, access to the SDRAM 2 is performed.

When the SDRAM 2 gives the address of the first reading position during burst reading (continuous reading),
The first data is output after a set time (hereinafter, referred to as CAS latency), and data read in the address order for a length (hereinafter, referred to as burst length) set for each clock from that time is output. Is done.
Similarly, in the case of burst write (continuous writing), if the address of the position to be written first is given and write data is given for each clock, continuous writing is performed in the address order by the amount set as the burst length.

The SDRAM has various settings. The settings for the mode register included in the SDRAM itself include burst length, CAS latency, and the order of addresses during continuous access. Also, as a setting required for the memory control circuit to control the SDRAM,
The number of clocks between a command for giving a row address (hereinafter referred to as an active command) and a command for recognizing read / write while giving a column address (read command, write command), and the number of clocks for continuous access There are settings such as an interval (for example, the interval between the first read data and the second read data), and automatically invalidating the row address after the first continuous access (auto precharge).

FIG. 2 is a block diagram showing the configuration of the memory control circuit 1 described above. In the figure, a memory control circuit 1
A setting unit 10 that can have various SDRAM settings for each bus master, a setting change detection unit 11 that monitors a signal from the arbitration circuit 5 and detects a timing of changing a setting required by the SDRAM, The contents of the mode register are rewritten in accordance with the contents set in the setting unit 10, and the read / write control is performed in accordance with the settings of the setting unit 10 such as the number of clocks from when an address is applied to the SDRAM until the write data is applied. Setting control unit 1
2 is provided.

As a method of changing the burst length of the SDRAM, there are a method of rewriting the mode register and a method of precharging during the burst. The precharge method requires complicated control.

FIG. 3 is a waveform chart showing the operation of the memory control circuit. First, referring to FIGS. 1 and 2, CPU 3 sets a setting value according to the access method in setting section 10. At the same time, the setting control unit 12 sets the mode register of the SDRAM 2 according to the set contents. Then C
PU3 is an SDRAM according to the access of the bus master 4.
Are set in the setting unit 10. The operation up to this point is performed before (A) in FIG. (A) CPU before
When the SDRAM 2 accesses the SDRAM 2, the SDRAM 2 operates stably with the optimum and fastest operation for the operation of the CPU 3.

When the bus master 4 validates the bus request as shown at point (B), the arbitration circuit 5 validates that the CPU has stopped and then validates the acknowledgment to the bus master 4. Immediately after the setting change detection unit 11 detects this operation, a set value according to the operation of the bus master 4 set in (C) is written in the mode register of the SDRAM 2.
Then, during the period (D), the S
Access to DRAM 2 is optimal for bus master 4 operation
It is performed stably with the fastest operation.

Next, as shown at point (E), the bus master 4
When the access to the DRAM 2 is terminated and the bus request is invalidated, the setting change detection unit 11 detects the operation, and immediately thereafter, automatically resets the mode register of the SDRAM 2 to a setting value according to the operation of the CPU 3. .

As described above, the arbitration circuit 5 controls the bus master 4
The mode register of the SDRAM is set when a request is received and when the request is invalidated, and a control signal to the SDRAM at the time of reading / writing is also set according to the value set in the setting unit 10 according to the operation of the access source. Operate.

By the way, the bus master 4 reads and writes data from and to the SDRAM in units of eight words, and the interval between data at the time of reading and writing is every clock. The CPU 3 reads and writes data from and to the SDRAM in units of four words, and the data is read and written at intervals of two clocks. Further, one clock is required between the active command and the read / write command as a set value determined by the operating frequency of the SDRAM 2 and the system, and the CAS latency is 2
It can be operated with.

In the above case, after the power is turned on and before the CPU 3 issues an access request to the SDRAM 2, the CPU 3 sets a set value according to the operation of the CPU in the setting unit 10.
Specifically, the interval between the active command and the read command or the write command is one clock, the CAS latency is two, the burst length is four, the data at the time of burst access (continuous access) is one clock, and at the same time, the setting control unit 12 The same operation as the point (F) in FIG.
The mode register of the RAM 2 is set.

Next, the CPU 3 sets a set value according to the operation of the bus master 4 in another area of the setting unit 10. Specifically, the interval between the active command and the read command or the write command is 1 clock, the CAS latency is 2,
The burst length is set to 8, and data for burst access is set every two clocks.

Thereafter, when the CPU 3 reads the SDRAM 2, 4-word data is read every two clocks as shown in FIG. 4B. Further, the bus request from the bus master 4 is accepted, and the bus master 4
When the RAM 2 is read, 8-word data is read every clock, as shown in FIG.

FIG. 5 is a block diagram showing a second embodiment of the present invention. In FIG. 1, a memory control circuit 1a is connected to a plurality of bus masters 41 to 4n and an arbitration circuit 5a, and controls the SDRAM 2 according to an instruction from the CPU 3. That is, the memory control circuit 1a includes a setting unit and a setting change detection unit corresponding to the n bus masters.

The above memory control circuit is an SDRAM
Is controlled in the same manner as SDRAM.
(Referred to as SROM).

[0038]

As described above, according to the present invention, the following effects can be obtained.

The first effect is that the CPU and the bus master are SD
Since the setting of the RAM does not have to be changed each time, a wasteful resetting time can be omitted. The reason is SD
This is because two or more sets of RAM setting information (for the number of bus masters) can be set.

The second effect is that the SDRAM can be accessed efficiently without performing complicated control of stopping the burst by the precharge command during the burst access. The reason is that the timing for changing the setting can be automatically detected and the setting can be made using information registered in advance.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a block diagram showing a memory control circuit in FIG. 1;

FIG. 3 is a waveform chart showing the operation of the present invention.

FIG. 4 is a waveform chart showing a specific example of the operation of the present invention.

FIG. 5 is a block diagram showing a second embodiment of the present invention.

FIG. 6 is an explanatory view showing a conventional example of the present invention.

[Explanation of symbols]

 Reference Signs List 1 memory control circuit 2 SDRAM 3 CPU 4 bus master 5 arbitration circuit 10 setting unit 11 setting change detection unit 12 setting control unit

Claims (6)

[Claims] A memory control circuit of a memory device having a synchronous DRAM as a storage element holds setting information for setting an operating condition of the synchronous DRAM and changes the setting information according to a condition externally specified. The synchronous type D
A memory control circuit for sending to a RAM and arbitrarily setting operating conditions of the synchronous DRAM. 2. A memory control circuit of a memory device having a synchronous DRAM as a storage element, wherein a setting unit for holding setting information for setting an operation condition of the synchronous DRAM; A memory control circuit, comprising: a setting change detection unit that detects an instruction signal; and a setting control unit that changes the setting information according to the instruction signal and sends the same to the synchronous DRAM. 3. The memory control circuit according to claim 2, wherein the setting unit holds a plurality of sets of setting information for setting an operation condition of the synchronous DRAM. 4. The memory control circuit according to claim 2, wherein said setting change detection section detects a plurality of external instruction signals indicating a change in setting information. 5. The memory control circuit according to claim 2, wherein the setting control unit selects one of a plurality of sets of setting information held by the setting unit according to a detection result of the setting change detection unit. A memory control circuit for transmitting the same to the synchronous DRAM. 6. The memory control circuit according to claim 1, wherein said synchronous DRAM is a synchronous ROM.