JPH1154576A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH1154576A JPH1154576A JP9209436A JP20943697A JPH1154576A JP H1154576 A JPH1154576 A JP H1154576A JP 9209436 A JP9209436 A JP 9209436A JP 20943697 A JP20943697 A JP 20943697A JP H1154576 A JPH1154576 A JP H1154576A
- Authority
- JP
- Japan
- Prior art keywords
- electrode pads
- semiconductor device
- electrode pad
- auxiliary electrode
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/931—Shapes of bond pads
- H10W72/932—Plan-view shape, i.e. in top view
Landscapes
- Tests Of Electronic Circuits (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
(57)【要約】
【課題】 測定の前に、特性測定用回路の電極パッドと
測定用端子の導通状態の確認を行なうことができる半導
体装置を提供する。
【解決手段】 基板１１上に、製品としての機能を有す
る本体回路と別個に設けられ複数の素子により構成され
た特性測定用回路１２を備え、特性測定用回路１２には
基板１１と電気的に絶縁された複数個の電極パッド１
３、１４が設けられ、電極パッド１３、１４各々には、
補助電極パッド１５、１６が設けられていることを特徴
とする。
(57) [Problem] To provide a semiconductor device capable of confirming a conduction state between an electrode pad of a characteristic measurement circuit and a measurement terminal before measurement. SOLUTION: A substrate 11 is provided with a characteristic measuring circuit 12 which is provided separately from a main body circuit having a function as a product and is constituted by a plurality of elements, and the characteristic measuring circuit 12 is electrically connected to the substrate 11. A plurality of insulated electrode pads 1
3 and 14 are provided, and each of the electrode pads 13 and 14 is
It is characterized in that auxiliary electrode pads 15 and 16 are provided.
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体装置に関
し、特に、製造工程における素子特性を測定するための
特性測定用回路を備えた半導体装置に関するものであ
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a characteristic measuring circuit for measuring element characteristics in a manufacturing process.
【０００２】[0002]
【従来の技術】図６は従来の製造工程における特性測定
用回路の１種であるショートチェックＴＥＧ（Test Ele
ment Group）を示す平面図、図７は図６のＡ−Ａ線に沿
う断面図であり、図において、１はリンが添加されたＰ
型単結晶シリコンからなるシリコン基板、２はシリコン
基板１上に設けられた櫛形状のショートチェックパター
ン、３、４はショートチェックパターン２に接続された
電極パッドである。2. Description of the Related Art FIG. 6 shows a short check TEG (Test Ele) which is a kind of a circuit for measuring characteristics in a conventional manufacturing process.
7 is a cross-sectional view taken along the line AA in FIG. 6, where 1 is P to which phosphorus is added.
Reference numeral 2 denotes a comb-shaped short check pattern provided on the silicon substrate 1, and reference numerals 3 and 4 denote electrode pads connected to the short check pattern 2.
【０００３】ショートチェックパターン２及び電極パッ
ド３、４は、リンが添加されたポリシリコン（多結晶シ
リコン）により構成されている。そして、ショートチェ
ックＴＥＧ全体、すなわちショートチェックパターン２
及び電極パッド３、４は、シリコン基板１と、絶縁膜で
あるシリコン酸化膜５により電気的に絶縁されている。The short check pattern 2 and the electrode pads 3 and 4 are made of phosphorus-doped polysilicon (polycrystalline silicon). Then, the entire short check TEG, that is, short check pattern 2
The electrode pads 3 and 4 are electrically insulated from the silicon substrate 1 by a silicon oxide film 5 which is an insulating film.
【０００４】このショートチェックＴＥＧでは、測定用
の１対の端子を電極パッド３、４にそれぞれ当接し、こ
れらの端子を介して電極パッド３、４間に５Ｖの電圧を
印加し、両端子間の電流の大きさが１ｐＡ以下であれば
合格（良品）とし、１ｐＡを超えるとショート不良と判
定して不合格（不良品）としている。In this short check TEG, a pair of terminals for measurement abut against the electrode pads 3 and 4, respectively, and a voltage of 5 V is applied between the electrode pads 3 and 4 via these terminals, and a voltage between both terminals is increased. If the magnitude of the current is 1 pA or less, it is judged as pass (non-defective), and if it exceeds 1 pA, it is judged as short-circuit failure and judged as reject (defective).
【０００５】[0005]
【発明が解決しようとする課題】従来のショートチェッ
クＴＥＧの問題点は、電極パッド３、４と測定端子との
間の導通状態を確認せずに測定を行っているために、実
際は電極パッド３、４間が導通状態にあった場合であっ
ても、誤って合格と判定する虞があるという点である。The problem of the conventional short check TEG is that the measurement is performed without confirming the continuity between the electrode pads 3 and 4 and the measuring terminal. 4 is that even if the connection between the four is in a conductive state, there is a possibility that a pass is erroneously determined.
【０００６】例えば、電極パッド３の表面に絶縁膜等の
絶縁材料が付着してしまった様な場合、電極パッド３と
端子との間が絶縁状態になってしまうために、実際は電
極パッド３、４間が導通状態になっていたにもかかわら
ず、両端子間に電圧を印加しても電流が流れず、誤って
合格と判定してしまうことがあった。シリコン基板１と
電極パッド３、４が電気的に導通した状態であれば、シ
リコン基板１と電極パッド３、４間で導通チェックを行
なえばよいが、これらの間が絶縁されているためにそれ
も不可能な状態である。For example, when an insulating material such as an insulating film adheres to the surface of the electrode pad 3, the electrode pad 3 and the terminal are in an insulated state. Even though a voltage was applied between the four terminals, current did not flow even when a voltage was applied between the two terminals, and a pass was erroneously determined. If the silicon substrate 1 and the electrode pads 3 and 4 are electrically connected, a continuity check may be performed between the silicon substrate 1 and the electrode pads 3 and 4. Is also impossible.
【０００７】本発明は上記の事情に鑑みてなされたもの
であって、測定の前に、特性測定用回路の電極パッドと
測定用端子の導通状態の確認を行なうことができる半導
体装置を提供することにある。The present invention has been made in view of the above circumstances, and provides a semiconductor device capable of confirming the continuity between an electrode pad of a characteristic measuring circuit and a measuring terminal before measurement. It is in.
【０００８】[0008]
【課題を解決するための手段】上記課題を解決するため
に、本発明は次の様な半導体装置を採用した。すなわ
ち、請求項１記載の半導体装置は、基板上に、製品とし
ての機能を有する本体回路と別個に設けられ複数の素子
により構成された特性測定用回路を備えたもので、該特
性測定用回路に前記基板と電気的に絶縁された電極パッ
ドを複数個設け、前記電極パッド各々に補助電極パッド
を設けたものである。In order to solve the above-mentioned problems, the present invention employs the following semiconductor device. In other words, the semiconductor device according to claim 1 is provided with a characteristic measuring circuit which is provided separately from a main body circuit having a function as a product on a substrate and includes a plurality of elements. A plurality of electrode pads that are electrically insulated from the substrate, and an auxiliary electrode pad is provided for each of the electrode pads.
【０００９】請求項２記載の半導体装置は、前記電極パ
ッド及び補助電極パッドを、絶縁膜を介して前記基板上
に設けたものである。According to a second aspect of the present invention, in the semiconductor device, the electrode pad and the auxiliary electrode pad are provided on the substrate via an insulating film.
【００１０】請求項３記載の半導体装置は、前記基板を
絶縁体基板とし、該絶縁体基板上に前記電極パッド及び
補助電極パッドを設けたものである。According to a third aspect of the present invention, in the semiconductor device, the substrate is an insulator substrate, and the electrode pads and the auxiliary electrode pads are provided on the insulator substrate.
【００１１】請求項４記載の半導体装置は、前記特性測
定用回路を、製造工程における素子特性を測定するため
のＴＥＧとしたものである。According to a fourth aspect of the present invention, in the semiconductor device, the characteristic measuring circuit is a TEG for measuring element characteristics in a manufacturing process.
【００１２】請求項５記載の半導体装置は、前記ＴＥＧ
を、ショートチェックＴＥＧとしたものである。According to a fifth aspect of the present invention, in the semiconductor device, the TEG
Is a short check TEG.
【００１３】本発明の半導体装置では、特性測定用回路
に設けられた複数個の電極パッド各々に補助電極パッド
を設けたことにより、前記特性測定用回路の測定を行な
う前に、前記電極パッドと前記補助電極パッドそれぞれ
に測定端子を当接させ、両端子間に電圧を印加すること
により、前記電極パッドと測定端子との間の導通状態を
確認する。これにより、前記電極パッドと測定端子との
間の導通状態を確認した上で測定することが可能にな
り、正確な測定が行なわれ、不良品を誤って良品と判定
してしまう虞も無くなる。In the semiconductor device according to the present invention, the auxiliary electrode pads are provided on each of the plurality of electrode pads provided on the characteristic measuring circuit, so that the electrode pads and the electrode pads are measured before the characteristic measuring circuit is measured. A measurement terminal is brought into contact with each of the auxiliary electrode pads, and a voltage is applied between the two terminals to check a conduction state between the electrode pad and the measurement terminal. As a result, it is possible to perform the measurement after confirming the conduction state between the electrode pad and the measurement terminal, so that accurate measurement is performed and there is no possibility that a defective product is erroneously determined as a non-defective product.
【００１４】[0014]
【発明の実施の形態】以下、本発明の半導体装置の各実
施形態について図面に基づき説明する。Embodiments of the present invention will be described below with reference to the accompanying drawings.
【００１５】（第１の実施形態）図１は本発明の第１の
実施形態の半導体装置の特性測定用回路を示す平面図、
図２は図１のＢ−Ｂ線に沿う断面図であり、図におい
て、１１はシリコン基板、１２はシリコン基板１１上に
設けられたＴＥＧ等の特性測定用回路、１３、１４は特
性測定用回路１２に設けられた電極パッド、１５は電極
パッド１３に設けられた補助電極パッド、１６は電極パ
ッド１４に設けられた補助電極パッドである。(First Embodiment) FIG. 1 is a plan view showing a circuit for measuring characteristics of a semiconductor device according to a first embodiment of the present invention.
FIG. 2 is a cross-sectional view taken along the line BB of FIG. 1. In the drawing, 11 is a silicon substrate, 12 is a circuit for measuring characteristics such as TEG provided on the silicon substrate 11, and 13 and 14 are for measuring characteristics. An electrode pad provided on the circuit 12, 15 is an auxiliary electrode pad provided on the electrode pad 13, and 16 is an auxiliary electrode pad provided on the electrode pad 14.
【００１６】ここでは、１つの電極パッド１３（１４）
には、ただ１つの補助電極パッド１５（１６）が設けら
れている。この特性測定用回路１２は、厚さが３００〜
７００μｍ程度のシリコン基板１１上に形成されたもの
で、厚さが３００〜２０００Å程度のシリコン酸化膜
（絶縁膜）５を介して電気的に絶縁されている。Here, one electrode pad 13 (14)
Is provided with only one auxiliary electrode pad 15 (16). This characteristic measuring circuit 12 has a thickness of 300 to
It is formed on a silicon substrate 11 having a thickness of about 700 μm, and is electrically insulated through a silicon oxide film (insulating film) 5 having a thickness of about 300 to 2000 °.
【００１７】電極パッド１３、１４及び補助電極パッド
１５、１６は、厚さが１０００〜５０００Å程度、一辺
の長さが５０〜１００μｍ程度のもので、リンがドープ
されたポリシリコン、アルミニウム、タングステン等の
導電物質により構成されており、シリコン基板１１と
は、図２に示すように、厚さが３００〜２０００Å程度
のシリコン酸化膜５を介して電気的に絶縁されている。The electrode pads 13 and 14 and the auxiliary electrode pads 15 and 16 have a thickness of about 1000 to 5000 ° and a side length of about 50 to 100 μm, and are doped with phosphorus-doped polysilicon, aluminum, tungsten, or the like. As shown in FIG. 2, it is electrically insulated from the silicon substrate 11 via a silicon oxide film 5 having a thickness of about 300 to 2000 °.
【００１８】次に、電極パッド１３、１４及び補助電極
パッド１５、１６を用いた測定方法について説明する。
まず、特性測定用回路１２の測定を行なう前に、電極パ
ッド１３と補助電極パッド１５それぞれに測定端子を当
接し、電極パッド１３と補助電極パッド１５が導通して
いるか否かを確認する。また、電極パッド１４と補助電
極パッド１６についても同様の確認をする。Next, a measuring method using the electrode pads 13 and 14 and the auxiliary electrode pads 15 and 16 will be described.
First, before measuring the characteristic measuring circuit 12, the measurement terminals are brought into contact with the electrode pads 13 and the auxiliary electrode pads 15, respectively, and it is checked whether the electrode pads 13 and the auxiliary electrode pads 15 are conducting. The same check is performed for the electrode pad 14 and the auxiliary electrode pad 16.
【００１９】もし、導通していない様ならば原因を調
べ、対策を講じてから同様の導通の確認を再度行なう。
この電極パッド１３と補助電極パッド１５との導通及び
電極パッド１４と補助電極パッド１６との導通が確認で
きた後に、特性測定用回路１２の測定を行なえば、正確
な測定を行なうことができる。If the continuity does not occur, the cause is investigated, countermeasures are taken, and the same continuity is confirmed again.
After the continuity between the electrode pad 13 and the auxiliary electrode pad 15 and the continuity between the electrode pad 14 and the auxiliary electrode pad 16 have been confirmed, if the measurement of the characteristic measuring circuit 12 is performed, accurate measurement can be performed.
【００２０】ここで、本発明の第１の実施形態を適用し
た一例であるショートチェックＴＥＧについて説明す
る。図３はショートチェックＴＥＧを示す平面図であ
り、図において、２１、２２は、シリコン基板１１上に
設けられた櫛形状のショートチェックパターン２に接続
された電極パッド、２３は電極パッド２１に設けられた
補助電極パッド、２４は電極パッド２２に設けられた補
助電極パッドである。Here, a short check TEG, which is an example to which the first embodiment of the present invention is applied, will be described. FIG. 3 is a plan view showing the short check TEG. In the drawing, reference numerals 21 and 22 denote electrode pads connected to the comb-shaped short check pattern 2 provided on the silicon substrate 11, and reference numeral 23 denotes an electrode pad 21. The auxiliary electrode pads 24 are auxiliary electrode pads provided on the electrode pads 22.
【００２１】電極パッド２１、２２及び補助電極パッド
２３、２４は、いずれもリンが添加されたポリシリコン
により形成されており、層抵抗は６０Ω／□、厚さ４０
００Å、一辺の長さが５０μｍである。このショートチ
ェックＴＥＧは、上述した特性測定用回路１２と同様
に、厚さ７００μｍのシリコン基板１１とは、１０００
Åの厚さのシリコン酸化膜５で絶縁されている。Each of the electrode pads 21 and 22 and the auxiliary electrode pads 23 and 24 is formed of polysilicon to which phosphorus is added, and has a layer resistance of 60 Ω / □ and a thickness of 40Ω.
00 °, and the length of one side is 50 μm. This short check TEG is, like the characteristic measuring circuit 12 described above, a 1000 μm thick silicon substrate 11
It is insulated by a silicon oxide film 5 having a thickness of Å.
【００２２】次に、このショートチェックＴＥＧの測定
方法について説明する。まず、ショートチェックの測定
を行なう前に、電極パッド２１と補助電極パッド２３そ
れぞれに測定端子を当接し、電極パッド２１と補助電極
パッド２３が導通しているか否かを確認するために、両
端子間に５Ｖの電圧を印加し、電流が１０μＡ以上流れ
るか否かを確認する。また、電極パッド２２と補助電極
パッド２４についても同様の確認をする。Next, a method of measuring the short check TEG will be described. First, before the measurement of the short check, the measurement terminals are brought into contact with the electrode pads 21 and the auxiliary electrode pads 23, respectively. In order to confirm whether or not the electrode pads 21 and the auxiliary electrode pads 23 are conducting, both terminals are connected. A voltage of 5 V is applied in between, and it is confirmed whether or not a current flows by 10 μA or more. The same check is performed for the electrode pad 22 and the auxiliary electrode pad 24.
【００２３】もし、電流値が１０μＡ未満ならば原因を
調査し、対策を講じてから同様の導通の確認を再度行な
う。この電極パッド２１と補助電極パッド２３との間及
び電極パッド２２と補助電極パッド２４との間に電流が
１０μＡ以上流れていることが確認できた後に、ショー
トチェックを行えば、正確な測定値を得ることができ
る。If the current value is less than 10 μA, the cause is investigated, countermeasures are taken, and the same conduction is confirmed again. After confirming that a current of 10 μA or more flows between the electrode pad 21 and the auxiliary electrode pad 23 and between the electrode pad 22 and the auxiliary electrode pad 24, an accurate measurement value can be obtained by performing a short check. Obtainable.
【００２４】本実施形態の半導体装置の特性測定用回路
によれば、測定用の電極パッド１３、１４各々に補助電
極パッド１５、１６を設け、測定を行なう前に、電極パ
ッド１３（１４）と補助電極パッド１５（１６）との間
で導通しているか否かの確認を行ない、導通しているこ
とを確認してから測定するので、測定前に電極パッド１
３、１４と測定端子との間が確実に導通しているか否か
の確認を行うことができ、正確な測定値を得ることがで
きる。According to the characteristic measuring circuit of the semiconductor device of the present embodiment, the auxiliary electrode pads 15 and 16 are provided on the measuring electrode pads 13 and 14, respectively. It is checked whether or not there is electrical continuity with the auxiliary electrode pad 15 (16), and the measurement is performed after confirming that there is electrical continuity.
It is possible to confirm whether or not there is electrical continuity between the measurement terminals 3 and 14 and the measurement terminals, and to obtain accurate measurement values.
【００２５】なお、電極パッド１３（１４）と補助電極
パッド１５（１６）との接続は、導通チェックができ
て、しかも特性測定用回路１２に影響を及ぼさなければ
何処でも良い。また、電極パッド１３、１４と補助電極
パッド１５、１６の位置関係は、測定に影響を及ぼさな
いかぎり特に限定する必要はない。これは、ショートチ
ェックＴＥＧの電極パッド２１、２２及び補助電極パッ
ド２３、２４についても同様である。The connection between the electrode pads 13 (14) and the auxiliary electrode pads 15 (16) may be made anywhere as long as the continuity can be checked and the characteristic measuring circuit 12 is not affected. The positional relationship between the electrode pads 13 and 14 and the auxiliary electrode pads 15 and 16 does not need to be particularly limited as long as it does not affect the measurement. This is the same for the electrode pads 21 and 22 and the auxiliary electrode pads 23 and 24 of the short check TEG.
【００２６】さらに、電極パッド１３（１４）に補助電
極パッド１５（１６）を設けるという本実施形態は、Ｔ
ＥＧに限らず、全ての回路の電極パッドに適用できるこ
とはいうまでもない。Further, in this embodiment in which the auxiliary electrode pads 15 (16) are provided on the electrode pads 13 (14),
It goes without saying that the present invention can be applied not only to EG but also to electrode pads of all circuits.
【００２７】（第２の実施形態）図４は本発明の第２の
実施形態の半導体装置の特性測定用回路を示す平面図、
図５は図４のＣ−Ｃ線に沿う断面図であり、図におい
て、３１は絶縁体基板である。この特性測定用回路１２
は、厚さが３００〜７００μｍ程度の絶縁体基板３１上
に直接形成されたもので電気的に絶縁されている。FIG. 4 is a plan view showing a circuit for measuring characteristics of a semiconductor device according to a second embodiment of the present invention.
FIG. 5 is a cross-sectional view taken along line CC of FIG. 4, and in the figure, reference numeral 31 denotes an insulator substrate. This characteristic measuring circuit 12
Are directly formed on the insulator substrate 31 having a thickness of about 300 to 700 μm and are electrically insulated.
【００２８】電極パッド１３、１４及び補助電極パッド
１５、１６は、上述した第１の実施形態と同様に、厚さ
が１０００〜５０００Å程度、一辺の長さが５０〜１０
０μｍ程度のもので、リンがドープされたポリシリコ
ン、アルミニウム、タングステン等の導電物質により構
成されており、絶縁体基板３１上に直接形成されてい
る。The electrode pads 13 and 14 and the auxiliary electrode pads 15 and 16 have a thickness of about 1000 to 5000 ° and a side length of 50 to 10 as in the first embodiment.
It has a thickness of about 0 μm, is made of a conductive material such as polysilicon doped with phosphorus, aluminum, and tungsten, and is formed directly on the insulator substrate 31.
【００２９】この特性測定用回路１２の場合において
も、上述した第１の実施形態と同様に、補助電極パッド
１５、１６を用いて導通の確認を行い、導通しているこ
とを確認してから測定を行えば、正確な測定値が得られ
る。なお、絶縁体基板３１上に特性測定用回路１２を形
成するには、例えば、絶縁体基板３１上に半導体薄膜を
形成した後、既知の製造方法を用いて容易に形成するこ
とができる。In the case of the characteristic measuring circuit 12, as in the first embodiment, the conduction is confirmed using the auxiliary electrode pads 15 and 16, and after the conduction is confirmed. If the measurement is performed, an accurate measurement value can be obtained. In order to form the characteristic measuring circuit 12 on the insulator substrate 31, for example, after forming a semiconductor thin film on the insulator substrate 31, it can be easily formed by using a known manufacturing method.
【００３０】[0030]
【発明の効果】以上説明した様に、本発明の半導体装置
によれば、特性測定用回路に設けられた複数個の電極パ
ッド各々に補助電極パッドを設けたので、前記特性測定
用回路の測定を行なう前に、前記電極パッドと測定端子
との間の導通状態を確認するので、前記電極パッドと測
定端子との間の導通状態を確認した上で測定することが
でき、正確な測定を行なうことができ、不良品を誤って
良品と判定してしまう虞が無くなるという効果を奏する
ことができる。As described above, according to the semiconductor device of the present invention, since the auxiliary electrode pads are provided for each of the plurality of electrode pads provided in the characteristic measuring circuit, the measurement of the characteristic measuring circuit is performed. Before conducting the measurement, the conduction state between the electrode pad and the measurement terminal is checked, so that the measurement can be performed after confirming the conduction state between the electrode pad and the measurement terminal, and accurate measurement can be performed. Therefore, there is an effect that there is no possibility that a defective product is erroneously determined as a non-defective product.
【図１】 本発明の第１の実施形態の半導体装置の特性
測定用回路を示す平面図である。FIG. 1 is a plan view showing a circuit for measuring characteristics of a semiconductor device according to a first embodiment of the present invention.
【図２】 図１のＢ−Ｂ線に沿う断面図である。FIG. 2 is a sectional view taken along line BB of FIG.
【図３】 本発明の第１の実施形態を適用した一例であ
るショートチェックＴＥＧを示す平面図である。FIG. 3 is a plan view showing a short check TEG as an example to which the first embodiment of the present invention is applied.
【図４】 本発明の第２の実施形態の半導体装置の特性
測定用回路を示す平面図である。FIG. 4 is a plan view showing a circuit for measuring characteristics of a semiconductor device according to a second embodiment of the present invention.
【図５】 図４のＣ−Ｃ線に沿う断面図である。FIG. 5 is a sectional view taken along line CC of FIG. 4;
【図６】 従来のショートチェックＴＥＧを示す平面図
である。FIG. 6 is a plan view showing a conventional short check TEG.
【図７】 図６のＡ−Ａ線に沿う断面図である。FIG. 7 is a sectional view taken along line AA of FIG.
１ シリコン基板 ２ ショートチェックパターン ３、４ 電極パッド ５ シリコン酸化膜（絶縁膜） １１ シリコン基板 １２ 特性測定用回路 １３、１４ 電極パッド １５、１６ 補助電極パッド ２１、２２ 電極パッド ２３、２４ 補助電極パッド ３１ 絶縁体基板 REFERENCE SIGNS LIST 1 silicon substrate 2 short check pattern 3, 4 electrode pad 5 silicon oxide film (insulating film) 11 silicon substrate 12 characteristic measuring circuit 13, 14 electrode pad 15, 16 auxiliary electrode pad 21, 22 electrode pad 23, 24 auxiliary electrode pad 31 Insulator substrate
Claims (5)
体回路と別個に設けられ複数の素子により構成された特
性測定用回路を備え、該特性測定用回路には前記基板と
電気的に絶縁された電極パッドが複数個設けられた半導
体装置において、 前記電極パッド各々には、補助電極パッドが設けられて
いることを特徴とする半導体装置。1. A circuit for measuring characteristics which is provided separately from a main circuit having a function as a product on a substrate and is constituted by a plurality of elements, wherein the circuit for measuring characteristics is electrically insulated from the substrate. A semiconductor device provided with a plurality of electrode pads provided, wherein each of the electrode pads is provided with an auxiliary electrode pad.
絶縁膜を介して前記基板上に設けられていることを特徴
とする請求項１記載の半導体装置。2. The electrode pad and the auxiliary electrode pad,
2. The semiconductor device according to claim 1, wherein the semiconductor device is provided on the substrate via an insulating film.
体基板上に前記電極パッド及び補助電極パッドが設けら
れていることを特徴とする請求項１記載の半導体装置。3. The semiconductor device according to claim 1, wherein said substrate is an insulator substrate, and said electrode pads and auxiliary electrode pads are provided on said insulator substrate.
る素子特性を測定するためのＴＥＧであることを特徴と
する請求項１記載の半導体装置。4. The semiconductor device according to claim 1, wherein said characteristic measuring circuit is a TEG for measuring element characteristics in a manufacturing process.
であることを特徴とする請求項４記載の半導体装置。5. The TEG is a short check TEG.
The semiconductor device according to claim 4, wherein
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9209436A JPH1154576A (en) | 1997-08-04 | 1997-08-04 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9209436A JPH1154576A (en) | 1997-08-04 | 1997-08-04 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH1154576A true JPH1154576A (en) | 1999-02-26 |
Family
ID=16572838
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9209436A Pending JPH1154576A (en) | 1997-08-04 | 1997-08-04 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH1154576A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112294326A (en) * | 2020-12-01 | 2021-02-02 | 天津九安医疗电子股份有限公司 | A flexible blood glucose electrochemical test probe and its assembly method |
-
1997
- 1997-08-04 JP JP9209436A patent/JPH1154576A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112294326A (en) * | 2020-12-01 | 2021-02-02 | 天津九安医疗电子股份有限公司 | A flexible blood glucose electrochemical test probe and its assembly method |
| CN112294326B (en) * | 2020-12-01 | 2025-09-23 | 天津九安医疗电子股份有限公司 | A flexible blood glucose electrochemical test probe and its assembly method |
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