JPH1165892A - Control device - Google Patents

Abstract

(57) [Problem] To provide a control device having a simple circuit configuration and capable of confirming an abnormal operation of a monitoring circuit itself. In a control device for monitoring an abnormal operation of a control circuit, a control circuit that reads a target value signal and outputs a set value signal having the same value as the target value signal, outputs a target value signal to the control circuit, and outputs the target value signal A monitoring circuit that resets the measurement time and changes the value of the target value signal when the value of the set value signal and the set value signal match, and outputs a reset signal to the control circuit when the measurement time reaches a certain time. Is provided.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a control device for monitoring an abnormal operation of a control circuit, and more particularly to a control device having a simple circuit configuration and capable of confirming an abnormal operation of the monitor circuit itself.

[0002]

2. Description of the Related Art Conventionally, in a control device installed in a field or the like, it is necessary to minimize adverse effects on external devices when a failure occurs in the control device due to its nature.

[0003] Specifically, an abnormal control signal is output to a field device connected to the control device, a data bus on the system side is blocked, and other operations that damage the entire system are performed. Had to be prevented.

For this reason, the conventional control device is provided with a monitoring circuit such as a watch dog timer (hereinafter referred to as WDT), and abnormal operation of the control device, specifically, a control circuit such as a microprocessor. Detect abnormal operation.

If an abnormal operation of the control circuit is detected, the WDT resets the control circuit and disconnects the connection on the system side.

FIG. 5 is a block diagram showing the configuration of such a conventional control device. In FIG. 5, 1 is a control circuit such as a microprocessor for controlling a control device, 2 is an address decoder circuit, 3 is an AND circuit, 4 is a monitoring circuit such as a conventional WDT, 5 is a switch circuit, and 100 is data on the system side. A bus, 101 is an address signal, 102 is a write enable signal, 103 is a chip select signal, and 104 is a reset signal.

The data bus 100 is connected to the control circuit 1 via the switch circuit 5, and an address signal 101 from the control circuit 1 is connected to the address decoder circuit 2. Chip select signal 1 output from address decoder circuit 2
03 is connected to one input terminal of the AND circuit 3.

The write enable signal 102 from the control circuit 1 is connected to the other input terminal of the AND circuit 3, and the output of the AND circuit 3 is connected to the timer reset terminal of the monitoring circuit 4.

A reset signal 104 output from the monitoring circuit 4 is connected to a reset terminal of the control circuit 1 and a control terminal of the switch circuit 5, respectively.

Now, the operation of the conventional example shown in FIG. 5 will be described. The control circuit 1 is provided with a routine for performing a periodic writing operation to the monitoring circuit 4 to which an address is assigned during the program.

On the other hand, the monitoring circuit 4 measures the time by a timer circuit provided therein and outputs a reset signal 104 when a predetermined time is reached. When the timer reset terminal of the monitoring circuit 4 becomes "active", the timer circuit 4 Reset the time measured by.

If the control circuit 1 is operating normally, write processing to the monitoring circuit 4 is performed periodically.

More specifically, an address signal 101 and a data signal (not shown) allocated from the control circuit 1 to the monitoring circuit 4 are synchronously output, and the write enable signal 1
02 becomes “high level”.

Address signal 101 is decoded by address decoder circuit 2 and chip select signal 103
Becomes "high level", the output of the AND circuit 3 becomes "high level".

Therefore, the timer circuit of the monitoring circuit 4 is reset and the reset signal 104 is not output, so that the control circuit 1 continues to operate.

If the control circuit 1 operates abnormally, the write processing to the monitoring circuit 4 is not performed periodically.

For this reason, the timer circuit of the monitoring circuit 4 is not reset and reaches a certain time, and the reset signal 104 is output.

When the reset signal 104 is output, the control circuit 1 is reset and its abnormal operation is forcibly terminated, the switch circuit 5 becomes "off", and the connection with the data bus 100 is cut off.

As a result, even when a failure occurs in the control device, it is possible to suppress adverse effects on external devices.

[0020]

However, in the conventional example shown in FIG. 5, the timer reset operation of the monitoring circuit 4 is performed by a write operation to a specific address. For this reason, if the clock of the control circuit 1 stops during this write operation, the output of the AND circuit 3 is fixed at "high level", and the timer circuit of the monitoring circuit 4 remains reset. The monitoring circuit 4 stops functioning.

Also, when an abnormal operation such as a write operation to all addresses occurs, the timer circuit of the monitoring circuit 4 is reset, so that the monitoring circuit 4 does not function.

Further, in the recent control circuit 1, a memory circuit and I
MPU that incorporates peripheral circuits such as the I / O circuit (Micr
In some cases, the address decoder circuit 3 is unnecessary, and in this case, it is necessary to provide the address decoder circuit 3 and the like for the monitoring circuit 4, which increases the number of circuit components and leads to an increase in cost.

Further, there is a problem that the control circuit 1 has no method for confirming whether the monitoring circuit 4 is operating normally. Therefore, an object of the present invention is to realize a control device having a simple circuit configuration and capable of confirming an abnormal operation of the monitoring circuit itself.

[0024]

According to a first aspect of the present invention, a control device for monitoring an abnormal operation of a control circuit reads a target value signal and outputs a signal having the same value as the target value signal. A control circuit for outputting a set value signal, outputting the target value signal to the control circuit, and resetting a measurement time when the value of the target value signal matches the value of the set value signal, and resetting the target value signal. And a monitoring circuit that outputs a reset signal to the control circuit when the measurement time reaches a predetermined time.

According to a second aspect of the present invention, in the first aspect of the present invention, the monitoring circuit detects a coincidence between the target value signal and the set value signal. A circuit, a target value setting circuit that outputs the target value signal to the control circuit and changes the value of the target value signal based on an output signal of the coincidence detection circuit; and And a timer circuit for outputting the reset signal when the time has reached, and resetting the measurement time in accordance with the output signal of the coincidence detection circuit.

In order to achieve the above object, according to a third aspect of the present invention, in the first and second aspects of the present invention, the control circuit monitors a periodic change of the target value signal from the monitoring circuit. Then, the abnormality of the monitoring circuit is determined.

In order to achieve the above object, a fourth aspect of the present invention is characterized in that in the first to third aspects of the present invention, the set value signal and the target value signal are 1-bit signals. Is what you do.

In order to achieve the above object, according to a fifth aspect of the present invention, in the fourth aspect of the present invention, the set value signal and the target value signal are transmitted and received via an input / output port of the control circuit. It is characterized by the following.

[0029]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the drawings. FIG. 1 is a configuration block diagram showing one embodiment of a control device according to the present invention.

In FIG. 1, reference numerals 5 and 100 denote the same reference numerals as in FIG. 5, 1a is a control circuit, 4a is a monitoring circuit,
04a is a reset signal, 105 is a set value signal, and 106 is a target value signal.

The data bus 100 is connected to the control circuit 1a via the switch circuit 5, the set value signal 105 from the control circuit 1 is connected to the input terminal of the monitoring circuit 4a, and the target value signal 106 from the monitoring circuit 4a is Connected to the input terminal of control circuit 1a.

The reset signal 104a output from the monitoring circuit 4a is connected to the reset terminal of the control circuit 1a and the control terminal of the switch circuit 5, respectively.

Here, the operation of the embodiment shown in FIG. 1 will be described. The control circuit 1a provides a routine for periodically reading the target value signal 106 during the program and outputting a set value signal 105 having the same value as the target value signal 106.

On the other hand, the monitoring circuit 4a measures the time by a timer circuit provided therein and outputs a reset signal 104a when a predetermined time is reached. When the value of the set value signal 105 matches the value of the target value signal 106, Resets the timer circuit in the monitoring circuit 4a and changes the value of the target value signal 106.

If the control circuit 1a is operating normally, the target value signal 106 is read periodically and the target value signal
The monitoring circuit 4a uses a signal having the same value as the value 6 as the set value signal 105.
Output to

The monitoring circuit 4a compares the set value signal 105 input from the control circuit 1a with the target value signal 106, and when the values match, resets the timer circuit in the monitoring circuit 4a and resets the target value signal. Change the value of 106.

For this reason, since the measurement time of the timer circuit in the monitoring circuit 4a does not reach a predetermined time, the reset signal 10
4a is not output.

If the control circuit 1a operates abnormally, the target value signal 106 is periodically read and the target value signal 106 is read.
The operation of outputting a signal of the same value as the set value signal 105 is not performed.

For this reason, the set value signal 105 does not match the target value signal 106, the timer circuit in the monitoring circuit 4a continues to operate and reaches a certain time, and the reset signal 10
4a is output.

When the reset signal 104a is output, the control circuit 1a is reset and its abnormal operation is forcibly terminated, the switch circuit 5 is turned off, and the data bus 10 is turned off.
The connection with 0 is cut off.

On the control circuit 1a side, if the monitoring circuit 4a operates normally, the control circuit 1a outputs the set value signal 10
5 after a certain period of time after changing the value of
However, if the monitoring circuit 4a operates abnormally, the target value signal 106 does not change.

That is, if there is no periodic change in the target value signal 106 of the monitoring circuit 4a, the control circuit 1a can determine that the monitoring circuit 4a is abnormal.

Here, the embodiment shown in FIG. 1 will be described in detail with reference to FIGS. 2, 3 and 4. FIG. 2 shows FIG.
3 is a block diagram showing a specific example of the monitoring circuit 4a, and FIGS. 3 and 4 are timing charts for explaining normal and abnormal operations of the monitoring circuit 4a.

In FIG. 2, 104a, 105 and 106
Are given the same reference numerals as in FIG. 1, 6 is a match detection circuit, 7
Is a target value setting circuit, and 8 is a timer circuit.

The set value signal 105 is connected to one input terminal of the match detection circuit 6, and the output of the match detection circuit 6 is connected to the control input terminal of the target value setting circuit 7 and the timer reset terminal of the timer circuit 8, respectively. .

The output of the target value setting circuit 7 is the target value signal 10
6 and connected to the other input terminal of the match detection circuit 6. Further, the reset signal 104a is output from the timer circuit 8.

3 and 4, (a) is the target value signal 106, (b) is the set value signal 105, (c) is the output signal of the coincidence detection circuit 6, and (d) is the measurement time of the timer circuit 8. , (E) are reset signals 104a.

For example, consider a case where the set value signal 105 and the target value signal 106 are "1 bit" signals and the control circuit 1a operates normally.

The target value setting circuit 7 (a) changes the target value signal 106 from "1" to "0" at the timing "A" in FIG.
Change to Since the control circuit 1a is operating normally, this change is read, and (b) the set value signal 105 is changed to "
It changes from "1" to "0" at the timing shown in "b".

At this time, since "1" is inputted to both input terminals of the coincidence detecting circuit 6, (c) the output of the coincidence detecting circuit 6 becomes "high level". Therefore, (d) the measurement time of the timer circuit 8 is reset at the rising edge of the output signal of the coincidence detection circuit 6 and (c) becomes "0" as shown by "c" in FIG.

Further, (d) the reset signal 104a is not output because the time measured by the timer circuit 8 does not reach the predetermined time.

Further, the target value setting circuit 7 is set to "d" in FIG.
After the lapse of the time shown by (a), the target value signal 106 is changed from "0" to "1" at the timing shown by "e" in FIG.

As described above, the control circuit 1a changes (b) the set value signal 105 from "0" to "1" at the timing indicated by "f" in FIG. 3, and (c) the output signal of the coincidence detection circuit 6. (D), the measurement time of the timer circuit 8 is reset.

That is, if the control circuit 1a is operating normally, (b) the set value signal 105 becomes (a) the target value signal 106
(E) the reset signal 104a is not output because the measured time of the timer circuit 8 continues to be reset and the measured time does not reach the fixed time.

On the other hand, consider the case where the control circuit 1a operates abnormally. If a failure occurs in the control circuit 1a at the point "A" in FIG. 4, the target value setting circuit 7 changes the (a) target value signal 106 from "0" at the timing "B" in FIG.
Even if it is changed to "1", (b) the set value signal 105 remains "0" because it cannot follow the change.

Therefore, (c) the output of the coincidence detection circuit 6 remains at "low level", and (d) the measurement time of the timer circuit 8 cannot be reset.

Therefore, as shown in FIG.
The measurement time of the timer circuit 8 increases to reach a certain time indicated by "D" in FIG. 4, and the reset signal 104a is output at a timing indicated by "E" in FIG.

When the reset signal 104a is output, the control circuit 1a is reset and its abnormal operation is forcibly terminated, the switch circuit 5 is turned off, and the data bus 10 is turned off.
The connection with 0 is cut off.

As described above, if there is no periodic change in the target value signal 106, the control circuit 1a can determine that the monitoring circuit 4a is abnormal.

As a result, the time is measured by the timer circuit 8 of the monitoring circuit 4a, and when a certain time is reached, the reset signal 104 is output.
a, and when the value of the set value signal 105 matches the value of the target value signal 106, the timer circuit 8 is reset and the value of the target value signal 106 is changed. The abnormal operation of the control circuit 1a can be detected and reset without using it.

Further, the target value signal 106 is
Of the monitoring circuit 4a itself can be confirmed by monitoring the periodical change of.

Further, since the timer reset operation of the monitoring circuit 4a is not a write operation to a specific address, there is no problem as in the conventional example.

In particular, since the control circuit 1a must make the value of the set value signal 105 follow the value of the target value signal 106, even if the control circuit 1a is fixed to a fixed state, the reset signal 104a Is output.

The set value signal 105 and the target value signal 1
When 06 is a "1 bit" signal, data can be easily exchanged with the monitoring circuit 4a by using the output port and the input port of the control circuit 1a.

This is particularly effective when the monitoring circuit 4a is used in the control circuit 1a having a small number of usable input / output ports.

Further, needless to say, the set value signal 105 and the target value signal 106 may be signals of "several bits" instead of "1 bit" signals.

In the description of FIGS. 3 and 4, the target value setting circuit 7
Changes the value of the target value signal 106 after a lapse of a predetermined time. The timing of the change may be arbitrary. For example, the value of the target value signal 106 is changed at the rising edge of the output signal of the coincidence detection circuit 6. No problem.

Although the output of the reset signal 104a is illustrated as a negative logic output in the description of FIG. 4, it may be a positive logic output.

[0069]

As is apparent from the above description,
According to the present invention, the following effects can be obtained. The timer circuit of the monitoring circuit measures the time and outputs a reset signal when a certain time is reached. When the set value signal and the target value signal match, the timer circuit is reset and the value of the target value signal is reset. By making the change, and by monitoring the change of the target value signal periodically on the control circuit side, it is possible to realize a control device having a simple circuit configuration and capable of confirming an abnormal operation of the monitor circuit itself.

[Brief description of the drawings]

FIG. 1 is a configuration block diagram showing an embodiment of a control device according to the present invention.

FIG. 2 is a configuration block diagram illustrating a specific example of a monitoring circuit 4a.

FIG. 3 is a timing chart for explaining the normal operation of the monitoring circuit 4a.

FIG. 4 is a timing chart illustrating an operation of the monitoring circuit 4a when an abnormality occurs.

FIG. 5 is a configuration block diagram illustrating a conventional example of a conventional control device.

[Explanation of symbols]

 1, 1a control circuit 2 address decoder circuit 3 AND circuit 4, 4a monitoring circuit 5 switch circuit 6 match detection circuit 7 target value setting circuit 8 timer circuit 100 data bus 101 address signal 102 write enable signal 103 chip select signal 104, 104a Reset signal 105 Set value signal 106 Target value signal

Claims (5)

[Claims] 1. A control device for monitoring an abnormal operation of a control circuit, comprising: a control circuit for reading a target value signal and outputting a set value signal having the same value as the target value signal; and outputting the target value signal to the control circuit. If the value of the target value signal and the value of the set value signal match, reset the measurement time and change the value of the target value signal, and if the measurement time reaches a certain time, the control circuit And a monitoring circuit for outputting a reset signal to the control device. 2. A match detection circuit for detecting a match between the target value signal and the set value signal, wherein the monitor circuit outputs the target value signal to the control circuit and an output signal of the match detection circuit. A target value setting circuit that changes the value of the target value signal based on the following formula: a reset signal is output when the measurement time reaches a predetermined time by measuring time, and the measurement time is calculated based on an output signal of the coincidence detection circuit. 2. The control device according to claim 1, further comprising a timer circuit for resetting the control signal. 3. The control circuit according to claim 1, wherein said control circuit monitors a periodic change of said target value signal from said monitoring circuit to determine an abnormality of said monitoring circuit. 2. The control device according to 2. 4. The control device according to claim 1, wherein said set value signal and said target value signal are 1-bit signals. 5. The control device according to claim 4, wherein said set value signal and said target value signal are transmitted and received via an input / output port of said control circuit.