JPH1168043A - ESD protection circuit - Google Patents

Abstract

[PROBLEMS] To provide an ESD protection circuit having a high protection effect against electrostatic breakdown regardless of an application mode of electrostatic discharge. A diffusion layer region serving as a drain has at least two diffusion regions.
And at least one of the divided diffusion layer regions is connected to a substrate potential in a transistor of an output buffer formed in a well region of the same type as the diffusion layer region. The above object is achieved by forming at least one diffusion layer region of a different type from the region in the well region.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD The present invention relates to an electrostatic discharge (ES)
The present invention relates to an ESD protection circuit for preventing an internal circuit of a semiconductor device from being damaged by D (Electro Static Discharge).

[0002]

2. Description of the Related Art In a semiconductor device, for example, a part of an internal circuit may be deteriorated or destroyed by the above-described electrostatic discharge. Here, the electrostatic discharge means that, for example, a charged human body or object discharges the static electricity through an external terminal of a package of the semiconductor device, or the semiconductor device itself is charged by assembling or transporting, The static electricity is discharged through a human body or an object.

Therefore, various techniques have been conventionally developed to protect the internal circuit of a semiconductor device from the above-described damage due to electrostatic discharge (hereinafter, referred to as electrostatic breakdown). Are provided. As one of such ESD protection circuits,
As a technique for protecting a transistor constituting an output buffer from electrostatic breakdown, for example, the following technique has been conventionally used.

FIGS. 2 (a), 2 (b) and 2 (c) are layout plan conceptual diagrams of an example of a conventional ESD protection circuit, respectively.
It is a sectional conceptual diagram and an equivalent circuit diagram. FIG. 1 shows an N-type MOS transistor (hereinafter, referred to as NMO) constituting an output buffer.
An output signal from an internal circuit (not shown) is input to the gate, the source is connected to the ground, and the drain is connected to the bonding pad 36.

In the illustrated example, the NMOS 12a has a P⁺Diffusion layer area
P-type semiconductor substrate connected to ground via region 34
(Hereinafter referred to as a P substrate)
N ⁺N as diffusion layer region 18 and drain⁺diffusion
Layer region 22 and P group between source and drain
It has a gate electrode 26 formed on the plate 16. Also,
A plurality of source contacts 30 are formed on the source, and
The rain has a predetermined distance L from the gate electrode 26._gcApart
A number of drain contacts 32 are formed.

As shown in FIG. 1, in a conventional output buffer, the distance L _gc between the drain contact 32 and the gate electrode 26 is often increased, for example, to about 5 μm. Thereby, the series resistance 3 is substantially reduced between the bonding pad 36 and the drain of the NMOS 12a.
8 is inserted, the energy of the pulse due to the electrostatic discharge is limited, and the local concentration of energy is also prevented.
a is prevented from breaking.

By the way, in recent semiconductor devices, a salicide technique has been used as miniaturization progresses. In the salicide technique, the surface of a diffusion layer region serving as a source or a drain is coated with a high-melting-point metal film, which is converted into silicide (a compound of silicon and a high-melting-point metal) to reduce the resistance value of the diffusion layer region. Technology. As the gate electrode, a silicide gate, a polycide structure in which silicide is overlapped with polysilicon, or the like is used.

Therefore, in the semiconductor device using the salicide technique, even if the distance L _gc between the drain contact and the gate electrode is increased, the resistance value of the series resistance inserted between the bonding pad and the drain is extremely large. It will be small. However, it is practically impossible to increase the distance L _gc until the resistance to electrostatic discharge is sufficiently ensured. Therefore, in a semiconductor device using salicide technology, for example, the following ESD protection circuit is used.

FIGS. 3 (a), 3 (b) and 3 (c) are a schematic plan view, a schematic sectional view and an equivalent circuit diagram of another example of the conventional ESD protection circuit, respectively. FIG. 1 shows an example of an NMOS 12b constituting an output buffer of a semiconductor device using salicide technology. As in the case of FIG. 2, an output signal from an internal circuit (not shown) is input to its gate. The source is connected to the ground, and the drain is connected to the bonding pad 36.

The NMOS 12b in the illustrated example is divided into an N ⁺ diffusion layer region 18 serving as a source formed in a P substrate 16 connected to the ground via a P ⁺ diffusion layer region 34, and is divided into two parts at a predetermined interval. It has N ⁺ diffusion layer regions 22 and 24 to be drains formed in n well region 20 apart from each other, and a gate electrode 26 formed on P substrate 16 between the source and the drain. A plurality of source contacts 30 are formed on the source, and a plurality of drain contacts 32 are formed on the drain.

As shown in FIG. 1, salicide technology is used.
In a semiconductor device such as this, the N
⁺Divide the diffusion layer region into two, and divide these two
N ⁺An n-well having a high resistance value is provided between the diffusion layer regions 22 and 24.
Forming the bonding region by forming the bonding region 20
As shown in FIG. 2 between the drain 36 and the drain of the NMOS 12b.
A series resistor 38 having substantially the same resistance value as the series resistor 38
2 and the same as the ESD protection circuit shown in FIG.
The same protection effect can be obtained.

By the way, in the actual layout of the semiconductor device, the N ⁺ diffusion layer region 24 serving as the drain connected to the bonding pad 36 is, for example, shown in FIGS. 4A and 4B and FIGS. As shown in the layout plan conceptual diagram and the cross-sectional conceptual diagram corresponding to (b), the two NMOSs 12c and 14c often share the layout. In this case, in the semiconductor device using the salicide technique, the N ⁺ diffusion layer region 24 serving as the drain is completely formed in the n-well region 20.

However, as shown in FIG.
And a diode 42 constituted by the n-well region 20
For example, as shown in FIG. 2, there is a characteristic that the forward current characteristic when compared under the same condition is worse than that of the diode composed of the P substrate 16 and the N ⁺ diffusion layer region 22. On the other hand, electrostatic discharge includes a positive application mode in which a positive pulse is applied using V _ss as a reference potential and a negative application mode in which a negative pulse is applied.

Therefore, as shown in FIG. 4, a part of the N ⁺ diffusion layer region 24 serving as a drain is completely
If the device structure is formed inside,
In the ESD protection circuit in which the protection effect is obtained by using the forward current characteristics of the diode as in the negative application mode of the electrostatic discharge described above, there is a problem that the protection effect is reduced. Although the conventional problem has been described by exemplifying the case of the NMOS, the same applies to the case of the P-type MOS transistor.

[0015]

SUMMARY OF THE INVENTION An object of the present invention is to solve the problems of the prior art and to divide a diffusion layer region serving as a drain into at least two parts, such as a semiconductor device using salicide technology. At least one of the divided diffusion layer regions is formed in a transistor of an output buffer formed in a well region of the same type as the diffusion layer region, irrespective of an electrostatic discharge application mode. An object of the present invention is to provide an ESD protection circuit having a high protection effect against electric breakdown.

[0016]

In order to achieve the above object, according to the present invention, a diffusion layer region serving as a drain is divided into at least two, and at least one of the divided diffusion layer regions is In the transistor of the output buffer formed in the well region of the same type as the diffusion layer region, at least one diffusion layer region of a type different from the well region and connected to the substrate potential is provided in the well region. It is intended to provide an ESD protection circuit characterized by being formed.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an ESD protection circuit according to the present invention will be described in detail with reference to a preferred embodiment shown in the accompanying drawings.

FIGS. 1A and 1B are a conceptual plan view and a schematic sectional view, respectively, of an embodiment of the ESD protection circuit of the present invention. FIGS. 4A and 4B respectively show examples corresponding to FIGS. 4A and 4B so as to be easily compared with the prior art, and the ESD protection circuit of the present invention is applied. N-type MO constituting output buffer 10
1 shows an example of S transistors (hereinafter, referred to as NMOS) 12 and 14.

That is, FIG. 1 shows two NMOSs 12,
14, one drain connected to the bonding pad is shared.
Is divided into two, an N ⁺ diffusion layer region 18 serving as a source formed in a P-type semiconductor substrate (hereinafter, referred to as a P substrate) 16 and formed in an n-well region 20 at a predetermined interval. It has N ⁺ diffusion layer regions 22 and 24 serving as drains, and a gate electrode 26 formed on P substrate 16 between the source and the drain.

The illustrated ESD protection circuit has a P ⁺ diffusion layer region 28 formed in the n-well region 20 and connected to ground (substrate potential). Also, each N
A plurality of source contacts 30 are formed in the N ⁺ diffusion layer regions 18 serving as the sources of the MOSs 12 and 14, and a plurality of drain contacts 32 are formed in the N ⁺ diffusion layer regions 24 serving as the drains. The P substrate 16 is connected to ground (substrate potential) via a P ⁺ diffusion layer region 34.

As shown in FIG. 1, in the ESD protection circuit of the present invention, the P ⁺ diffusion layer region 28 and the n well region 20
By this, the diode 40 having a good forward current characteristic
Is formed. Therefore, in the illustrated example of the ESD protection circuit,
Even in the case of the negative application mode of electrostatic discharge, the P substrate 1
Since the current can be supplied not only from the diode 42 formed by the 6 and the n-well region 20 but also from the diode 40, the protection effect against the electrostatic breakdown can be improved.

The ESD protection circuit according to the present invention is also effective in preventing latch-up. That is, the diode 42
Is turned on, and a current flows from the P substrate 16 side to the N ⁺ diffusion layer region 24 serving as a drain through the n well region 20, the current can be supplied also from the diode 40. Therefore, the substrate current (voltage drop in the substrate) can be reduced and stabilized, and the parasitic bipolar transistor that causes latch-up can be prevented from being turned on.

In the illustrated example, the diffusion layer region serving as the drain is divided into two. However, the present invention is not limited to this. For example, the diffusion layer region serving as the drain may be divided into three or more. Good. That is, the present invention is applicable to a structure in which a diffusion layer region serving as a drain is divided into at least two,
A series resistor having substantially the same resistance value as the series resistor 38 shown in FIG. 2 is formed by the well region of the same type as the diffusion layer region formed between the divided diffusion layer regions.

In the illustrated example, each NMOS 12,
In 14, but each is provided with a P ⁺ diffusion layer regions 28 between the N ⁺ diffusion layer regions 22 and 24 serving as the divided drain into two, the present invention is not limited thereto, the P ⁺ diffusion layer regions 28 may be at least one in the n-well region 20, and its arrangement is not particularly limited. In the above embodiment, the case of the NMOS has been described as an example.
It is also applicable to the case of a type MOS transistor (hereinafter, referred to as a PMOS).

Here, in FIG. 1, the drawing is easy to see.
In order to perform N⁺Diffusion layer area
The series resistance formed between the regions 22 and 24 is not described.
But N⁺P between the diffusion layer regions 22 and 24⁺Diffusion layer area
When 28 is arranged, N⁺The voltage between the diffusion layer regions 22 and 24
The spiritual path is P⁺I will go under the diffusion layer region 28
And the resistance of the series resistor (not shown) increases.
N ⁺Distance between diffusion layer regions 22 and 24
Can be shortened.

When the present invention is applied to a PMOS,
The P ⁺ diffusion layer region serving as a drain is divided into at least two, and at least one of the divided P ⁺ diffusion layer regions is formed.
One is formed in a p-well region, and at least one N ⁺ diffusion layer region connected to a power supply (substrate potential) is formed in the p-well region. Also, the present invention provides
It may be applied only to the OS, may be applied only to the PMOS, or may be applied to both the NMOS and the PMOS.

In the embodiment, an n-well region 20 is formed in the p-substrate 16, and an n-well region 20 is formed in the n-well region 20.
N ⁺ diffusion layer region 24 serving as drains of MOSs 12 and 14
However, the present invention is not limited to this. A p-well region is further formed in the n-well region 20 and the p-well region is formed.
The present invention is also applicable to a multi-well structure such as forming a P ⁺ diffusion layer region serving as a drain of a PMOS in a well region. Further, the present invention can be applied to an N-type semiconductor substrate in exactly the same manner.

The present invention can be applied, for example, as an ESD protection circuit for an output buffer of a semiconductor device using salicide technology. However, the present invention is not limited to this, and can be applied to a semiconductor device not using salicide technology. Also, an output buffer in which a diffusion layer region serving as a drain is divided into at least two, and at least one of the divided diffusion layer regions is formed in a well region of the same type as the diffusion layer region. Of transistors.

Although the ESD protection circuit according to the present invention has been described in detail above, the present invention is not limited to the above embodiment, and various improvements and modifications may be made without departing from the gist of the present invention. Of course.

[0030]

As described in detail above, the ES of the present invention
In the D protection circuit, a diffusion layer region serving as a drain is divided into at least two, and at least one of the divided diffusion layer regions is formed in a well region of the same type as the diffusion layer region. In the transistor of the output buffer, at least one diffusion layer region connected to the substrate potential and having a different type from the well region is formed in the well region. According to the ESD protection circuit of the present invention, a new diode is formed by the well region and a diffusion layer region of a different type from the well region formed in the well region, and a current is supplied by the new diode. Therefore, a high effect of protection against electrostatic breakdown can be obtained irrespective of the application mode of the electrostatic discharge, and a high effect can also be obtained in preventing latch-up.

[Brief description of the drawings]

1 (a) and 1 (b) show the ESD of the present invention, respectively.
3A and 3B are a layout plan conceptual diagram and a cross-sectional conceptual diagram of an embodiment of a protection circuit.

FIGS. 2A, 2B, and 2C are a schematic plan view, a schematic sectional view, and an equivalent circuit diagram of an example of a conventional ESD protection circuit, respectively.

FIGS. 3A, 3B, and 3C are a schematic plan view, a schematic sectional view, and an equivalent circuit diagram, respectively, of another example of the conventional ESD protection circuit.

FIGS. 4A and 4B are a schematic plan view and a schematic sectional view, respectively, of another example of the conventional ESD protection circuit.

[Explanation of symbols]

10 Output buffer 12, 12a, 12b, 12c, 14, 14c N-type M
OS transistor 16 P-type semiconductor substrate 18, 22, 24 N ⁺ diffusion layer region 20 n-well region 26 gate electrode 28, 34 P ⁺ diffusion layer region 30 source contact 32 drain contact 36 bonding pad 38 series resistance 40, 42 diode

Claims (1)

[Claims] 1. A diffusion layer region serving as a drain has at least two diffusion regions.
At least one of the divided diffusion layer regions is connected to a substrate potential in a transistor of an output buffer formed in a well region of the same type as the diffusion layer region; An ESD protection circuit, wherein at least one diffusion layer region of a different type from the well region is formed in the well region.