JPH1168734A - Interleave device and de-interleave device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To encrypt data by effectively utilizing the interleave device with a simple circuit configuration. SOLUTION: Upon the receipt of input data 100, a CPU 2T generates a synchronization pattern generating instruction signal 22 and gives it to a synchronization pattern generating circuit 5 and generates a synchronization pattern 51 for transmission based on a synchronization pattern generating instruction signal 22 and transmits it. The CPU 2T gives interleave depth data corresponding to a content configuration of the synchronization operational amplifier based on a table 200 to a register circuit 3 as interleave depth data 21 and gives interleave depth data 31 to a read control circuit 13T. Upon the receipt of the input data 100 by a buffer memory circuit 11T, a write control circuit 12T writes the input data 100 in the order of input to the buffer memory circuit 11T. The read control circuit 13T decides a read pattern based on the interleave depth data 31 received from the register circuit 3T and gives a read address 131 required for the read to the buffer memory circuit 11T, from which the data are read.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interleave device and a deinterleave device, and for example, to a device using an interleave circuit and a deinterleave circuit in a communication system.

[0002]

2. Description of the Related Art In a digital radio communication device for a digital car telephone, since data errors occur in a burst, error data is dispersed by an interleave circuit. The reason for dispersing the error data is to enhance the error correction capability of the error correction circuit for the error data. The interleaving means that the transmission data is once stored in a buffer according to a certain rule and then read out in a different order.

FIG. 2 is a diagram for explaining an example of an interleaving method. In FIG. 2, information bits Y1 to Y48
In writing to the buffer circuit for interleaving, the horizontal method (row direction) Y1, Y2, Y3, Y4, Y5, Y6,
.., Y9 to Y16, Y17 to Y24, Y25 to Y32, Y33 to Y40, Y41 to Y48, and the interleave depth is set to 6. Then, the interleave reading is performed in the depth direction (vertical direction, column direction) by Y1, Y9, Y17, Y25, Y33, Y41,.
··· Read in order from Y2 to Y42, Y3 to Y43, Y4 to Y44, Y5 to Y45, Y6 to Y46, Y7 to Y47, and Y8 to Y48 for interleaving.

There is also a technique for randomizing transmission data in order to enhance confidentiality of communication. As a conventional concealment method, a scramble circuit using a PN (Pseudo random Number) code is used.

FIG. 3 is a diagram for explaining a method of generating a scramble pattern for randomizing transmission data. In FIG. 3, the scramble pattern generation circuit includes shift registers S0 to S8 and shift register S0.
An exclusive OR circuit EOR for performing an exclusive OR operation on the output signal of the shift register S4 and the output signal of the shift register S4 and updating the signal of the shift register S8. First, set some initial signals in the shift registers S0 to S8,
Thereafter, by updating the value of the shift register S8 with the exclusive OR result each time shifting is performed by one clock,
The values of the signals stored in the shift registers S0 to S8 change to random values, and the randomized values can be used to extract the scramble pattern signal SKP from the shift register S0 and to randomize the transmission data. .

[0006]

Generally, a wireless communication device must be provided with a concealment function because it is more easily intercepted than a wire communication device. In particular, in wireless communication requiring a concealment function, it is desired to prevent a leakage of information by combining a plurality of concealment functions.

[0007] The concealment function can be realized in various forms. For example, when realized by a hardware circuit,
A dedicated processing circuit (for example, a logic circuit or the like) is required, resulting in a problem that the cost and the mounting area increase. Also, when concealment is performed by software, the processing time is likely to be longer than that of a hardware processing circuit, depending on the level of processing capacity, and thus transmission delay tends to increase.

In view of the above, there is a need for an interleave device and a deinterleave device capable of concealing data by effectively using an interleave circuit and a deinterleave circuit with a simple circuit configuration.

[0009]

Therefore, according to the present invention, there is provided an interleave apparatus including an interleave buffer memory means for storing interleaved input data having a predetermined data length and transmitting interleaved result data.
In order to change the interleaving depth each time interleaving is performed on input data of one predetermined data length,
Updating the interleave depth in the interleave buffer memory means, generating a read address based on the updated interleave depth, and providing the interleave depth update means to the interleave buffer memory means; and indicating the updated interleave depth. Interleave depth data transmitting means for transmitting data.

According to the present invention, a deinterleave device that receives transmission data from an interleave device and performs deinterleave stores the interleave result transmission data and performs deinterleave by being given a read address. Deinterleaving buffer memory means for outputting data of the deinterleaving result, receiving data indicating the interleaving depth, and storing the data stored in the deinterleaving buffer memory means based on the data indicating the interleaving depth. Read address generating means for generating a read address for reading and supplying the read address to the deinterleave buffer memory means.

By employing such a configuration, interleaving of input data is performed with a very simple device configuration, and at the same time, the interleaving depth is updated for each predetermined length of data. it can. The deinterleave device receives the data indicating the interleave depth, recognizes the depth for deinterleave, and stores the data stored in the deinterleave buffer memory means based on the deinterleave depth. Can be decoded and read out while deinterleaving, so that the configuration of deinterleaving can be very simplified.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, a preferred embodiment of the present invention will be described with reference to the drawings. In this embodiment, the depth for determining the interleave read pattern is made variable and the transmission data is randomized. In addition, the readout pattern is set in the depth setting register for each communication so that the concealment function is enhanced.

More specifically, conventionally, an interleave circuit aims at dispersing error data as described above with a fixed interleave depth.
According to the present invention, by making the interleaving depth variable, it becomes possible to use the error data in a confidential function as well as in a distributed manner. This minimizes the addition of hardware circuits and minimizes the processing delay for transmission.

FIG. 1 shows an interleave device 70 for concealing data by an interleave circuit according to an embodiment of the present invention.
FIG. 3 is a functional configuration diagram of FIG. In FIG. 1, the interleave device 70 basically performs an interleave on the input data 100 and simultaneously performs data concealment on the input data 100 to output a transmission data 110, and an interleave circuit 1T for the interleave in the interleave circuit 1T. The interleave depth setting register circuit 3T that sets the depth data 31 and gives the interleave depth setting register circuit 3T and the interleave depth data 21 that is given to the interleave depth setting register circuit 3T and generates the interleave depth setting register circuit 3T Circuit 2T to be supplied to the CPU, and a synchronous pattern generating circuit 5 that generates a synchronous pattern 51 based on the synchronous pattern generation command signal 22 from the CPU circuit 2T and outputs it as a transmission signal.
It is composed of

The interleave circuit 1T basically stores the input data 100 and interleaves the input data 100.
An interleave buffer memory circuit 11T as temporary storage means for performing data concealment on
A write control circuit 12T that supplies a write address 121 for writing 100 to the interleave buffer memory circuit 11T, and data from the interleave buffer memory circuit 11T based on the interleave depth data 31 supplied from the interleave depth setting register circuit 3T. A read control circuit 13T for determining a read pattern and providing a read address 131 to the interleave buffer memory circuit 11T.

The CPU circuit 2T generates an interleave depth data 21 and a synchronous pattern generation command signal 22 in order to generate an interleave depth table 200 in which the correspondence between the synchronous pattern and the interleave depth data is stored in a table 200.
It has 200. FIG. 4 is an explanatory diagram of the interleave depth table 200.

In FIG. 4, the synchronization pattern is
For example, a public digital communication system (RCR-STD-39A, a specification standardized by the Radio System Development Center)
In the case of ()), it is determined by the configuration of the slot numbers 0 to 3 and the function channel. The function channel includes a control channel, a synchronization burst, and a communication channel. The synchronization pattern is determined by these settings. Different interleave depth data may be set in the table 200 in accordance with the setting contents of the synchronization pattern, and may be given to the interleave depth setting register circuit 3 as interleave depth data 21.

Next, the operation of the interleave device 70 of FIG. 1 will be described. First, the input data 100 to be transmitted before interleaving and before concealment are input to the interleave circuit 1T and
When input to the CPU 2T, the CPU 2T sets a slot number and a function channel, generates a synchronization pattern generation command signal 22, and gives it to the synchronization pattern generation circuit 5. by this,
The synchronization pattern generation circuit 5 outputs a synchronization pattern generation command signal.
Based on 22, a synchronization pattern 51 for transmission is generated and transmitted. As the synchronization pattern 51, it is preferable to output a pattern having different contents for each communication.

After the transmission of the synchronization pattern 51, the CPU 2T converts the interleaving depth data corresponding to the content configuration of the synchronization pattern into the interleaving depth data 21 according to the interleaving depth table 200 as an interleave depth setting register circuit. Give to 3. The interleave depth setting register circuit 3T holds the interleave depth data 21 unless updated, and
31 is given to the read control circuit 13T.

On the other hand, when the input data 100 is given to the interleave buffer memory circuit 11T, the write control circuit 12T writes the input data 100 to the buffer memory circuit in the input order. That is, writing is sequentially performed from Y1 to Y48 as shown in FIG. And Y1
When the data is written from Y to Y48, the read control circuit 13T
Determines a read pattern based on the interleave depth data 31 given from the interleave depth setting register circuit 3T, and gives a read address 131 necessary for reading to the interleave buffer memory circuit 11T.

That is, when the read control circuit 13T is given, for example, data of a depth of 8 as the interleave depth data 31 from the interleave depth setting register circuit 3T, as shown in FIG. Y7, Y13, Y19,
Y25, Y31, Y37, Y43, ..., from Y2 to Y44, from Y3
By reading in the order of Y45, Y4 to Y46, Y5 to Y47, and Y6 to Y48, the data is read out in a completely random order from the input order, and is output as transmission data 110.

When the interleave depth data 31 is given as the interleave depth data 31 from the interleave depth setting register circuit 3T, for example, as shown in FIG. , Y8, Y15
, Y22, Y29, Y36, Y43, ..., from Y2 to Y44, Y3
To Y45, Y4 to Y46, Y5 to Y47, Y6 to Y48
6 can be read out in a random order different from the interleave depth 8 in FIG. 6 and completely different from the input order, and can be output as transmission data 110.

The synchronization pattern 51 transmitted as described above
And the transmission data 110 are the deinterleave device on the receiving side.
It is provided to 70 to perform deinterleaving and decryption for data concealment.

FIG. 5 is a functional block diagram of a deinterleave device 80 used on the receiving side. In FIG. 5, the deinterleave device 80 basically includes the following elements. That is, the synchronous pattern detecting circuit 4 for receiving the synchronous pattern from the transmitting side and supplying the synchronous pattern detection signal 41 to the CPU circuit 2R and the synchronous pattern detecting circuit 4 shown in FIG. 4 as in the CPU circuit 2T of the interleave device 70 in FIG. Deinterleave depth table like interleave depth table
It is provided as 200A, reads the synchronization pattern detection signal 41, selects the deinterleave depth data corresponding to the detected synchronization pattern from the deinterleave depth table 200A, and deinterleaves the deinterleave depth data 21A. A CPU circuit 2R to be provided to the depth setting register circuit 3R;
A deinterleave depth setting register circuit 3R that sets the deinterleave depth data 31A in the deinterleave circuit 1R and gives it to the deinterleave circuit 1R;
0 is deinterleaved based on the deinterleave depth data 31A, and decryption for concealment is performed.
This is a deinterleave circuit 1R that outputs 0.

The deinterleave circuit 1R is basically composed of the following elements. That is, the received data 11
A deinterleave buffer memory circuit 11R as temporary storage means for storing deinterleaving and data decoding for the received data 110;
Control circuit that supplies a write address 121 for writing data to the deinterleave buffer memory circuit 11R.
The data read pattern is determined from the deinterleave buffer memory circuit 11R based on 12R and the deinterleave depth data 31A supplied from the deinterleave depth setting register circuit 3R, and the read address 131 is transferred to the deinterleave buffer memory circuit 11R. The read control circuit 13R is provided.

In order to generate the deinterleave depth data 21A, the CPU circuit 2R stores a deinterleave depth table 200A indicating the correspondence between the synchronization pattern and the deinterleave depth data in the interleave device on the transmission side. Figure 4 of 70
In the same way as the interleave depth table 200 shown in FIG.

Next, the operation of the deinterleave device 80 of FIG. 5 will be described. In FIG. 5, a deinterleave device 80
First, the synchronization pattern detecting circuit 4 detects a different synchronization pattern 51 for each communication from the interleaving device 70 on the transmission side. When the synchronization pattern 51 is detected, the synchronization pattern detection signal 41 is sent from the synchronization pattern detection circuit 4 to the CPU circuit 2R.
Given to. The CPU circuit 2R decodes the content of the synchronization pattern from the given synchronization pattern detection signal 41. That is, the setting contents such as the slot number, the control channel, the synchronization burst, and the communication channel are read, and the corresponding deinterleave depth data 21A is selected and output from the deinterleave depth table 200A to set the deinterleave depth. Give to register circuit 3R. The deinterleave depth setting register circuit 3R supplies the set data with the deinterleave depth data 31A to the read control circuit 13R of the deinterleave circuit 1R.

On the other hand, when the received data 110 is given to the deinterleave buffer memory circuit 11R, the write control circuit 12R writes the received data 110 to the deinterleave buffer memory circuit 11R in the input order. That is, for example, in the case of FIG. 2 described above, Y1, Y9, Y17, Y25
, Y33, Y41, Y2, Y10, Y18, Y26, Y34, Y42, Y
3, Y11, Y19, Y27, Y35, Y43, Y4, Y12, Y20, Y
28, Y36, Y44, Y5, Y13, Y21, Y29, Y37, Y45
, Y6, Y14, Y22, Y30, Y38, Y46, Y7, Y15, Y23
, Y31, Y39, Y47, Y8, Y16, Y24, Y32, Y40, Y
, And are written to the deinterleave buffer memory circuit 11R.

In this way, the received data is changed from Y1 to Y48
When the data is written to the memory, the read control circuit 13R determines the read pattern based on the deinterleave depth data 31A given from the deinterleave depth setting register circuit 3R, and stores the read address 131 necessary for reading in the deinterleave buffer memory circuit. Give to 11R.

The deinterleave buffer memory circuit 11R, for example, in FIG. 2, determines that the depth of the deinterleave is 6, so that it reads out every sixth received data from Y1, and , Y2, Y3,
Read Y4, Y5, Y6, Y7, Y8, then receive Y9
Read the received data every 6th from Y9, Y1
0, Y11, Y12, Y13, Y14, Y15, Y16 are read, and then every sixth received data is read from the received Y17, and Y17, Y18, Y19, Y20, Y21, Y2 are read out.
2, Y23, Y24, and then every sixth received data from the received Y25, and read out Y25, Y2.
6, Y27, Y28, Y29, Y30, Y31, Y32 are read out, and then every sixth received data is read out from the received Y33, and Y33, Y34, Y35, Y36, Y37, Y3 are read out.
8, Y39, Y40, and finally the received Y41
And read out the received data every sixth from Y41,
Read out Y42, Y43, Y44, Y45, Y46, Y47, Y48.

In this way, the received data is changed from Y1 to Y8
To Y9 to Y16, Y17 to Y24, Y25 to Y32,
The decoded data 100 can be output by reading from Y33 to Y40 in the order of Y41 to Y48. As a result, the same data as the input data before interleaving on the transmission side can be obtained as decoded data 100.

In the case of the interleave of the depth 8 described in FIG. 6 and the interleave of the depth 7 described in FIG. 7, the interleave depth can be recognized on the receiving side. Decryption can be performed.
In the case of the communication system of the present embodiment, the content of the synchronization pattern changes for each communication, that is, the transmission is performed with the interleaving depth changed, so that the receiving side can recognize the information indicating the interleaving depth, Deinterleaving and decoding can be performed by adapting the deinterleaving depth corresponding to the interleaving depth.

By providing the above-described interleave device and deinterleave device, it becomes possible to simultaneously perform interleave on data and concealment of data with a very simple circuit configuration. In addition, since it can be composed of a memory circuit, a CPU circuit, a register, a logic control circuit, and the like, it is easy to integrate the semiconductor,
The size can be reduced. Increasing the depth variable range increases the concealment effect.

In the above embodiment, the synchronization pattern and the data are transmitted separately, but as another configuration, data (for example, pattern data) indicating the depth of interleaving is inserted into the transmission signal format. The data representing the interleaving depth is transmitted without interleaving, and the data representing the interleaving depth inserted on the receiving side is transmitted to the CPU circuit as shown by the dotted line 300 in FIG.
If the data is extracted by 2R and the extracted data 21 of the interleave depth is supplied to the deinterleave depth setting register circuit 3R, the above-described embodiment can be performed without the synchronization pattern generation circuit 5 and the synchronization pattern detection circuit 4. And the secrecy of data can be performed at the same time. When data indicating the interleave depth is to be inserted, the data may be replaced with an encryption word and transmitted, and the reception side may convert the data into data indicating the deinterleave depth.

In a communication system including an interleave device and a deinterleave device, when transmitting a password and transmitting information after being authenticated on the receiving side, when transmitting a password, the above-described interleaving depth is used. May be sent together, and the information may be sent with interleaving and concealment.

[0036]

As described above, according to the present invention, the interleaving apparatus changes the interleaving depth every time interleaving is performed for one input data having a predetermined data length. Updating the interleaving depth, generating a read address based on the updated interleaving depth, transmitting data representing the updated interleaving depth, and receiving the data representing the interleaving depth. Then, a read address for reading data stored in the deinterleave buffer memory means is generated based on the data indicating the interleave depth, deinterleave is performed, and data of a deinterleave result is output. A simple circuit configuration makes effective use of the interleave circuit So that confidentiality can also be carried out for the other.

[Brief description of the drawings]

FIG. 1 is a functional configuration diagram of an interleave device that conceals data by an interleave circuit according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating an example of a conventional interleaving method.

FIG. 3 is a diagram for explaining a method of generating a scramble pattern for randomizing transmission data in the related art.

FIG. 4 is an explanatory diagram of an interleave depth table used inside the CPU of the interleave circuit of the present embodiment.

FIG. 5 is a functional configuration diagram of a deinterleaving device that receives a transmission signal and a synchronization signal output from the interleaving device of the present embodiment and performs deinterleaving.

FIG. 6 is a diagram showing the order of data read from the interleave buffer memory circuit when the interleave depth is set to 8 in the interleave device of the present embodiment.

FIG. 7 is a diagram showing the order of data read from the interleave buffer memory circuit when the interleave depth is 7 in the interleave device of the present embodiment.

[Explanation of symbols]

 1T interleave circuit 1R deinterleave circuit 2T, 2R CPU circuit 3T, 3R interleave depth setting register circuit 11T interleave buffer memory circuit 11R deinterleave buffer memory circuit 200 Interleave depth table

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁶ Identification code FI // H04Q 7/38 H04B 7/26 109R

Claims (5)

[Claims] 1. An interleave device including interleave buffer memory means for storing interleaved input data of a predetermined data length and transmitting data of an interleave result, the device comprising: one input data having a predetermined data length; In order to change the interleave depth every time interleaving is performed, the interleave depth in the interleave buffer memory means is updated, and a read address is generated based on the updated interleave depth. An interleave apparatus comprising: an interleave depth updating unit that supplies the interleave depth; and an interleave depth data transmission unit that transmits data indicating the updated interleave depth. 2. An interleave device including interleave buffer memory means for storing interleaved input data having a predetermined data length and transmitting data of an interleave result, the device comprising: one input data having a predetermined data length; In order to change the interleave depth every time interleaving is performed, the interleave depth in the interleave buffer memory means is updated, and a read address is generated based on the updated interleave depth. Means for updating the interleave depth given to the interleaving depth table, an interleaving depth table indicating the relationship between the data indicating the interleaving depth and the contents of the synchronization pattern data or the encryption word data, and using the interleaving depth table, Interleaved An interleave depth data transmitting means for converting data representing the depth of the data into synchronous pattern data or encrypted word data and transmitting the data. 3. The interleaving apparatus according to claim 2, wherein the synchronization pattern data is formed by a combination of two or more of slot information, control channel information, synchronization burst information, communication channel information, and the like. An interleaving device characterized by the following. 4. A deinterleaving device for receiving transmission data from the interleaving device according to claim 1 and performing deinterleaving, wherein the device stores transmission data of the interleaving result and gives a read address. Deinterleave buffer memory means for performing deinterleaving by outputting the data of a deinterleave result, receiving data representing the depth of the interleave, and deinterleaving buffer memory based on the data representing the depth of the interleave. A deinterleave device for generating the read address for reading the data stored in the means, and providing the read address to the deinterleave buffer memory means. 5. A deinterleave device for receiving transmission data from the interleave device according to claim 2 or 3 and performing deinterleaving, wherein the device stores transmission data of the interleave result, and reads a read address. And deinterleaving buffer memory means for outputting deinterleaving result data, and deinterleaving indicating the relationship between the content of the synchronization pattern data or encryption word data and the data indicating the depth of deinterleaving. A depth table, receiving the synchronization pattern data or the encrypted word data, obtaining data representing the depth of the deinterleaving using the deinterleaving depth table, and based on the data representing the depth of the deinterleaving, Stored in deinterleave buffer memory means And a read address generating means for generating the read address for reading the stored data and supplying the read address to the deinterleave buffer memory means.