JPH1173330A5

JPH1173330A5 -

Info

Publication number: JPH1173330A5
Application number: JP1997234285A
Authority: JP
Filing date: 1997-08-29
Publication date: 2005-06-16
Anticipated expiration: 2017-08-29

Description

【００１５】
【課題を解決するための手段】
この発明は、割り込み要求を受付ないシステム管理モードで所定の処理を実行するコンピュータシステムに於いて、ＯＳの動作中にシステム管理割り込み要求を発生する手段と、前記システム管理割り込み要求に応答して、ＣＰＵの動作モードを前記システム管理モードに変更する手段と、前記ＣＰＵの動作モードが前記システム管理モードに変更された後、前記ＣＰＵの動作モードを、割り込み要求の受付が可能な割り込み受付可能モードに設定する手段と、前記割り込み受付可能モードで割り込み制御処理を実行する手段とを具備することを特徴とする。 [0015]
[Means for solving the problem]
This invention is characterized in that a computer system that executes predetermined processing in a system management mode that does not accept interrupt requests comprises means for generating a system management interrupt request while an OS is running, means for changing the operating mode of a CPU to the system management mode in response to the system management interrupt request, means for setting the operating mode of the CPU to an interrupt acceptance enabled mode in which interrupt requests can be accepted after the operating mode of the CPU has been changed to the system management mode, and means for executing interrupt control processing in the interrupt acceptance enabled mode .

Claims

In a computer system that executes a predetermined process in a system management mode that does not accept interrupt requests,
means for generating a system management interrupt request during operation of the OS;
means for changing the operation mode of a CPU to the system management mode in response to the system management interrupt request;
means for setting the operation mode of the CPU to an interrupt acceptance mode in which an interrupt request can be accepted after the operation mode of the CPU has been changed to the system management mode;
means for executing interrupt control processing in the interrupt acceptance enabled mode .

2. The computer system according to claim 1, wherein the means for setting the operation mode of the CPU to the system management mode comprises means for saving CPU state map information in a first area in memory in response to the system management interrupt request.

2. The computer system according to claim 1, wherein the interrupt control process is at least a suspend/resume process or a docking/undocking process of an external device.

3. The computer system according to claim 2, wherein the means for executing the interrupt control process in the interrupt acceptance mode comprises means for executing the interrupt control processes in parallel.

5. The computer system according to claim 4, wherein the means for setting the operation mode of the CPU to the interrupt acceptance mode includes means for saving CPU state map information in a second area of the memory at the time of system initialization.

6. The computer system according to claim 5, wherein the means for setting the operation mode of the CPU to the interrupt acceptance mode includes means for switching the CPU state map information stored in the first area of the memory with the CPU state map information stored in the second area.

7. The computer system according to claim 6, wherein the means for setting the operation mode of the CPU to the interrupt acceptance mode comprises means for executing a return to normal mode (RSM) instruction when the operation mode of the CPU is set to the system management mode, and setting CPU state map information stored in a first area in the memory to the CPU.

8. The computer system according to claim 7, further comprising: means for generating a system management interrupt request to change the operating mode of the CPU to the system management mode again after completing execution of interrupt control processing in the interrupt acceptance mode ; means for saving CPU state map information in a first area in the memory in response to the system management interrupt request; and means for exchanging the CPU state map information saved in the first area in the memory with the CPU state map information saved in the second area.

9. The computer system according to claim 8, further comprising means for setting the CPU state map information stored in the first area in the memory to the CPU when the computer system returns from the system management mode to a CPU mode that existed before the system management interrupt request was generated.