JPH1174465A - Semiconductor integrated circuit device - Google Patents

Abstract

(57) [Problem] To provide a semiconductor integrated circuit device which can be applied to automatic placement / wiring using a floor plan of an internal IO system and can improve chip performance / quality, reduce area and reduce man-hours. SOLUTION: This is a synchronous cache SRAM having an eight-macrocell configuration, and the semiconductor chip has a horizontal (X)
The vertical (Y) direction is divided into 11 columns extending in the vertical direction, and the vertical (Y) direction is divided into the RAM macro cell area A, the IO cell area B, and the standard cell area C, respectively. The standard cell area C is arranged between the IO cell area B and the FUS.
E macro cell 10 and PLL macro cell 11
FU in the vacant area of this IO cell area B according to the cell
An SE macro cell 10 and a PLL macro cell 11 are arranged, and an IO cell group 9 is arranged below the internal bump group 20.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device technology, and more particularly to a semiconductor device suitable for automatic placement and wiring using an internal IO type floor plan in layout design of a high-speed cache SRAM, a high-performance microprocessor, and the like. The present invention relates to a technology that is effective when applied to an integrated circuit device.

[0002]

2. Description of the Related Art For example, according to studies made by the present inventors, an SRAM as an example of a semiconductor integrated circuit device has been disclosed.
In layout design such as microprocessors,
A peripheral IO type floor plan in which an IO cell region is arranged in a peripheral portion of a semiconductor chip corresponding to a structure in which internal bumps are provided around a semiconductor chip is generally known.

Incidentally, with respect to such a layout design technique of a semiconductor integrated circuit device, for example,
On October 30, the technology described in “LSI Handbook” P161 to P189, published by Ohm Co., Ltd., edited by the Institute of Electronics, Information and Communication Engineers, etc. may be mentioned.

[0004]

In the layout design technique for a semiconductor integrated circuit device as described above, a peripheral IO type floor plan is generally used, and an internal IO
The floor plan of the method, particularly the area division and the macro cell model when applying the automatic placement / wiring are not clarified.

[0005] In addition, the integrated circuit has a hierarchical structure,
In a hierarchical design that progresses at each hierarchical level, bottom-up design starting from cell design tends to cause interference between macrocells and megacells, increase the wiring length, and fall into a floor plan where the area cannot be used effectively. In addition, the number of design steps may increase.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to apply the present invention to automatic placement / wiring using a floor plan of an internal IO system in layout design of a high-speed cache SRAM, a high-performance microprocessor, etc., thereby improving chip performance / quality and reducing area. Another object of the present invention is to provide a semiconductor integrated circuit device capable of reducing man-hours.

[0007] The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0008]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, the semiconductor integrated circuit device according to the present invention is applied to an LSI having an internal IO cell structure, and divides a semiconductor chip into a plurality of regions or stages.
This area is classified and assigned to three types, a RAM macro cell area, an IO cell area, and a standard cell area, and a standard cell area is arranged between the RAM macro cell area and the IO cell area.

[0010] Specifically, the RAM macro cell area has RA
The M macro cell, the standard cell in the standard cell area, the macro cell other than the IO cell and the RAM macro cell in the IO cell area are arranged, and the IO cell and the macro cell in this IO cell area have the same cell height. is there.

In addition, internal bumps are arranged in the upper layer of the IO cell or in the upper layer of the wiring area between the IO cell and the standard cell, and are particularly applied to a cache SRAM, a microprocessor and the like.

Therefore, according to the semiconductor integrated circuit device, the IO cell region and the standard cell region are separated from each other, and the IO cell and other macro cells are arranged side by side. Wiring can prevent interference between the two, and the area can be reduced by preventing interference between macrocells and megacells.

Further, the cell height of the macro cell is previously set to IO
By arranging macrocells in the vacant area in accordance with the cells, efficient layout can be achieved by applying automatic placement and wiring in layout design, and furthermore, the number of design steps can be reduced and the quality can be improved.

By arranging an IO cell below the internal bump and arranging an internal standard cell connected to the IO cell, particularly a latch circuit, close to each other, a transfer delay across these can be reduced. Package Pin-I
The transfer delay between the O cell and the internal cell can be reduced.

As a result, by independently providing the standard cell region to be automatically placed, automatic placement and wiring can be easily performed, and the number of design steps can be greatly reduced. Man-hours can be reduced.

[0016]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments, the same members are denoted by the same reference numerals, and the description thereof will not be repeated.

FIG. 1 is a schematic layout diagram showing a semiconductor integrated circuit device according to an embodiment of the present invention, FIG. 2 is a schematic layout diagram showing a power supply wiring, FIG. 3 is a schematic layout diagram showing a standard cell, and FIG. FIG. 5 is a circuit diagram showing a standard cell, and FIG. 5 is a functional block diagram showing a semiconductor integrated circuit device.

First, the layout configuration of the semiconductor integrated circuit device according to the present embodiment will be described with reference to FIG.

The semiconductor integrated circuit device according to the present embodiment is, for example, a synchronous cache SR having an 8-macrocell configuration.
The semiconductor chip is divided into 11 columns extending in the horizontal (X) direction in the vertical (Y) direction, and is assigned to the RAM macro cell area A, the IO cell area B, and the standard cell area C, respectively. It is configured.

In particular, a standard cell area C is arranged between the RAM macro cell area A and the IO cell area B. This is because the RAM macro cell and the IO cell are always connected via a standard cell, and the distance between the internal bump on the IO cell and the memory cell is increased to prevent α-ray noise. .

In the RAM macro cell area A, a memory array having a plurality of memory cells, a decoder, a driver, a sense amplifier, and the like, and RAM macro cells 0 to 7 including register circuits for addresses and data are arranged.
These RAM macro cells 0 to 7 correspond to one of the semiconductor chips.
Two are arranged in each of the first, fifth, seventh and eleventh columns of the one column.

In the IO cell area B, addresses, data,
IO cell group 9 including buffer circuits for control signals and the like
And a fuse (FU) for redundancy repair of a defective memory cell.
FUSE macrocell 10 composed of an SE (SE) circuit and the like, and a PLL (Phase Locked Loo
p) A PLL macro cell 11 composed of a circuit and the like is arranged. Each IO cell of the IO cell group 9, the FUSE macro cell 10, and the PLL macro cell 11 have the same cell height. Each IO cell of these IO cell groups 9 is arranged in the third and ninth columns of the semiconductor chip, and the FUSE macrocell 10 is the left and right ends of the third column, the PLL macrocell 1
1 is arranged at the center of the ninth row.

In the standard cell area C, addresses, data,
A standard cell group 12 including a register circuit for control signals and the like and a logic circuit such as a RAM interface and a mode selector is arranged. The standard cells of the standard cell group 12 are arranged in the second, fourth, sixth, eighth and tenth columns of the semiconductor chip.

In the above-described configuration including the plurality of RAM macro cell areas A, IO cell areas B, and standard cell areas C, on the surface of the semiconductor chip, ie, the IO cell area B
In the upper layer of the IO cell, and in the upper layer of the wiring area between the IO cell area B and the standard cell area C, an internal bump group 20 connected to the pins of the package is arranged.

Each of the internal bumps in the internal bump group 20 is assigned by a symbol as shown in FIG. 1, and includes a control signal bump Signal, a data bump Signal (DQ, CQ), and an internal power supply bump VSS. , VDD, external power supply bumps VSSQ, VDDQ
Is represented.

In FIG. 1, the RAM macro cells 0-7 in the RAM macro cell area A and the IO macros in the IO cell area B
Arrows shown for each IO cell of the cell group 9 indicate the direction of the cell, and the starting point of the arrow indicates the origin of the cell. Although not shown, the same applies to the FUSE macrocell 10 and the PLL macrocell 11 in the IO cell area B, and the standard cells of the standard cell group 12 in the standard cell area C.

Next, the layout of the power supply wiring will be described with reference to FIG. This power supply wiring includes the internal power supplies VSS, VD
D, an external power supply VSSQ, VDDQ, a reference power supply, a substrate control power supply, and the like, which are used in an internal circuit of a semiconductor chip.

The internal power supplies VSS and VDD are arranged in a comb-like manner in the Y-direction of the semiconductor chip below the internal bump group 20 in the metal 4 layer wiring, and the IO cell group 9 and the The upper layer of the standard cell group 12 is arranged in the X direction of the semiconductor chip.

The external power supplies VSSQ and VDDQ are metal 3
In the wiring of the layers, the upper layer of the IO cell group 9 is arranged in the X direction of the semiconductor chip. Although not shown, a reference power supply, a substrate control power supply, and the like are also arranged above the IO cell group 9 in the X direction of the semiconductor chip in the wiring of the three metal layers.

Next, the layout of each standard cell of the standard cell group 12 will be described with reference to FIG. The cell row by this standard cell can be arranged adjacently by X mirror inversion.
Further, it is formed in a region up to the first metal layer and the second metal layer on the semiconductor wafer.

The pattern of the standard cells is assigned by symbols as shown in FIG. 3, and includes active areas L and LK and a first gate polysilicon FG, respectively.
3, PFG3, FG, contact LCONT, FCON
T, through holes TH1 and TH2, a first metal layer M1, a second metal layer M2, and input / output pins IN1, IN2, and OUT.

This standard cell has, for example, a circuit configuration as shown in FIG.
And a CMOS circuit including an NMOS transistor TN1 and an NWE connected to a PMOS transistor TP1.
Switch PMOS transistor TP2 for controlling LL potential
And a switch NMOS transistor TN2 for controlling the substrate potential connected to the NMOS transistor TN1.

In this circuit configuration, the gates of the PMOS transistor TP1 and the NMOS transistor TN1 are connected to input pins IN1 and IN2, respectively, and the common drain is connected to the output pin OUT. The power supply voltages include the internal power supplies VDD, VSS, NW
An ELL potential VDB, a substrate potential VSB, an NWELL potential control power supply VDBC, and a substrate potential control power supply VSBC are supplied.

These power supply wirings are, as shown in FIG.
The internal power supplies VDD and VSS are arranged in the X direction of the semiconductor chip in the wiring of the first metal layer M1. Similarly, NWELL potential VDB, substrate potential VSB, NWELL
L potential control power supply VDBC, substrate potential control power supply VSBC
Is the X of the semiconductor chip in the wiring of the metal 1 layer M1.
It is arranged in the direction.

Next, a functional block configuration of the synchronous cache SRAM according to the present embodiment will be described with reference to FIG. Since the configuration of this synchronous cache SRAM is the same as that of a known technology, a detailed description thereof is omitted here.
Only the configuration is shown.

In this synchronous cache SRAM, RAM macro cells 0 to 7 have a × 8 macro cell configuration, and include a memory array MA including a plurality of memory cells and an address decoder AD of the memory array MA. Peripheral circuit, second stage address register SAR, clock enable register C
A plurality of registers such as an ER, a read / write register R / WR, a block select register BSR, and a second stage input data register SIDR are provided.

An address signal S is provided in the IO cell group 9.
A buffer, a buffer for the data signal DQ, a write strobe signal WS, a read / write signal R / W, a chip select signal SSB ("B" of SSB is an inverted signal of SS, the same applies to the following signal names), Buffers for control signals such as a write enable signal SWEB, mode select signals M1 and M2, and clock signals K, KB, C, CB, and GB are provided. As control signals, test signals TCK, TMS, TDO, and ZZ, and a data wide signal DW are also input and output.

The standard cell group 12 includes an IO cell group 9
Read / write register R / W as a latch circuit for each signal to RAM macro cells 0 to 7 via the buffer
R, first stage address register FAR, first stage chip enable register FCER, first stage global write register FGWR,
First stage byte write register FBWR, second stage byte write register SBWR, first stage input data register FIDR, RA
An M interface logic RAMIL, a data selector DS, a RAM clock supplier RAMCS, and the like are provided.

Further, the standard cell group 12 includes:
First stage address stack register FASR, second stage address register SAR, second stage address stack register SASR, compare register CR, write enable register WER, bypass selector BS as a latch circuit for each signal for controlling the output from RAM macro cells 0-7. , Through-out data register TODR, enable control register ECR, mode select logic MSL, first-stage output data register FODR, first-stage output enable register FOER
And so on.

In the standard cell group 12, the I
A plurality of joint test action group registers JTAGR, which are connected between the buffer of the O cell group 9 and the registers of the standard cell group 12, are data latch circuits for testing by boundary scan. JTAGR is a joint test action group controller JTA
Controlled by GC.

The operation of the synchronous cache SRAM is performed in synchronization with clock signals K and KB, an arbitrary memory cell in memory array MA is selected by an externally applied address signal SA, and a write operation to this memory cell is performed. Is input data DQ is written to a selected memory cell via a buffer and a register, and a read operation is read from a selected memory cell as output data DQ via a buffer and a register.

The synchronous cache SRAM configured as described above has a layout design based on automatic arrangement and wiring, and is based on RAM macro cells 0 to 7, each IO cell of the IO cell group 9, a FUSE macro cell 10, a PLL macro cell 11, and a standard cell. Each standard cell of the group 12 is arranged in each area, and wiring is performed between these cells to design a device.

Based on this device design, a wafer process is performed by repeating exposure and etching of a semiconductor wafer, and the semiconductor wafer is diced into individual semiconductor chips and then diced into, for example, wire bonding and mold sealing. Through an assembling process, a semiconductor integrated circuit device having a package structure is completed.

Therefore, according to the semiconductor integrated circuit device of the present embodiment, the following effects can be obtained in the layout design of the RAM macro cell area A, the IO cell area B, and the standard cell area C.

For example, the upper layer of the IO cell group 9 is an internal power supply,
Although occupied by an external power supply, a reference power supply, and the like, there is no room for signal lines to run in parallel. However, there is almost no direct data transfer between IO cells and macro cells, and both are connected via standard cells. Therefore, by separating the IO cell from the standard cell area C and arranging the IO cell and the FUSE macro cell 10 and the PLL macro cell 11 side by side, the flow of the data path can be made unidirectional, and the interference between the two due to complicated wiring can be prevented. Can be.

Further, in the design using the automatic placement / wiring, it is difficult to place the standard cells in the cell row of the IO cell group 9, but the height of the FUSE macro cell 10 and the PLL macro cell 11 is previously adjusted to the IO cell. By arranging the FUSE macro cell 10 and the PLL macro cell 11 in the vacant area of the IO cell area B, an efficient layout can be performed.

Further, an IO cell group 9 is arranged below the internal bump group 20 and an internal standard cell connected to the IO cell, particularly a latch circuit, is arranged close to the IO cell group 9 so that a transfer delay across them can be achieved. Can be reduced.

As a result, by independently providing the standard cell area C to be automatically placed, automatic placement and wiring can be easily performed, and the number of design steps can be greatly reduced.

Although the invention made by the inventor has been specifically described based on the embodiment, the invention is not limited to the embodiment, and various modifications may be made without departing from the gist of the invention. It goes without saying that it is possible.

For example, in the above embodiment, 8
The case where the present invention is applied to a synchronous cache SRAM having a macro cell configuration has been described. However, the present invention is not limited to this, and can be widely applied to other macro cell configurations such as two macro cells and four macro cells according to characteristics such as storage capacity. is there.

Further, a synchronous cache SRAM
Has been described in which the semiconductor chip is divided into 11 columns in the Y direction. However, the present invention is not limited to this, and the number of divisions can be divided into other columns in accordance with the macrocell configuration.

In the above description, the case where the invention made mainly by the present inventor is applied to a semiconductor integrated circuit device using a synchronous cache SRAM, which is a technical field to which the invention belongs, has been described. However, the present invention is not limited to this. General-purpose SRAM, DRAM, RAM, ROM, P
The present invention is widely applicable to other semiconductor storage devices such as ROM, EPROM, and EEPROM, and semiconductor integrated circuit devices such as microprocessors, and is particularly applicable to high-performance and high-quality semiconductor integrated circuit devices capable of high-speed operation. it can.

[0053]

Advantageous effects obtained by typical ones of the inventions disclosed in the present application will be briefly described.
It is as follows.

(1) A RAM macro cell area, an IO cell area, and a standard cell area are allocated to a plurality of areas or stages of a semiconductor chip, and a standard cell is provided between the RAM macro cell area and the IO cell area. By arranging the areas, separating the IO cell area from the standard cell area, and arranging the IO cells and other macro cells side by side, the flow of the data path can be made unidirectional, and the complicated wiring causes interference between the two. Therefore, the area can be reduced by preventing interference between the macro cell and the mega cell.

(2) By automatically adjusting the cell height of the macro cell to the IO cell and arranging the macro cell in this vacant area, automatic arrangement and wiring can be applied in the layout design. , An efficient layout can be achieved, and the number of design steps can be reduced and the quality can be improved.

(3) By arranging the IO cells below the internal bumps and arranging the internal standard cells connected to the IO cells, especially the latch circuits, close to each other, the transfer delay across them can be reduced. Therefore, it is possible to reduce the transfer delay between the pin, the IO cell, and the internal cell of the package.

(4) According to the above (1) to (3), in the layout design of a semiconductor integrated circuit device such as a high-speed cache SRAM and a high-performance microprocessor, a standard cell region to be automatically placed is independently provided. In this case, automatic placement and wiring can be easily performed, and the number of design steps can be significantly reduced. Therefore, the chip performance and quality can be improved, the chip area can be reduced, and the number of design steps can be reduced.

[Brief description of the drawings]

FIG. 1 is a schematic layout diagram showing a semiconductor integrated circuit device according to an embodiment of the present invention.

FIG. 2 is a schematic layout diagram showing power supply wiring in the semiconductor integrated circuit device according to one embodiment of the present invention;

FIG. 3 is a schematic layout diagram showing standard cells in the semiconductor integrated circuit device according to one embodiment of the present invention;

FIG. 4 is a circuit diagram showing a standard cell in the semiconductor integrated circuit device according to one embodiment of the present invention;

FIG. 5 is a functional block diagram showing a semiconductor integrated circuit device according to one embodiment of the present invention.

[Explanation of symbols]

A RAM macro cell area B IO cell area C Standard cell area 0-7 RAM macro cell 9 IO cell group 10 FUSE macro cell 11 PLL macro cell 12 Standard cell group 20 Internal bump group TP1 PMOS transistor TN1 NMOS transistor TP2 Switch PMOS transistor TN2 Switch NMOS transistor MA Memory Array AD Address Decoder SAR Second Stage Address Register CER Clock Enable Register R / WR Read / Write Register BSR Block Select Register SIDR Second Stage Input Data Register R / WR Read / Write Register FAR First Stage Address Register FCER First Stage Chip Enable Register FGWR First stay Global write register FBWR First stage byte write register SBWR Second stage byte write register FIDR First stage input data register RAMIL RAM interface logic DS Data selector RAMCS RAM clock supplier FASR First stage address stack register SAR Second stage address register SASR Second stage address stack register CR Compare register WER Write enable register BS Bypass selector TODR Through-out data register ECR Enable control register MSL Mode select logic FODR First stage output data register FOER First stage out Tsu door enable register JTAGR Joint Test Action Group Register JTAGC Joint Test Action Group controller

 ──────────────────────────────────────────────────の Continuing from the front page (72) Inventor Masahiko Nishiyama 2326 Imai, Ome-shi, Tokyo Inside the Hitachi, Ltd.Device Development Center (72) Inventor Kayoko Saito 2326, Imai, Ome-shi, Tokyo Hitachi, Ltd. Inside

Claims (5)

[Claims] 1. A semiconductor integrated circuit device having an internal IO cell structure to which a layout design by automatic arrangement and wiring is applied, wherein a semiconductor chip is divided into a plurality of regions in a predetermined direction, and a RAM is provided in each region. Macrocell area, I
O cell area and standard cell area are allocated, and the RAM
A semiconductor integrated circuit device, wherein the standard cell region is arranged between a macro cell region and the IO cell region. 2. The semiconductor integrated circuit device according to claim 1, wherein a RAM macro cell is arranged in said RAM macro cell area, a standard cell is arranged in said standard cell area, and an IO cell is arranged in said IO cell area. A semiconductor integrated circuit device comprising a cell and a macro cell other than the RAM macro cell. 3. The semiconductor integrated circuit device according to claim 2, wherein said IO cell and said macro cell in said IO cell region have the same cell height. 4. The semiconductor integrated circuit device according to claim 2, wherein an upper layer of the IO cell arranged in the IO cell region,
Alternatively, a semiconductor integrated circuit device is characterized in that internal bumps are arranged in an upper layer of a wiring region between the IO cell and the standard cell arranged in the standard cell region. 5. The semiconductor integrated circuit device according to claim 1, wherein said semiconductor integrated circuit device is a cache SRAM or a microprocessor.