JPH1174792A - Digital-to-analog conversion circuit - Google Patents

Abstract

(57) Abstract: In a DA converter using a resistor string, it is possible to switch between three digital signal inputs having different variable bits with a simple circuit configuration. A first bit expansion circuit, a resistor string, and a second bit expansion circuit, a first operation mode in which all bits of a digital signal input change, and a second operation mode in which some bits of a digital signal input change. A first connection control circuit for controlling connection of the bit extension circuit to the resistor string in accordance with the operation mode and a third operation mode in which fewer bits change, and a middle point C of the resistor string in the third operation mode. A second connection control circuit 27 connected to the ground node and a digital signal input,
Selection circuits 16, 17, 18, 2 for selectively extracting the voltage of each voltage dividing node of the bit extension circuit and the resistor string
2 and 23.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital-to-analog (DA) conversion circuit formed on a semiconductor integrated circuit, and more particularly to a resistance string type DA conversion circuit used for various electronic devices.

[0002]

2. Description of the Related Art For example, a digital-to-analog converter (D / A) converter is used for processing various digital signals inside a one-chip microcomputer / controller (hereinafter, referred to as a microcomputer) and then converting the digital signals into analog signals. Is known as a string resistance method.

[0003] A DA converter circuit of the string resistance type has n
To perform DA conversion of the bit, a decoder for decoding a binary code signal of n bits, 2 ⁿ pieces of resistive elements between the reference voltage and a ground voltage and a resistor string connected in series, 2 ⁿ pieces of And a switch circuit for selectively extracting a plurality of voltages divided by a resistor string. The switch circuit has high accuracy and excellent monotonicity.

However, the output voltage obtained by the DA converter is one of values obtained by dividing the reference voltage Vref and the ground voltage Vss into 2 ⁿ -1 units in units of Vref / ^2n. Considering that the DA conversion circuit is used not only as a DA conversion circuit dedicated to n bits but also as a DA conversion circuit for m (m <n) bits,
The following problems occur.

That is, when an n-bit signal is input, an n-bit signal input is supplied to the n address input terminals of the decoding circuit correspondingly, and when an m-bit signal is input, one of the n address input terminals of the decoding circuit is supplied. An address connection switching circuit (address map switching circuit) so as to supply an n-bit signal input to the upper m address input terminals in a corresponding manner.
Must be added, which complicates the circuit configuration.

Alternatively, when an n-bit signal is input, 2 ⁿ output signals of the decoding circuit are supplied corresponding to 2 ⁿ switch circuits, and when an m-bit signal is input, 2 ^m output signals of the decoding circuit are supplied. Since it is necessary to add a switch connection switching circuit so as to supply corresponding to some of the 2 ⁿ switch circuits, the circuit configuration becomes complicated.

In order to solve such a problem, the inventor of the present application has made it difficult to complicate the circuit configuration even when switching between two operation modes in which the number of variable bits of the digital signal input is different. DA designed to make it easier
Conversion circuit (Japanese Patent Application No. 5-55574, JP-A-6-268)
No. 525) or a voltage dividing circuit (Japanese Patent Application No. Hei 7-17).
No. 2166, JP-A-9-23160) have already been proposed.

However, even in the case where switching is performed in accordance with three operation modes in which the number of variable bits of the digital signal input is different from each other, it is possible to make the circuit configuration more complicated by improving the circuit configuration. Effective DA
It is desirable to provide a conversion circuit.

[0009]

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and does not greatly increase the number of used resistive elements, switch elements, and the like and the pattern area thereof.
It is possible to switch between three operation modes in which the number of variable bits of the digital signal input is different, thereby realizing DA conversion of a multi-bit digital signal, which is suitable for an integrated circuit. An object is to provide an analog conversion circuit.

[0010]

A digital-to-analog conversion circuit according to the present invention comprises a first bit extension circuit, a resistor string, and a second bit extension circuit in which a plurality of resistance elements each having the same resistance value are connected in series. A first bit extension circuit, a resistor string, and a second bit extension circuit in series between a reference voltage node and a ground voltage node in a first operation mode in which all bits of a digital signal input change. A second operation mode in which some bits of the digital signal input change and a third operation mode in which less bits change, the first operation mode is connected between the reference voltage node and the ground voltage node. A first connection control circuit for connecting the resistor string without passing through a bit extension circuit and a second bit extension circuit;
In the operation mode of the second operation mode and the second operation mode, an intermediate point obtained by dividing the resistance string into two equal parts is not connected to the ground voltage node. In the third operation mode, the intermediate point is connected to the ground voltage node. A second connection control circuit to be connected, the digital signal input being decoded, and the voltage at each of the voltage dividing nodes of the first bit extension circuit, the resistor string, and the second bit extension circuit being selectively selected according to the decoded output. And a selection circuit for extracting the data.

[0011]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 and FIG. 2 show an example of a block configuration and an example of a circuit configuration of a DA converter circuit for switching between three modes according to a first embodiment of the DA converter circuit of the string resistance type according to the present invention.

1 and 2, reference numeral 11 denotes a first voltage node (Vref node) to which a reference voltage Vref is applied, 13 denotes a second voltage node (Vss node) to which a ground voltage Vss is applied, and 12 denotes a second voltage node (Vss node). First bit extension circuit, 14
Is a second bit extension circuit, 15 is a resistor string, and the first bit extension circuit 12 and the resistor string 1
5 and the second bit extension circuit 14 are connected in series.

The resistor string 15 has the same resistance value, for example, 2 ^K (k ≧ 1, in this example, k = 3, 2
^K = 8) first resistance elements R1 to R8 are connected in series.

The first bit extension circuit 12 has 2 ^L (L ≦ k, L = k−1 in this example) having the same resistance value.
= 2, 2 ^L = 2 ^L / 2 = 4) resistance elements R _{L1 to} R _L4 are connected in series.

The second bit extension circuit 14 has 2 ^J (J ≦ k, J = k−1 in this example) having the same resistance value.
= 2, 2 ^J = 2 ^L / 2 = 4) resistance elements R _{J1 to} R _J4 are connected in series.

The first operation mode in which all bits (4 bits in this example) of the digital signal input change, and the operation mode in which some bits of the digital signal input change (the 3rd bit in this example changes). For controlling the connection relationship between the first bit extension circuit, the resistor string, and the second bit extension circuit according to the second operation mode and the third operation mode in which two less bits change. A connection control circuit is provided.

The first connection control circuit connects the first bit extension circuit 12, the resistor string 15, and the second bit extension circuit 14 to the Vre in the first operation mode.
f is connected in series between node 11 and Vss node 13,
In the second operation mode and the third operation mode, the resistor string 15 is connected between the Vref node 11 and the Vss node 13 without passing through the first bit extension circuit and the second bit extension circuit. It is configured as follows.

As a specific example of the first connection control circuit, a first switch circuit 12a having one end connected to the Vref node 11 and the other end connected to one end node of the resistor string 15; One end is the Vref node 1
1 and a second switch circuit 12b having the other end connected to one end node of the resistance element R _L1 of the first bit extension circuit 12 and one end connected to the other end node of the resistor string 15. a third switching circuit 14a whose other end is connected to the ssV node 13 has one end connected to one end node of the resistive element R _J4 of the second bit extension circuit 14, the other end said ssV node 13 And a fourth switch circuit 14b connected thereto.

In this case, for example, the first switch circuit 12a in the first bit extension circuit 12 and the third switch circuit in the second bit extension circuit 14 according to the logical level of the 1-bit bit switching signal BCH. 14a for controlling both the second switch circuit 12b in the first bit extension circuit 12 and the fourth switch circuit 14b in the second bit extension circuit 14 to the selected state. Three logic circuits 25 are provided.

The third logic circuit 25 transmits the bit switching signal BCH and the signal BCH to the inverter circuit 2.
Control is performed by a signal inverted by 51. The intermediate point obtained by dividing the resistance string 15 into two equal parts is represented by C.
2 ^K / 2 resistor elements R1 to R between one end node on the Vref node side of the resistor string 15 and the intermediate point C
4 to the first resistor string 15a, V
The 2 ^K / 2 resistor elements R5 to R8 between the other node on the ss node side are referred to as a second resistor string 15b.

In the first operation mode and in the second operation mode, the intermediate point C is not connected to the Vref node, and in the third operation mode, the intermediate point C is connected to the Vref node. A second connection control circuit 27 is provided.

One specific example of the second connection control circuit 27 is a third operation mode switch circuit SWX composed of, for example, a CMOS transfer gate connected between the intermediate point C of the resistor string 15 and the Vss node. For example, according to a logic level of a 1-bit third operation mode control signal CCH (depending on whether or not the third operation mode is designated), a second operation mode for controlling the switch circuit SWX to be turned on / off. 3 operation mode control circuit 26 (for example, including an inverter circuit 261).

Further, the variable bit of the digital signal input is decoded, and the voltage of each voltage dividing node of the first bit extension circuit 12, the resistor string 15, and the second bit extension circuit 14 is selected according to the decoded output. There is provided a selection circuit for selectively extracting the data.

This selection circuit selectively takes out a voltage from all of the voltage dividing nodes in the first operation mode, and selects each voltage corresponding to the resistor string 15 in the second operation mode. A voltage is selectively taken out from the voltage dividing nodes, and in the third operation mode, a voltage is selectively taken out from each voltage dividing node of the first resistor string 15a of the resistor strings 15. It is configured as follows.

Hereinafter, a specific example of the selection circuit will be described. The selection circuit includes a first selection circuit 16, a second selection circuit 17, a third selection circuit 18, a first logic circuit 22, a second logic circuit 23, and a third selection circuit. Circuit 1
8 and an impedance conversion circuit 19 inserted between the DA conversion output node 20 and the output node.

The first selection circuit 16 divides the voltage from each of the 0th and even-numbered resistance connection nodes from the Vss node side in the first bit extension circuit 12, the resistor string 15, and the second bit extension circuit 14. It is composed of a plurality of switch elements (for example, CMOS transfer gates) SW2, SW4,..., SW16 for extracting a voltage.

The second selection circuit 17 extracts a divided voltage from each of the odd-numbered resistance connection nodes from the Vss node side in the first bit extension circuit 12, the resistor string 15, and the second bit extension circuit 14. Switch elements (for example, CMOS transfer gate) S
.., SW15.

The third selection circuit 18 comprises two switch elements (for example, CMOS transfer gates) for selectively taking out the selection output of the first selection circuit 16 and the selection output of the second selection circuit 17. SWa and SWb.

The first logic circuit 22 includes signals A3 to A1 other than the least significant bit LSB (A0) of the digital signal DS (4-bit digital signals A3 to A0 in this example), and inverted signals / A3 to / A3. A1 is a three-input NAND circuit N1-
N8, and the complementary signals of the decoded signals are generated by the inverter circuits I1 to I8. In response to the decoded signals, the switch element groups SW2, SW4,. , SW3,..., SW15
Is similarly controlled. In this case, the decoding operation of a part of the first logic circuit 22 may be controlled in accordance with the logic level of the bit switching signal BCH and the logic level of the third operation mode control signal CCH.

The second logic circuit 23 controls the switch elements SWa and SWb of the third selection circuit 18 according to the least significant bit signal A0 of the digital signals A3 to A0. In this case, the logic level of the signal A0 is “0” /
According to the "1" state, the selection output of the first selection circuit 16 / the selection output of the second selection circuit 17 is selected.

The second logic circuit 23 controls the two switch elements SWa and SWb of the third selection circuit 18 in a complementary manner by the signal A0 and a signal obtained by inverting the signal A0 by the inverter circuit 231. It is configured to be.

Next, the operation of the DA converter having the above configuration will be described. A first connection control circuit (two switch circuits 12a and 12b of the first bit extension circuit 12 and two switches of the second bit extension circuit 14) controlled according to the bit switching signal BCH as described above. Circuit 14a,
14b), and a second connection control circuit (third operation mode switch circuit SWX, third operation mode control circuit 26) controlled according to a third operation mode control signal CCH. With the configuration, the DA conversion operation can be selectively performed corresponding to three operation modes in which the number of variable bits of the digital signal is different.

That is, in this example, the 4-bit digital signal A
An all-bit (4-bit) variable mode operation in which all bits 3 to A0 change; a 3-bit variable mode operation in which only three bits A2 to A0 of the digital signals A3 to A0 change; A two-bit variable mode operation in which only two bits A1 to A0 of A0 change is possible.

(1) In the first operation mode in which all bits A3 to A0 of a 4-bit digital signal can be changed,
The bit switching signal BCH turns off / on the first switch circuit 12a / second switch circuit 12b in the first bit extension circuit 12 correspondingly, and the third switch circuit 14a in the second bit extension circuit 14 / 4th
Of the switching circuit 14b in response to control the off / on state, the first bit extension resistance element group of circuit 12 R _L1 to R _L4
And the resistance element groups R _{J1 to} R _{J of} the second bit extension circuit 14.
_{Put J4} in use. Further, the third operation mode control signal C
CH controls the operation mode switching switch circuit SWX to the off state, and all the resistance element groups R1 of the resistance string 15
-R8 are put in use.

The first logic circuit 22 switches the switch element groups SW2, SW4,..., SW16 of the first selection circuit 16 according to the upper three bits A3 to A1 of the digital signal.
And switch element groups SW1, S of the second selection circuit 17
W3,..., SW15 are similarly controlled, and the first selection circuit 1
6 and the second selection circuit 17, a pair of adjacent voltage dividing nodes (the 0th voltage dividing node and the 1st number voltage dividing node,
Alternatively, an even-numbered voltage and an odd-numbered voltage dividing node voltage are extracted.

Further, the selection output of the first selection circuit 16 or the selection output of the second selection circuit 17 is used as the digital signal A
A desired DA conversion output can be obtained by making a selection by the third selection circuit 18 according to the level of 0.

For example, a 4-bit digital signal A3, A
When (0001) = 1 in A1, A2, and A0, the first logical circuit 22 sets the upper three bits A3 to A1 = (00
0), only the output of the NAND circuit N8 becomes “0”, only the switch element SW16 is turned on in the first selection circuit 16, and the switch element SW16 is turned on in the second selection circuit 17.
15 is turned on, and the third selection circuit 18
In response to 0 = "1", the selection output of the second selection circuit 17 (the voltage of the odd-numbered voltage dividing node, here, the voltage of the first voltage dividing node from the Vss node side of all voltage dividing nodes) is activated by the switch SWb. Voltage).

(2) Three bits A2 to A0 of the digital signal
In the second operation mode in which the first switch circuit 12a / second switch circuit 12 in the first bit extension circuit 12 can be changed.
b corresponding to the on / off state, the second bit extension circuit 1
4 to control the third switch circuit 13a / fourth switch circuit 14b to the on / off state correspondingly, so that the resistance element groups R _{L1 to} R _L4 and the second
The resistance element groups R _{J1 to} R _J4 of the bit expansion circuit 14 of FIG. Further, the third operation mode control signal CCH controls the third operation mode switch circuit SWX to an off state,
All the resistance element groups R1 to R8 of the resistance string 15 are put into a use state.

In the second operation mode, the resistance element groups R _{L1 to} R _{L4 of} the first bit extension circuit 12 and the second
In response to _bringing the resistance element groups R _{J1 to} R _J4 of the bit extension circuit 14 into the non-use state, digital signal conversion processing and non-operation control of some NAND circuits of the first logic circuit 22 are performed. .

That is, the digital signal input of the first logic circuit 22 is shifted (+4 shift in this example) by the number of resistance element groups R _{J1 to} R _J4 of the second bit extension circuit 14 (4 in this example). For this purpose, the variable three bits A2 to A0 are converted into 4-bit digital signals A3 to A0 in which a bit corresponding to +4 is added and input. This conversion processing is performed by a digital signal conversion processing circuit (not shown) based on the bit switching signal BCH. Further, the bit switching signal BCH controls the NAND circuits N1, N2, N7 and N8 of the first logic circuit to a non-operating state.

The first logic circuit 22 switches the switch element groups SW6, SW8,..., S of the first selection circuit 16 according to the upper three bits A3, A2, A1 of the digital signal.
W12 and the switch element group SW5 of the second selection circuit,
The switches SW7,..., And SW11 are similarly controlled, and the first selection circuit 16 and the second selection circuit 17 take out the voltages of the adjacent even-numbered voltage division nodes and the odd-numbered voltage division nodes.

Further, by selecting the selection output of the first selection circuit 16 or the selection output of the second selection circuit 17 by the third selection circuit 18 in accordance with the level of the signal A0, a desired DA conversion output is obtained. can get.

That is, the variable 3-bit signals A2, A1,.
When A0 is, for example, (101) = 5, 4-bit digital signals A3, A2, A1, A0 = (1001) = 9
Converted to and input. Then, in the first logic circuit 16, only the output of the NAND circuit N5 becomes "0" according to the upper three bits A3, A2, A1 = (100), and only the switch element SW8 is turned on in the first selection circuit. State, only the switch element SW7 is turned on in the second selection circuit, and the third selection circuit 18 selects the output of the second selection circuit 17 by the switch SWb in response to the signal A0 = "1". Then, the voltage of the fifth voltage dividing node from the Vss node side of the voltage dividing nodes of the resistor string 15 is extracted.

(3) Two bits A1, A0 of the digital signal
In the third operation mode in which the first switch circuit 12a / second switch circuit 12 in the first bit extension circuit 12,
b corresponding to the on / off state, the second bit extension circuit 1
4 to control the third switch circuit 14a / fourth switch circuit 14b to the on / off state correspondingly, so that the resistance element groups R _{L1 to} R _L4 and the second
The resistance element groups R _{J1 to} R _J4 of the bit expansion circuit 14 of FIG. Further, the third operation mode control signal CCH controls the third operation mode switch circuit SWX to an on state,
Second resistor string 15 of resistor strings 15
The resistance element groups R5 to R8 of b are put into the non-use state.

In the third operation mode, the resistance element groups R _{L1 to} R _L4 of the first bit expansion circuit 12, the resistance element groups R _{J1 to} R _{J4 of} the second bit expansion circuit 14, and the resistance strings 15 In response to bringing the resistance element groups R5 to R8 of the second resistance string 15b into the non-use state, the digital signal conversion processing and the non-operation control of some NAND circuits of the first logic circuit 22 are performed. Will be

That is, the number of resistance element groups R _{J1 to} R _J4 of the second bit extension circuit 14 (four in this example) and the number of resistance element groups R5 to R8 of the second resistance string 15b (four in this example) ) In order to shift the digital signal input of the first logic circuit 22 by the sum (+8 shift in this example) by the sum of the variable 2 bits A1 and A0, a bit corresponding to +8 shift is added to the variable 2 bits A1 and A0 Bit digital signals A3 to A0
Converted to and input. This conversion processing is performed by a digital signal conversion processing circuit (not shown) based on the bit switching signal BCH and the third operation mode control signal CCH.

The bit switching signal BCH and the third operation mode control signal CCH control the NAND circuits N1, N2, N5 to N8 of the first logic circuit to be in an inactive state. The first logic circuit 22 switches the switch element groups SW6 and SW8 of the first selection circuit 16 and the switch element group SW5 of the second selection circuit in accordance with the upper three bits A3, A2 and A1 of the digital signal. SW7 is similarly controlled, and the first selection circuit 16 and the second selection circuit 17 take out the voltage of a pair of adjacent even-numbered voltage dividing nodes and the voltage of the odd-numbered voltage dividing nodes. Further, the selection output of the first selection circuit 16 or the selection output of the second selection circuit 17 is changed according to the level of the signal A0.
, A desired DA conversion output is obtained.

That is, when the variable 2-bit signals A1 and A0 are, for example, (01) = 1, they are converted into 4-bit digital signals A3, A2, A1, and A0 = (1001) = 9 and input. Then, in the first logic circuit 22, only the output of the NAND circuit N4 becomes "0", only the switch element SW8 is turned on in the first selection circuit 16, and only the switch element SW7 is turned on in the second selection circuit 16. In response to the signal A0 = "1", the third selection circuit 18 turns on the selection output of the second selection circuit 17 by the switch element SWb (in this case, the voltage is applied to the voltage dividing node of the first resistor string 15a). From the Vss node side).

Therefore, according to the above-mentioned DA converter circuit, it is possible to switch and use the digital signal input corresponding to three operation modes having different variable bit numbers.
Further, in the DA conversion circuit, an addition circuit (operational amplification circuit) 30 is added to the output side of the impedance conversion circuit, the input of the n-bit digital signal is divided into a plurality of bits, and at least two DA conversion circuits are provided. By sequentially switching to a different operation mode and adding the D / A conversion output in each mode to analog, D / A conversion of a digital signal of more bits becomes possible.

In this case, the three operation modes include two D / A conversion operation modes for an even-numbered digital signal and one D / A conversion operation mode for an odd-numbered digital signal. If the respective DA conversion outputs in the DA conversion operation mode are analog-added, more even-bit digital signals can be DA-converted. Further, if the respective DA conversion outputs in the above three operation modes are added in an analog manner, it is possible to perform D / A conversion of digital signals of more odd bits.

For example, first, D / A conversion is performed on the upper (n−m−k) bits of the n bits, then D / A conversion is performed on the middle m bits of the n bits, and D / A conversion for each bit
By adding a predetermined weight to the A-conversion output (by changing the operation coefficient), a DA conversion output of an n-bit digital signal is obtained as a result.

In this way, in the DA converter of the above-described embodiment, the digital conversion of the digital signal of 4 bits + 3 bits + 2 bits = 9 bits becomes possible, without increasing the number of resistance elements and switch elements. , A DA conversion of a multi-bit digital signal can be realized.

In the case of a D / A conversion circuit which only needs to satisfy a monotonic increasing characteristic, for example, for driving a liquid crystal display panel, a D / A conversion in which a digital signal is divided into two is performed, and a high D value is obtained.
In the case of a D / A conversion circuit requiring A-conversion accuracy, the usage can be selected according to the application of the D / A conversion circuit, such as performing D / A conversion in which a digital signal is divided into three.

[0054]

As described above, according to the DA converter of the present invention, the number of variable bits in the digital signal input differs without increasing the number of resistors and switch elements used and the pattern area thereof. Switching can be performed in accordance with three operation modes, thereby realizing DA conversion of a multi-bit digital signal, which is suitable for integration into an integrated circuit.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a DA converter according to a first embodiment of the present invention;

FIG. 2 is a circuit diagram showing a specific example of the DA converter circuit of FIG. 1;

[Explanation of symbols]

12: a first bit extension circuit, R _{L1 to} R _L4 : a resistance element of the first bit extension circuit, 14: a second bit extension circuit, R _{J1 to} R _J4 : a resistance element of the second bit extension circuit, 12a, 12b, 14a, 14b: first connection control circuit, 15: resistor string, R1 to R8: resistor element of resistor string, C: midpoint of resistor string, 15a: first resistor string, 15b: second 16: a first selection circuit, 17: a second selection circuit, 18: a third selection circuit, 20: a voltage output terminal, 22: a first logic circuit, 23: a second logic circuit, 25: third logic circuit, 26: third operation mode control circuit, SWX: third operation mode switch circuit, 27: second connection control circuit, A3 to A0: digital signal input.

Claims (3)

[Claims] A first bit extension circuit, a resistor string, and a second bit extension circuit in which a plurality of resistance elements each having the same resistance value are connected in series; and a first bit extension circuit in which all bits of a digital signal input change. In the operation mode, the first bit extension circuit, the resistor string, and the second bit extension circuit are connected in series between a reference voltage node and a ground voltage node, and some bits of a digital signal input change. In the second operation mode and the third operation mode in which fewer bits change, the first bit extension circuit and the second bit extension circuit do not intervene between the reference voltage node and the ground voltage node. A first connection control circuit for connecting the resistor string; and A second connection control circuit that does not connect the divided intermediate point to the ground voltage node, and connects the intermediate point to the ground voltage node in the third operation mode; A digital-to-analog conversion circuit, comprising: a selection circuit for selectively extracting a voltage of each voltage dividing node of the first bit extension circuit, the resistor string, and the second bit extension circuit according to an output. 2. The digital-to-analog conversion circuit according to claim 1, wherein said selection circuit selectively takes out a voltage from all of said voltage dividing nodes in said first operation mode, and In the second operation mode, a voltage is selectively taken out from each voltage dividing node corresponding to the resistor string, and in the third operation mode, a voltage from the reference voltage node of the resistor string to the intermediate point is obtained. A digital-to-analog conversion circuit for selectively extracting a voltage from each voltage dividing node. 3. The digital-to-analog conversion circuit according to claim 1, wherein said selection circuit comprises: said first bit extension circuit, a resistor string, and a second bit extension circuit.
A first selection circuit including a plurality of switch elements for extracting a divided voltage from each of the even-numbered resistance connection nodes in the bit expansion circuit, and the first bit expansion circuit, the resistance string, and the second selection circuit.
A second selection circuit composed of a plurality of switch elements for extracting a divided voltage from each of the odd-numbered resistance connection nodes in the bit extension circuit, and a selection output of the first selection circuit and a selection of the second selection circuit A third selection circuit including a switch element for selectively extracting an output; a switch element of the first selection circuit and a switch of the second selection circuit according to a signal other than the least significant bit of the digital signal input A first logic circuit for controlling an element; and a second logic circuit for controlling a switch element of the third selection circuit in accordance with a signal of the least significant bit of the digital signal input. Digital-to-analog conversion circuit.