JPH1175367A - Dc/dc converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the efficiency of a DC/DC converter and reduce its cost. SOLUTION: In a DC/DC converter, a DC power supply to a load is turned on and off by the switching operation of a MOS transistor Q1 . The DC/DC converter has a detecting means R1 which detects whether the load 1 is large or small and a connecting means SW1 with which another MOS transistor Q2 is connected in parallel to the MOS transistor Q1 when the detecting means R1 detects that the load is large.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DC / DC converter, and more particularly, to a technology that operates efficiently even when the magnitude of a load current changes.

[0002]

2. Description of the Related Art Conventionally, DC / DC converters have been used.
Have been. JP-A-9-140126 discloses this DC /
A conventional example of a DC converter is disclosed. FIG.
Shown is a conventional circuit. In FIG. 4, the DC / DC converter
(Note that in Japanese Patent Application Laid-Open No. 9-140126,
Regulator. ) Indicates the output circuit 20,
PWM control circuit 30, output control circuit 40, and switch S
W _FiveConsists of The output circuit 20 has a power MOS field effect.
Transistor (hereinafter "MOS field effect transistor")
Is a “MOS transistor”. ) (MOSFET)
Q₁₁, Q₁₂, Diode D_Three, Inductance L_Three,
Anti-R_Three, Capacitor C_Five, C₆And drivers 21 and 22
Consists of The transistor Q₁₁Is large allowable output current
Transistor, and transistor Q₁₂Is the allowable output
It is a transistor with small current.

[0003] The driver 21 drives the transistor Q _11, the driver 22 is for driving the transistor Q _12. The transistors Q ₁₁ and Q ₁₂ perform a switching operation, and the sources and drains of the transistors Q ₁₁ and Q ₁₂ are connected in parallel. Inductance L ₃ and capacitor C ₆ is a smoothing. The power terminal 23 is connected to the sources of the transistors Q ₁₁ and Q ₁₂ . Load resistor R ₆ is connected to the output terminal 24. The PWM control circuit 30 includes an oscillator 31, a control logic 32, a comparator 3,
3, a differential amplifier 34, reference voltage 35, the resistor R _4, R ₅ and controllable offset voltage 36.

[0004] PWM control circuit 30, to the voltage of the output terminal 24 to adjust the current through resistor R ₃ to a desired value, current-mode pulse-width modulation controlling the duty cycle of the driver 21 ( PWM) circuit. The control logic 32 is controlled by the oscillator 31 so that the driver 2
An on-pulse of a constant frequency is supplied to 1, 22. With each ON pulse, the drivers 21 and 22 turn on the transistors Q ₁₁ and Q ₁₂ . Incidentally, when the current flowing through the inductance L ₃ is shown a comparator 33 that it has reached a level which is set by the differential amplifier 34, control logic 32 serves to turn off the Torajisuta Q _11, Q _12. The output control circuit 40 includes a comparator 41 and a reference voltage 42.
Consists of To to work effectively, the output control circuit 40 and a light load by the switch SW ₅ (resistance R ₃
When the current flowing through the transistor Q is small)
₁₁ does not operate, the transistor Q ₁₂ operates, in heavy load, the transistor Q ₁₂ does not operate, the transistor Q ₁₁ operates.

[0005]

[SUMMARY OF THE INVENTION However, in the conventional example described above, when the load current is large using a large power MOS transistors Q _11, does not use small power MOS transistors Q _12, large power MOS transistor Q ₁₁ You can not control the load of capacity together a small power MOS transistor Q _12. Therefore, in order to control the load of a predetermined capacity, since a small power MOS transistor Q ₁₂ is wasted, there is a drawback that the cost is increased. Therefore, an object of the present invention is to provide a DC / DC converter that eliminates the above-mentioned disadvantages of the conventional example, operates efficiently even when the load current is large or small, and is inexpensive.

[0006]

According to a first aspect of the present invention, there is provided a DC / DC converter in which a switching operation is performed between a load and a DC power supply by a MOS transistor. DC / DC comprising: detecting means for detecting the magnitude of the load; and connecting means for connecting another MOS transistor in parallel with the MOS transistor when the detecting means detects that the load is large. It is a converter.

According to the configuration of the first invention, when the detecting means detects the magnitude of the load and the detecting means detects that the load is large, the connecting means switches the load and the DC power supply by switching operation. Since another MOS transistor is connected in parallel with the MOS transistor that turns on and off, the DC / DC converter can be operated efficiently regardless of the size of the load.

Further, according to a second aspect of the present invention, there is provided a DC / DC converter in which switching between a load and a DC power supply is turned on and off by a switching MOS transistor, a detecting means for detecting the magnitude of the load, and the load is large. When the detection means detects that the other MOS transistor is connected in parallel with the MOS transistor that drives the MOS transistor.
A DC / DC converter comprising: a connection unit for connecting a transistor.

Further, according to the second aspect of the present invention, there is provided a DC / DC converter in which a switching operation is performed between a load and a DC power supply by a MOS transistor.
The detecting means detects the magnitude of the load, and when the detecting means detects that the load is large, the connecting means sets the M
Since another MOS transistor is connected in parallel to the MOS transistor that drives the OS transistor, the DC / DC converter can be operated efficiently regardless of the magnitude of the load.

[0010]

FIG. 1 shows a circuit of a DC / DC converter according to a first embodiment of the present invention.
In FIG. 1, a power MOS transistor (p-channel type MOSFE) is connected in series between a power supply terminal 6 and an output terminal 7.
T) between the source and the drain of Q _1, the inductance L ₁ and resistor R ₁ are connected in series, the DC power source + V _DD is connected between the power supply terminal 6 and a ground point, a ground point load 1 and the output terminal 7 Is connected between. Furthermore, between the source and the drain of the power MOS transistor (p-channel type MOSFET) Q ₂ are connected in parallel between the source and drain of the MOS transistor Q _1. MOS transistor (n-channel type MOSFET) Q ₃ has a source connected to ground, a drain connected to the drain of the MOS transistor Q _1. Furthermore, between the source and the drain of the MOS transistor (n-channel type MOSFET) Q ₄ is M
Between the source and the drain of the OS transistor Q ₃ are connected in parallel.

The output terminal of the differential amplifier 2 is connected to a switch SW
₁Input terminal d₁And switch SW _TwoInput terminal d_TwoTo
It is connected. The differential amplifier 2 has a resistor R₁Voltage and off
Set voltage V_S1And the difference voltage is input
If it is less than the value, switch SW₁And switch SW_TwoTo
Connection state (SW₁Then terminal a₁And terminal b₁But
Connected, SW_TwoThen terminal a_TwoAnd terminal b_TwoWas connected
State), and when the difference voltage exceeds the predetermined value,
Switch SW₁And switch SW_TwoWith a dotted line
State (SW₁Then terminal a₁And terminal c₁Is connected and SW_Two
Then terminal a_TwoAnd terminal c_TwoIs connected). System
The control circuit 3 includes drivers 4, 5 and a switch SW.₁, SW_Two
Contains. The output terminal of driver 4 is
Jista Q₁Gate and switch SW₁Terminal c₁Contact
The output terminal of the driver 5 is a MOS transistor
Q_ThreeGate and switch SW_TwoTerminal c_TwoConnected to
ing. Diode D₁Is a MOS transistor on the cathode
TA Q₁And the anode is grounded.
You. Capacitor C₁Is connected between the power terminal 6 and the ground point
And the capacitor C_TwoIs connected between the output terminal 7 and the ground point.
Has been continued.

With the above configuration, the load 1 is equal to or less than a predetermined value.
When the load is light, the resistance R₁The voltage drop is small
And switch SW₁And switch SW_TwoConnection with a solid line
It is the state shown. Therefore, the driver 4 of the control circuit 3
MOS transistor Q₁Drive the gate of the driver 5
Is the MOS transistor Q_ThreeDrive the gate. In addition,
At this time, the MOS transistor Q_TwoBetween gate and source
Is a switch SW₁Terminal a₁, B₁Short-circuited by M
OS transistor Q_FourSwitch S between gate and source
W_TwoTerminal a_Two, B_TwoIs short-circuited. others
Therefore, when the load is light, the power MOS transistor Q₁Only
Gate charge (capacitance present in the gate
Of the MOS transistor Q ₁And MOS tiger
Transistor Q_TwoLess than the sum of the gate charge with
Thus, the efficiency can be improved. The MOS transistor
Star Q₁And MOS transistor Q_ThreeMeans driver 4,
5 and turned on alternately.

Meanwhile, when the load exceeds a predetermined value (heavy load), because the voltage drop across the resistor R ₁ is large, the switch S
Connecting W ₁ and the switch SW ₂ is in a state shown by a dotted line. Therefore, MOS transistor Q ₂ is connected in parallel to MOS transistor Q _1, MOS transistor Q ₄
It is connected in parallel to MOS transistor Q _3. Therefore, the on-resistance of the combined MOS transistors Q ₁ and Q ₂ is reduced, and the efficiency is improved. At this time, the driver 4 of the control circuit 3 drives the gates of the MOS transistors Q ₁ and Q ₂ , and the driver 5 drives the gates of the MOS transistors Q ₃ and Q ₄ . The power MOS transistors Q ₁ and Q ₂ are connected to an n-channel power M
An OS transistor may be used. In this case, the polarities of the gate input signals of the n-channel type power MOS transistors Q ₁ and Q ₂ are opposite to those of the p-channel type.

FIG. 2 shows a circuit of a DC / DC converter according to a second embodiment of the present invention. The second embodiment is a modified example of the first embodiment. FIG.
, The control circuit 3a includes the driver 4a and the driver 5
a, the driver 4a operates in the same manner as the driver 4 in FIG. 1, and the driver 5a operates in the same manner as the driver 5 in FIG. The differential amplifiers 2a and 2b replace the differential amplifier 2 of FIG. Differential amplifier 2a amplifies the voltage of the resistor R _1, a differential amplifier 2b operates as a comparator for comparing the output with a reference voltage Vr of the differential amplifier 2a, and controls the switch SW _1, SW _2. The control circuit 3a has an output terminal 7
And the drivers 4a and 5a are pulse width modulated (PW) so as to maintain the load output at a predetermined value.
M). Others are the same as those in FIG.

[0015] Also in FIG. 2, as in FIG. 1, MOS transistor Q ₂ is MOS transistor Q when the heavy load
₁ and the MOS transistor Q ₄
Is connected in parallel to the transistor Q _3, when the light load M
Only OS transistor Q ₁ and the MOS transistor Q ₃ to operate. Therefore, the circuit of FIG. 2 has the same effect as the circuit of FIG.

FIG. 3 shows a DC / DC converter according to the third embodiment.
2 shows a circuit of a DC converter. In FIG. 3, a power MOS is connected in series between a power supply terminal 17 and an output terminal 18.
Between the source and the drain of the transistor (p-channel type MOSFET) Q _9, inductance L ₂ and the resistor R ₂ are connected in series, a load 11 is connected between the output terminal 18 and the ground point. A DC power supply is connected to the power supply terminal 17 in the same manner as the power supply terminal 6.

The control circuit 13 includes a MOS transistor (p
Channel type MOSFET) Q_Five, Q ₆, MOS transistor
Star (n-channel MOSFET) Q₇, Q₈, Switch
Switch_Three, SW_FourAnd drivers 14, 15, 16
You. MOS transistor Q₆M between source and drain of
OS transistor Q₉Connected between the source and gate of
Further, the MOS transistor Q_FiveBetween the source and drain of
MOS transistor Q₆Connected between the source and drain of
Have been. The ground point and the MOS transistor Q₉Dre
Power MOS transistor (n-channel type)
MOSFET) Q_TenConnected between the source and drain of
I have. MOS transistor Q₈Between the source and drain of
MOS transistor Q₉Connected between the gate and ground
And the MOS transistor Q₇Source Dray
MOS transistor Q₈Between source and drain of
It is connected.

The output terminal of the driver 14 is a MOS transistor.
Star Q_FiveGate and switch SW _ThreeTerminal c_ThreeConnect to
The output terminal of the driver 15 is a MOS transistor Q
₈Gate and switch SW_FourTerminal c_FourConnected to
I have. Further, the output terminal of the driver 16 is a MOS transistor.
Star Q_TenConnected to the gate. Differential amplifier 12
Is the resistance R_TwoVoltage and offset voltage V_S2And the difference voltage
Input and the output terminal of the differential amplifier 12 is a switch SW_Three
Input terminal d_ThreeAnd SW_FourInput terminal d_FourConnected to
I have. By the differential amplifier 12, the resistance R_TwoVoltage is a predetermined value
In the following cases (at light load), switch SW_Three, SW_Fourof
The connection state is indicated by a solid line (SW_ThreeTerminal a_ThreeAnd terminal b
_ThreeIs connected and SW_FourTerminal a_FourAnd terminal b_FourIs connected
State), and the resistance R_TwoVoltage exceeds the predetermined value
Time (at heavy load), switch SW_Three, SW_FourConnection
The state is indicated by the dotted line (SW_ThreeTerminal a_ThreeAnd terminal c_ThreeContact
Continued, SW_FourTerminal a_FourAnd terminal c_FourConnected
State).

The diode D ₂ has a cathode connected to the drain of the MOS transistor Q _9, the anode is grounded. Capacitor C ₃ is connected between the ground point and the power supply terminal 17, the capacitor C ₄ is connected between the ground point and the output terminal 18. The circuit connected to the gate of the power MOS transistor Q _10, even driver 16,
It may be similar to the circuit to be connected to the gate of the power MOS transistor Q _9. It is also an asynchronous type DC / DC converter by eliminating the power MOS transistor Q _10.

With the above configuration, when the load is light, the resistance R_Two
Is lower than the predetermined value, the switch SW_ThreeMO
S transistor Q₆Will not work, switch
SW _FourMOS transistor Q₇Will not work
To be. Therefore, the driver 14 is connected to the MOS transistor
TA Q_FiveDriver 15 and the MOS transistor 15
TA Q₈Only drive. Therefore, the drivers 14, 15
Since the drive loss of the device is reduced, the efficiency is increased. Note that M
OS transistor Q_FiveAnd MOS transistor Q₈Is C
Operates as a MOS and turns on alternately, and the next stage MOS
Transistor Q₉Drive. The driver 16 is a MOS transistor
Transistor Q_TenDrive.

Meanwhile, the heavy load, the voltage of the resistor R ₂ exceeds a predetermined value, MOS transistor Q ₆ is connected in parallel to the MOS transistor Q ₅ by the switch SW _3,
MOS transistor Q ₇ by the switch SW ₄ is MOS
It is connected in parallel to the transistor Q _8. Therefore, the driver 14 drives the MOS transistors Q ₅ and Q ₆ , and the driver 15 drives the MOS transistors Q ₇ and Q ₈ . The MOS transistors Q ₅ and Q ₆ and the MOS transistors Q ₇ and Q ₈ operate as CMOS and are turned on alternately to drive the next stage MOS transistor Q ₉ . Therefore, MOS transistor Q ₉ is the switching speed is increased, switching loss of the MOS transistor Q ₉ is reduced. As a result, efficiency is improved. In addition,
The driver 16 drives the MOS transistor Q _10, MO
S transistor Q ₉ and the MOS transistor Q ₁₀ is turned on alternately. For this reason, DC /
The DC converter can be operated efficiently.

[0022]

According to the DC / DC converter according to the first aspect of the present invention, when the load is large, another power MOS transistor is connected in parallel with the power MOS transistor that switches on and off between the load and the DC power supply by switching operation. Since the transistor is connected, DC / D
The C converter can be operated efficiently. Further, since the capacity of the power MOS transistor to be used is used to the maximum, the cost is reduced because there is no useless power MOS transistor. Further, the DC /
According to the DC converter, when the load is large, another MOS transistor is connected in parallel to the MOS transistor that drives the power MOS transistor that turns on and off the load and the DC power supply by the switching operation.
The DC / DC converter can be operated efficiently regardless of the magnitude of the load. Furthermore, since the capacity of the MOS transistor to be used is used to the maximum, the useless MO
Since there is no S transistor, the cost is reduced.

[Brief description of the drawings]

FIG. 1 shows a DC / D according to a first embodiment of the present invention.
It is a circuit diagram of a C converter.

FIG. 2 is a circuit diagram of a DC / DC converter according to a second embodiment.

FIG. 3 is a circuit diagram of a DC / DC converter according to a third embodiment.

FIG. 4 is a circuit diagram of a conventional example.

[Explanation of symbols]

1, 11 Load 6, 17 Power supply terminals Q ₁ , Q ₂ , Q ₉ P-channel power MOS transistors Q ₃ , Q ₄ , Q ₁₀ N-channel power MOS transistors Q ₅ , Q ₆ P-channel MOS transistors Q ₇ , Q ₈ n-channel MOS transistor R ₁ , R ₂ resistance 2, 2a, 2b differential amplifier SW ₁ , SW ₂ , SW ₃ , SW ₄ switch

Claims (2)

[Claims] 1. A DC / D which turns on and off between a load and a DC power supply by a switching MOS transistor.
A C converter, comprising: detecting means for detecting the magnitude of the load; and connecting means for connecting another MOS transistor in parallel with the MOS transistor when the detecting means detects that the load is large. Characteristic DC / DC converter. 2. A DC / D which turns on and off between a load and a DC power supply by a switching MOS transistor.
In the C converter, a detecting means for detecting the magnitude of the load, and another M parallel to a MOS transistor for driving the MOS transistor when the detecting means detects that the load is large.
A DC / DC converter comprising: a connection unit for connecting an OS transistor.