JPH117601A - Disk control device, disk drive device and computer device - Google Patents

Abstract

(57) Abstract: A disk control device capable of shortening a transient response period of a bias current supplied to a magnetoresistive element is provided. SOLUTION: A magneto-resistance effect type reading element (MR)
A low-pass filter (LPF1, LPF2) is arranged at the gate of the bias current supply transistor (M2, M) arranged between the terminals of the read element in the bias circuit (1) for DC biasing H). Bypass MOS transistors (M3, M7) are arranged in parallel with the delay elements (R1, R2) of the low-pass filter, and when the bias current is determined, the bypass MOS transistors are controlled to be on. The transient response period until the bias current is determined is shortened. The control of the bypass MOS transistor
This is performed based on control information given from outside.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a disk control device for performing read / write control of a magnetic disk, a disk drive device having the disk control device, and a computer device having the disk drive device. The present invention relates to a technique for speeding up a transition to a steady state of a bias circuit for supplying a bias current to a read element of a type.

[0002]

2. Description of the Related Art Information recorded on a magnetic disk can be read by utilizing the magnetoresistance effect, and a magnetoresistance effect type read element (hereinafter simply referred to as M) used in a read head thereof.
The resistance value of the R element changes under the influence of the magnetic field. With the bias current flowing through the MR element, the MR
When the change in the resistance value of the element changes, the voltage between the terminals of the MR head changes, and the recorded information can be read based on the change.

[0003] As an example of a document describing a method of a storage information reproducing circuit using an MR element, there is an IEEE Transac.
tions On Magnetics vol27, No.6 November 1991 (Magnet
ic Recording Channel Front-Ends).

[0004]

The present applicant has proposed a bias circuit for applying a bias current to an MR element in an earlier application (Japanese Patent Application No. 8-80863).
The bias circuit includes, for example, a pair of current source MOS transistors that receive a control voltage depending on a constant current generated by the constant current circuit at a gate and form a bias current for the MR element. The pair of current source MOS transistors are:
A first control voltage formed by a mirror circuit that reflects a current of a constant current circuit is supplied to a control terminal of one current source transistor disposed at both ends of the MR element. The control terminal of the other current source transistor is supplied with the second control voltage via a feedback circuit. The feedback circuit is constituted by a differential circuit that makes a DC differential output voltage zero. At this time, in order to secure a sufficient amount of read signals due to a change in the resistance value of the MR element, a noise component superimposed via a transistor of a current mirror circuit for forming a first control voltage or a constant current supplied from a constant current circuit. Tried to remove the noise component. For this purpose, a capacitive element is arranged at a control terminal of a current source transistor receiving a first control voltage, a noise component superimposed in a feedback loop forming a second control voltage is removed, and a frequency of the feedback loop is reduced. In order to determine the characteristics, a capacitive element was arranged at the control terminal of the current source transistor receiving the second control voltage.

However, these capacitors have several μF.
Since a relatively large capacitance is required, the capacitance element has been externally attached to a semiconductor device including the bias circuit. Therefore, it has been clarified that in a high-frequency region, the parasitic inductance component of a junction terminal or a lead wire for connecting a capacitor externally becomes so large that it cannot be neglected, and that noise characteristics deteriorate. In addition, a semiconductor device having a built-in bias circuit is arranged in the immediate vicinity of a read / write head, and there is a strong demand for miniaturization of a disk drive device. In view of this, it is difficult to secure a space for externally attaching a capacitive element. It was revealed.

Further, the capacitive element constitutes a delay component of the control voltage. Thus, when the reading operation is instructed, the transient response period until the bias current of the MR element is determined by the control voltage becomes long.
Then, it has been clarified by the present inventor that when the reading operation is instructed, the determination of the bias current of the magnetoresistive element is delayed, and the time until the actual reading becomes possible may be lengthened.

An object of the present invention is to provide a disk control device capable of reducing a noise component of a bias current applied to a magnetoresistive element.

Another object of the present invention is to provide a disk control device capable of reducing the number of parts.

Still another object of the present invention is to provide a disk control device which can promptly determine a bias current supplied to a magnetoresistive element when a read operation is instructed.

It is another object of the present invention to provide a disk drive capable of shortening a period from an instruction for a read operation to a magnetic disk to a transition to an actual read operation.

Another object of the present invention is to provide a computer device capable of realizing a high-speed information processing operation using data stored in a disk drive sending device.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0013]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application.

That is, in order to remove a noise component of a bias current in a bias circuit for DC-biasing a magnetoresistive read element, a bias current supply transistor disposed between terminals of the read element is connected to a MOS transistor.
A transistor (current source MOS transistor), and a low-pass filter is arranged at the gate of the current source MOS transistor so that a noise component is not superimposed on the bias current. The capacitive element constituting the low-pass filter is formed inside a semiconductor device in which a bias circuit is formed. This eliminates the need for externally attaching a low-pass filter capacitive element to a semiconductor device having a built-in bias circuit. Therefore, since there is no inductance component that is parasitic on a terminal or a wiring for connecting an external capacitor in the related art, a noise component superimposed on a bias current of the reading element in a high frequency region can be reduced. In the low-pass filter of the current source transistor, the combination of the value of the resistance value and the value of the capacitance value is determined so as to have a frequency characteristic capable of removing a noise component in a signal band.
Since the transistor is sufficiently large due to its properties, a combination of increasing the resistance value and decreasing the capacitance value is possible, whereby the capacitance for the low-pass filter can be built in the semiconductor device.

When the bias circuit starts forming a bias current in response to an instruction such as a data read operation, the low-pass filter constitutes a delay component with respect to the gate input signal of the current source MOS transistor. When a bypass MOS transistor is arranged in parallel with a delay element such as a resistance element of such a low-pass filter and a bias circuit is activated to initially determine a bias current or when changing a bias current, the bypass MOS transistor is turned on. Control the state. As a result, the transient response period until the bias current is determined can be shortened, and, for example, the time from when a read operation is instructed until data can be actually read can be shortened. Bypass M
A control circuit for controlling the OS transistor controls the read / write circuit based on control information given from the outside, and controls an external interface between data information read by the read / write circuit and data information to be written by the read / write circuit. Based on instructions from. That is, the control circuit gives a command to the read / write circuit in accordance with external control information for instructing a read operation or the like, and the read / write circuit receiving this command sets a predetermined value when starting the current output operation of the constant current circuit. During the period, the bypass MOS transistor is turned on, the time constant of the low-pass filter is reduced, and the determination of the DC bias current of the reading element is hastened.

As described above, the disk drive device using such a disk control device can read data at high speed because of its excellent noise resistance in a high frequency range. Further, the time from the instruction of the read operation until the data can be actually read can be shortened, and high-speed response to the instruction of the read operation can be realized. A computer device using such a disk drive device can speed up information processing using data of the disk drive device.

The bias circuit uses a positive power supply voltage and a negative power supply voltage as operating power supplies, the current source MOS transistors are arranged at both ends of the read element, and the gate electrode of one of the current source MOS transistors has the constant voltage. A first control voltage depending on a constant current generated by a current circuit is supplied, and a gate electrode of the other current source MOS transistor is provided with a constant current generated by the constant current circuit as an operating current and an output current of the reading element. A second control voltage formed by a feedback circuit for canceling a difference voltage between the divided voltage of the terminal voltage and the ground voltage is supplied, and a low-pass filter is coupled to a gate electrode of each of the current source MOS transistors. The bypass MOS transistor may be arranged in parallel with the delay element of each low-pass filter.

A disk drive device includes a disk control device, a read / write head having a write element for a magnetic disk and a magnetoresistive read element connected to a read / write circuit of the magnetic disk control device, And a positioning mechanism for the read / write head with respect to the disk.

The computer device has a processor board having a microprocessor and a disk interface controller connected to a bus mounted on a mounting board, and the disk drive device connected to the disk interface controller. The control circuit included in the device may be combined with the disk interface controller.

[0020]

FIG. 1 shows an example of a bias circuit. The bias circuit 1 shown in FIG. 1 has an M as a reading element for reading information recorded on a magnetic disk.
This is a circuit for flowing a bias current to the R element MRH.
When the resistance of the MR element MRH changes in accordance with the recorded information as the magnetic information while the bias current is flowing through the MR element MRH, the voltage between the terminals of the MR element MRH changes, and the change is amplified by the amplifier AP1. I do. As will be described later, the bias circuit 1 and the amplifier AP1 are mounted on a read / write circuit formed as a semiconductor integrated circuit. The MR element MRH is externally connected to the read / write circuit.

The bias circuit 1 has a positive power supply voltage VCC.
And the negative power supply voltage VEE as the operating power supply. At both ends of the MR element MRH, a p-channel type current source MOS transistor M2 and an n-channel type current source MOS transistor M8 are arranged. 1 is a constant current circuit, and a constant current I1 supplied from the constant current circuit 2 is an n-channel MOS transistor M4.
Flows to The MOS transistor M4 is so-called diode-connected with its drain coupled to the gate. The one current source MOS transistor M8 forms a current mirror circuit with the MOS transistor M4,
The gate of the S transistor M8 is supplied with a first control voltage VA formed depending on the constant current I1. The n-channel MOS transistors M5 and M6 are respectively connected to the MOS transistors.
The transistor M4 forms a current mirror circuit. A diode-connected p-channel MOS transistor M1 arranged in series with the MOS transistor M6 supplies a second control voltage VB depending on a current flowing through the MOS transistor M6 to the MO transistor M1.
It is supplied to the gate of the S transistor M2. The MOS transistor M2 forms a current mirror circuit with the MOS transistor M1.

An npn-type bipolar transistor Q1 forming one differential input is provided between the drain of the MOS transistor M5 and the drain of the MOS transistor M6.
Is arranged between the drain of the MOS transistor M5 and the power supply voltage VCC, and an npn-type bipolar transistor Q2 forming the other differential input is arranged. The ground voltage GND is supplied to the base of the bipolar transistor Q1. The divided voltage VFB of the voltage between the terminals of the MR element MRH is supplied to the base of the bipolar transistor Q2. The divided voltage VFB is formed by a series circuit of resistors R3 and R4.
R4 have the same resistance, and the divided voltage VFB is equal to MR
The center potential of the element MRH. The transistor M
5, Q1 and Q2 constitute a feedback circuit 3 for controlling the second control voltage VB so as to cancel the difference voltage between the divided voltage VFB of the voltage between the terminals of the MR element MRH and the ground voltage GND. As is clear from the above, the center voltage of the MR element MRH of the bias circuit 1 is equal to the ground voltage GND.
It is said. This is to prevent the potential difference between the read / write head and the magnetic disk from being formed because the potential of the magnetic disk is normally set to the ground voltage. If there is a potential difference, an undesired electric field is formed, and if the read / write head comes into contact with the magnetic disk, a current may flow to damage the head.

A low-pass filter LPF1 composed of a resistance element R1 and a capacitance element C1 is arranged at the gate of the MOS transistor M2, and a resistance element R2 and a capacitance element C2 at the gate of the MOS transistor M8. A low-pass filter LPF2 is provided. The low-pass filters LPF1 and LPF2 are controlled by the control voltages VB and VB.
A noise component superimposed on A is removed, and a current with a small noise component flows through the MOS transistors M2 and M8.

A p-channel type bypass MOS transistor M3 is arranged in series with the resistance element R1, and an n-channel type bypass MOS transistor M7 is arranged in series with the resistance element R2. VSW1 and VSW2 are switch control signals for the MOS transistors M3 and M7.

The operation of the above bias circuit will be described. For example, when the current IMR is to flow through the MR element MRH, I1
= IMR / n is supplied from the constant current circuit 2. By setting the size ratio between the transistors M4 and M8 to 1: n, the current IMR flows through the transistor M8.

The low-pass filter LPF2 removes noise included in the constant current I1 from the constant current circuit 2 and noise from the MOS transistor M4, and can suppress superposition of noise on the current flowing through the transistor M8. The combination of the values of the resistance element R2 and the capacitance element C2 may be set so that the band of the low-pass filter LPF2 is lower than the read signal frequency and noise can be sufficiently removed in the read signal frequency band. In order to minimize the generation of noise in the transistor M8 itself, the substrate resistance of the MOS transistor M8 may be reduced.

The MOS transistors M5 and M6 have M
A current that depends on the constant current I1 flows through the OS transistor M4. For example, when the size ratio between the transistors M1 and M2 is 1: n, IM4, IM5, and IM6 are currents flowing through M4, M5, and M6, and assuming that IM4 = I1, (IM5 / 2) + IM6 = IM4 The sizes of the transistors M5 and M6 may be determined so that
For example, M4: M5: M6 may be set to 1: 0.8: 0.6.

The low-pass filter LPF1 removes noise contained in the gate signal of the MOS transistor M2, and can suppress superposition of noise on the current flowing through the transistor M2. To minimize the generation of noise in the transistor M2 itself, the MOS transistor M2
The substrate resistance of No. 2 may be reduced.

When the current flowing through the transistor M2 becomes smaller than the current IMR, the center potential of the MR element MRH (that is, the divided voltage VFB) becomes lower than the ground voltage GND. At this time, the base voltage of the transistor Q1 becomes higher than the base voltage of the transistor Q2, and a large amount of current flows through the transistor M1. As a result, the current flowing through the transistor M2 increases, and the center potential VFB of the MR element MRH increases. On the other hand, when the current flowing through transistor M2 is larger than current IMR, the current flowing through transistor Q1 decreases, and the current flowing through transistor M2 decreases accordingly, and the central potential VFB of MR element MRH drops. . Due to this feedback operation, a current equal to the current IMR flowing through the transistor M8 flows through the transistor M2, and the center potential VFB of the MR element MRH tends to become the ground voltage GND.

The amount of feedback by the feedback circuit 3 is determined by the size ratio between the transistors M5 and M6. A current depending on the constant current I1 flows through the transistor M6, and the current flows through the transistor M1. The transistor M5 tries to supply a current corresponding to the base voltage difference between the transistors Q1 and Q2 to the transistor M1 via the differential pair including the transistors Q1 and Q2. Control voltage V
A part of the level of B is fixedly determined by the current flowing through the MOS transistors M1 and M6, and the necessary remaining level is generated by the feedback circuit 3. When the size ratio between the transistors M1 and M2 is 1: n, the current IM1 flowing through the transistor M1 becomes IQ1 in a steady state.
+ IM6 = I1. Therefore, the bias voltage can be stabilized without requiring a very large amplification degree in the feedback circuit 3.

The capacitive element constituting the low-pass filter is formed inside the semiconductor device in which the bias circuit 1 is formed. This eliminates the need to externally attach the low-pass filter capacitance elements C1 and C2 to the semiconductor device having the bias circuit 1 built-in. Therefore, since there is no inductance component that is parasitic on a terminal or a wiring for connecting an external capacitor in the related art, a noise component superimposed on a bias current of the reading element in a high frequency region can be reduced. The combination of the resistance value and the capacitance value of the low-pass filters LPF1 and LPF2 of the current source transistors is determined so as to have a frequency characteristic capable of removing a noise component in a signal band, but the input of the current source MOS transistors M2 and M8 is determined. Since the impedance is sufficiently large due to the nature of the MOS transistor, a combination of increasing the resistance value and decreasing the capacitance value is possible, whereby the capacitances C1 and C2 for the low-pass filter can be built in the semiconductor device.

When the bias circuit 1 starts forming a bias current in response to an instruction such as a read operation, the low-pass filters LPF1 and LPF2 constitute a delay component with respect to the gate input signals of the current source MOS transistors M2 and M8. become. Delay elements of such low-pass filters LPF1, LPF2, for example, resistance elements R1, R
2, the bypass MOS transistors M3 and M7 are arranged in parallel, and the bias circuit 1 is activated to initially determine the bias current, or when the bias current is changed, the bypass MOS transistors M3 and M7 are turned on. . This makes it possible to shorten a transient response period from when a read operation is instructed to when the bias voltage is determined. As described above, the noise can be removed by using the low-pass filter with the built-in capacitor without delaying the transient response.

FIG. 2 shows an example of the circuit 4 for generating the switch signals VSW1 and VSW2 based on the control voltages VA and VB. A p-channel MOS transistor M10 is connected to a connection node between the p-channel MOS transistor M9 having its gate receiving the control voltage VB and the resistance element R5.
And a CMOS inverter constituted by an n-channel MOS transistor M11 and a p-channel MOS
A transistor M12 and a CMOS inverter constituted by an n-channel MOS transistor M13 are connected in series, and these circuits are connected to a power supply voltage VCC and a ground voltage G.
ND is an operation power supply. Similarly, a CMOS inverter constituted by a p-channel MOS transistor M15 and an n-channel MOS transistor M16 is connected to a connection node between an n-channel MOS transistor M14 receiving a control voltage VA at its gate and a resistance element R7, CMOS constituted by MOS transistor M17 and n-channel MOS transistor M18
Inverters are connected in series, and these circuits are connected to ground voltage G
ND and the power supply voltage VEE are used as operation power supplies.

When the bias circuit is in an inactive state (a state where the constant current I1 is not supplied from the constant current circuit 2),
The control voltage VA is at a low level, and the control voltage VB is at a high level. In response to this, the switch control signal VS
W2 is set to a high level, and the bypass MOS transistor M7 is turned on. Further, the switch control signal VSW1 is set to low level, and the bypass MOS transistor M3 is turned on.

When the constant current I1 is supplied to activate the bias circuit, the gate level of the MOS transistor M4, that is, the level of the control voltage VA is increased. Thereby, the MOS transistors M15, M1
6, the MOS transistor M15 is turned on, and the MOS transistor M16 is turned off. Then, after a delay time determined by the time constant of the capacitance element C4 and the resistance element R8 has elapsed, the switch control signal VSW2 is inverted from the high level to the low level, and the bypass MOS transistor M7 is turned off. At this time, the resistance element R8 and the point element C4
Is determined by the MOS transistor M
The bypass MOS transistor M7 is set to be turned off after the gate level of the transistor 8 (the current of the transistor M8) reaches a steady state. The same applies to the switch control signal VSW1, and after the level of the control voltage VB starts to decrease, the above-described element C3 and the resistor R
6, after the delay time determined by the switch control signal SW
1 is changed from low level to high level. Thus, the bypass transistors M3 and M7 can be automatically switch-controlled in accordance with a transient response period from when the operation of the bias circuit is started to when the conductance of the current source transistors M2 and M8 reaches a steady state. .

FIG. 3 shows an example of the read / write circuit 10 having the bias circuit 2. The read / write circuit 10 is not particularly limited, but the bias circuit 1, the constant current circuit 2, the read preamplifier and write driver 11, the read amplifier 12, the write circuit 13, and the controller 14 are formed on one semiconductor substrate. Semiconductor integrated circuits. In the figure, the switch control signals VSW1 and VSW2 are generated by the controller 14 and do not employ the circuit of FIG.

FIG. 2 shows one MR element MRH as a representative, but in the example of FIG. 3, a plurality of MR elements MRH can be connected to external terminals MR0X, MR0Y to MRnX, MRnY. Accordingly, an external terminal W to which a plurality of write inductance elements INDH can be externally attached.
0X, W0Y to WnX, WnY.

The read preamplifier and write driver 11 are provided with external terminals MR0X and MRO for each MR element MRH.
For each of R0Y to MRnX and MRnY, the preamplifier AP1 described with reference to FIG.
A write driver is provided for each of X, W0Y to WnX, WnY. One set of MR element MRH and inductance element IND
H constitutes a read / write head for one magnetic disk. The bias circuit 2 is connected to each of the amplifiers AP1
The output of the amplifier AP1 whose operation is selected is further amplified by the read amplifier 12 and output to the outside from the output terminals OUT1 and OUT2. Write data is input to the write circuit 13 from the input terminals IN1 and IN2. The data input to the write circuit 13 is supplied to a write driver whose operation is selected,
The write driver drives the inductance element INDH.

The controller 14 has control functions of mode select, head select, current control, and serial interface control.

SDEN is an enable signal for serial data, SCLK is a synchronous clock signal for serial transfer, SD
ATA is serial data, CS is a chip select signal of the read / write circuit, and R / W is a read / write signal for selecting a read mode or a write mode for the read / write circuit. The serial interface control function controls serial data transfer using these signals.

The current amount control function controls the amount of current to the constant current circuit 2 according to control data supplied through a serial interface. The constant current circuit 2 is constituted by, for example, a D / A conversion circuit, and outputs a constant current according to data set by a current control function.

The head select function selectively controls the operation of the read / write head for disk access according to the control data supplied via the serial interface.

The operation mode of the read / write circuit for disk access is not particularly limited, but is roughly classified into an idle mode, a read mode, and a write mode. In the idle mode, the current output operation of the constant current circuit 2 is stopped. The read mode refers to a disk read operation using a read / write head, and the write mode refers to a disk write operation using a read / write head.

When switching to the read mode, switching the read / write head, and changing the bias current set value for the constant current circuit 2, the controller 14 changes the switch control signals VSW1 and VSW2 to low level and high level for a certain period. To turn on the bypass MOS transistors M3 and M7 during that period. When such switching of operation or change of bias current is performed,
When the state of the bias circuit 1 is changed, the transient response operation is performed. At this time, as the MOS transistors M3 and M7 are forcibly turned on for a certain period, the transient response operation can be sped up as described above. Therefore, it is possible to immediately shift from the idle state to the read operation. Also, when changing the disk to be accessed or changing the bias current of the bias circuit 1, the state change of the bias circuit 1 is speeded up, and the interruption period of the read operation can be shortened as much as possible. This makes it possible to speed up disk access as a whole.
The ON operation periods of the MOS transistors M3 and M7 may be made different depending on the operation mode. For example, when the operation is expected to have a relatively long transient response period such as when the read mode is changed from the idle state, the on-operation period of the bypass MOS transistors M3 and M7 is lengthened. As described above, if it is considered that the transient response period is relatively short and it is sufficient to consider only the noise at the time of switching, the on-operation period of the bypass MOS transistors M3 and M7 may be shortened.

FIG. 4 is a block diagram of a disk drive device 20 using the read / write circuit 10. As shown in FIG.
The disk drive device shown in FIG. 4 is a hard disk device (also referred to as a fixed disk device), and has a structure in which a disk portion as a storage medium and a head assembly are fixed.
Numeral 0 has a plurality of magnetic disks 21 arranged concentrically and fixed to a common spindle, and the spindle is rotationally driven by a disk motor 22. The read / write head 23 has an MR element MRH and an inductance element IND.
H pairs are provided for each magnetic disk. FIG. 4 typically shows a pair of an MR element MRH and an inductance element INDH. The read / write head 23 is supported by a head actuator 24. Disk motor 2
2 and the tracking control for the head actuator 24 are performed by the servo circuit 27. Although not particularly limited, the magnetic disk 21 and the disk motor 2
2 constitutes a disk assembly. The read / write head 23, the head actuator 24, and the read / write circuit 10 constitute a head assembly.

The filtering process and the decoding process for the signal read from the read / write circuit 10 and the coding process for the write data through the read / write circuit 10 are performed by a signal processing circuit 25 such as a digital signal processor integrated into a semiconductor integrated circuit. Do.

The lead dry circuit 10, the signal processing circuit 2
5 and the servo circuit 27 are controlled by the control circuit 26. The control circuit 26 includes a CPU (not shown).
(Central Processing Unit), RAM (Random Acc
ess Memory), RO that stores CPU operation program
M (Read Only Memory), serial interface, parallel interface, D / A converter, etc. For example, the control circuit 26 is constituted by a single-chip microcomputer. The control circuit 26 is a circuit that controls the entire disk drive device in accordance with a command supplied from the external host device 30, controls the setting of control information and data transfer to the signal processing device 25 and the read / write circuit 10, It also controls the transfer of control information and data to and from the host device.

In this disk drive device 20,
The control of the bypass MOS transistors M3 and M7 is as follows.
Based on an instruction from the control circuit 26. For example, the control circuit 26 gives a read command to the read / write circuit 10 in accordance with control information instructing a read operation from the host device 30, and the read / write circuit 10 which has received this read command outputs the current output of the constant current circuit 2. When the operation is started, the bypass MOS transistor M
(3) Turn on M7 to reduce the time constant of the low-pass filter, thereby speeding up the establishment of the DC bias current in the bias circuit 1. Similarly, when the bias current value is changed according to the control information from the host device 30, the read / write circuit 10 performs the bypass MOS transistor M for a certain period of time as part of the operation in response to the command.
3, M7 is turned on. Switching of the head is performed by the control circuit 26 in accordance with the cylinder number of the magnetic disk to be accessed.
6 to the read / write circuit 10, the read / write circuit 10 turns on the bypass MOS transistors M3 and M7 for a certain period of time, as described above, as part of the operation in response to the command.

FIG. 5 shows an example of the head assembly. The read / write head 23 and the read / write circuit 10 are mounted on a beam 240 of a head actuator. At this time, the capacitance elements C1,
Since C2 has a built-in chip and does not require external attachment, the number of components to be mounted on the beam 240 is reduced and the weight is reduced.
The inertia of the head actuator can be reduced, which can contribute to speeding up of seek operation and the like.

FIG. 6 is a block diagram of a computer device 40 having the disk drive device 20 mounted thereon. In the computer device 40, the microprocessor 50 includes, but is not limited to, a system bus 51.
Through Peripheral Component Interconnec
t) It is connected to the bus controller 52. The PC
An internal bus (PCI bus) 53 conforming to the PCI bus standard is connected to the I bus controller 52. An IDE interface controller 54 and other interface controllers 55 are connected to the internal bus 53 as peripheral controllers. The magnetic disk drive device 20 is coupled to the IDE (Integrated Device Electronics) interface controller 54 via an interface cable. The ID
The E interface controller 54 also controls the interface between the magnetic disk drive device 20 and the internal bus 53. The microprocessor 50, PCI bus controller 52, internal bus 53, IDE interface controller 54, and other interface controllers 55 constitute a processor board 41. Note that the other interface controller 55 is, for example, a Centronics interface controller that performs a parallel interface with a graphic accelerator, a printer, or the like. 4 corresponds to FIG. 6, the host device 30 in FIG. 4 corresponds to the processor board 41.

Since the bias circuit 1 has excellent noise resistance in a high frequency range, the disk drive 2 using the read / write circuit 10 including the bias circuit 1
0 enables high-speed reading of data. Further, the time from the instruction of the read operation until the data can be actually read can be shortened, and high-speed response to the instruction of the read operation can be realized. Therefore, the computer device 40 using the disk drive device can speed up the information processing using the data of the disk drive device 20.

Although the invention made by the inventor has been specifically described based on the embodiment, it is needless to say that the present invention is not limited to the embodiment and can be variously modified without departing from the gist of the invention. No.

For example, the differential transistors Q1 and Q2 of the bias circuit 1 can be constituted by MOS transistors. The other and the current mirror ratio in the circuit are not limited to the above example, and can be changed as appropriate.

[0054]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, it is not necessary to externally attach a low-pass filter capacitive element to a semiconductor device having a built-in bias circuit. Therefore, since there is no inductance component that is parasitic on a terminal or a wiring for connecting an external capacitor in the related art, a noise component superimposed on a bias current of the reading element in a high frequency region can be reduced.

The transient response period until the bias current is determined can be shortened.

Because of the excellent noise resistance in the high frequency range, a disk drive using such a disk controller can read data at high speed. Furthermore,
It is possible to shorten the time from the instruction of the read operation until the data can be actually read, and to realize a high-speed response to the instruction of the read operation. A computer device using such a disk drive device can speed up information processing using data of the disk drive device.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an example of a bias circuit for flowing a bias current to an MR element.

FIG. 2 is a circuit diagram illustrating an example of a circuit that generates a switch control signal for a bypass MOS transistor.

FIG. 3 is a block diagram illustrating an example of a semiconductor integrated circuit read / write circuit having the bias circuit.

FIG. 4 is a block diagram of a disk drive device using the read / write circuit of FIG. 3;

FIG. 5 is an explanatory diagram illustrating an example of a head assembly.

FIG. 6 is a block diagram of a computer device equipped with the disk drive device of FIG. 4;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Bias circuit 2 Constant current circuit I1 Constant current 3 Feedback circuit M2, M3 MRH MR element LPF1, LPF2 Low-pass filter C1, C2 Capacitance element R1, R2 Resistance element M3, M7 Bypass MOS transistor VSW1, VSW2 Switch control signal VA, VB control Voltage 10 read / write circuit 20 magnetic disk drive device 21 magnetic disk 23 read / write head 25 signal processing circuit 26 control circuit 40 computer device 41 processor board 50 microprocessor 54 IDE interface controller

Claims (5)

[Claims] 1. A read / write circuit for reading information from a magnetic recording medium by applying a direct current bias to a magnetoresistive read element and driving a write element to write information to the magnetic recording medium; A control circuit that controls the read / write circuit based on the read / write circuit and performs an external interface control between data information read by the read / write circuit and data information to be written by the read / write circuit, The circuit includes a bias circuit for direct-current biasing the read element, wherein the bias circuit receives a control voltage generated depending on a constant current generated by a constant current circuit at a gate to form the bias current. Source MOS transistor and the gate voltage of the current source MOS transistor. And a bypass MOS transistor connected in parallel to the delay element of the low-pass filter, wherein the control circuit gives a command to the read / write circuit according to external control information, and receives the command. When the read / write circuit starts the current output operation of the constant current circuit or changes the output current, the bypass M
A disk control device for turning on an OS transistor for a predetermined period. 2. The bias circuit uses a positive power supply voltage and a negative power supply voltage as an operation power supply, and the current source MOS transistor is disposed at both ends of the read element. A first control voltage dependent on a constant current generated by the constant current circuit is supplied, and a gate electrode of the other current source MOS transistor has a current dependent on a constant current generated by the constant current circuit; A second control voltage formed by a divided voltage of the voltage between the terminals of the reading element and a feedback current corresponding to a difference voltage between a ground voltage and a low-pass filter is supplied to a gate electrode of each of the current source MOS transistors. And the bypass MOS transistor is connected in parallel with the delay element of each low-pass filter. 2. The disk control device according to claim 1, wherein: 3. A bias circuit comprising: a first power supply voltage; a first power supply voltage; a first power supply voltage; a negative power supply voltage;
MOS transistor, a second MOS transistor in which the constant current is mirrored at a predetermined ratio, and a second MOS transistor.
A third MOS transistor in a diode connection form connected in series to the S transistor; a fourth MOS transistor in which a current flowing through the third MOS transistor is mirrored at a predetermined ratio and coupled to the other end of the read element; Wherein the first and fourth MOS transistors output current corresponding to a difference between an intermediate voltage and a ground voltage of the read element to the second MOS transistor and the third MOS transistor. And a feedback circuit for supplying the signal to the connection point of
Are the current source MOS transistors, a low-pass filter is coupled to the gate electrodes of the first and fourth MOS transistors, and the bypass MOS transistor is arranged in parallel with the delay element of each low-pass filter. The disk control device according to claim 1, wherein the disk control device is a disk control device. 4. A read / write circuit of the magnetic disk control device, comprising: the disk control device according to claim 1; and a write element for a magnetic disk and a magnetoresistive read element. A disk drive device further comprising: a read / write head to be connected; and a mechanism for positioning the read / write head with respect to the magnetic disk. 5. A processor board having a microprocessor and a disk interface controller connected to a bus mounted on a mounting board, and the disk drive device according to claim 4 connected to the disk interface controller. A computer device, wherein the control circuit included in a disk drive device is coupled to the disk interface controller.