JPH117794A - Error correction circuit and semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain an error correction circuit whose circuit constitution is simple and by which the bit error of an arbitrary memory cell can be corrected. SOLUTION: When data is to be stored, e.g. a memory cell unit 100 is selected, and word data D7 to D0 are stored. At this time, the same data Dk [where (k) represents any integer out of 0 to 7] is stored in nonvolatile memory transistors TM1k, TM2k. When data is to be read out, word lines WL0, WL1 are set to '1' by an address decoder ADR0, and cell selection transistors TW1k, TW2k are turned on simultaneously. Memory transistors TM's are turned on when stored data is '0', and they are turned off when the data is '1'. The TM's are degraded in such a way that the stored data is changed surely from '0' to '1'. Data in which stored data in transistors TM1k, TM2k are ANDed are outputted to a bit line BL0k. As a result, even when any TM is degraded, read-out data can be corrected.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an error correction circuit and a semiconductor memory device having an error correction function, and more particularly to an EEP.
The present invention relates to an error correction circuit capable of correcting a bit error due to deterioration of a memory cell of an electrically writable nonvolatile semiconductor memory device such as a ROM.

[0002]

2. Description of the Related Art Conventionally, such a semiconductor memory device has, for example, at least four error correction bits (parity bits) for eight data bits and one error bit out of eight bits. Some have been provided with an error correction circuit that can correct only. Also, Japanese Patent Application Laid-Open No. 1-13
There was one disclosed in Japanese Patent No. 3300. In this method, data is read from the same memory cell a plurality of times by changing the sense voltage, and a bit error is corrected by an error correction circuit based on the value of the data read a plurality of times and one parity bit.

[0003]

However, in the above-mentioned conventional semiconductor memory device, an error correction circuit must be provided in a region other than the memory cell array, and the circuit configuration of the error correction circuit is complicated. When attempting to change a semiconductor memory device having no correction function to a semiconductor memory device having an error correction function, there is a problem that a significant design change is required. There is also a problem that it takes time to read. Only one bit in one word can be corrected, and two bits in the same word can be corrected.
When a bit error occurs, there is a problem that error correction cannot be performed. Further, in the memory cell array, a region (redundant region) of a memory cell (redundant memory cell) for performing error correction and a region (non-redundant region) of a memory cell (non-redundant memory cell) for which error correction is not performed are set according to applications. There was a problem that it was not possible.

An object of the present invention is to solve such a conventional problem and to provide an error correction circuit and a semiconductor memory device which can correct a bit error of an arbitrary memory cell with a simple circuit configuration. And It is still another object of the present invention to provide a semiconductor memory device capable of programmably changing a redundant region and a non-redundant region of a memory cell array according to a use.

[0005]

In order to achieve the above object, an error correction circuit according to the present invention stores the same data in first to Nth (N is an integer of 2 or more) memory cells, 1
To N-number of data stored in the N-th memory cell are output as error correction data.

An error correction circuit according to a second aspect of the present invention is the first aspect of the invention.
, The data output electrodes of the first to Nth memory cells are connected in common, and the N data are simultaneously output from the first to Nth memory cells, whereby the AN
It is characterized by generating data in which D or OR is taken.

The error correction circuit according to the third aspect is the second aspect.
, Wherein the memory cell is a nonvolatile memory cell capable of electrically erasing and writing data.

An error correction circuit according to a fourth aspect of the present invention is the third aspect of the invention.
Wherein the memory cell includes the first to N-th memory cells, a bit line, and first to N-th word lines which are simultaneously at a first level, and the k-th (k is any one of 1 to N) (Integer) memory cell includes a k-th cell selection transistor and a k-th memory transistor, and the k-th cell selection transistor is connected to the gate connected to the k-th word line and to the bit line. A transistor having a first electrode and a second electrode, the transistor being turned on when the word line is at a first level, and being turned off when the word line is at a second level. A control gate to which a sense voltage is input, a floating gate for storing data, a first electrode connected to the second electrode of the k-th cell selection transistor, Characterized in that it is a non-volatile memory transistor having a second electrode connected to the ground.

According to a fifth aspect of the present invention, there is provided a semiconductor memory device including a memory cell array in which a plurality of error correction circuits having first to Nth (N is an integer of 2 or more) memory cells are formed. At this time, one error correction circuit is selected for one input data, the data is stored in the error correction circuit, and the error correction circuit storing the data is selected when reading the data. Then, the data is read from the error correction circuit, and the selected error correction circuit stores the same input data in the first to Nth memory cells at the time of data storage. , And outputs data obtained by ANDing or ORing the N pieces of data stored in the first to Nth memory cells as error correction data.

According to a sixth aspect of the present invention, in the semiconductor memory device according to the fifth aspect, the error correction circuit connects the data output electrodes of the first to Nth memory cells to the same bit line, and By simultaneously outputting the N data from the Nth memory cell, the AND or OR
Is generated on the bit line.

According to a seventh aspect of the present invention, in the semiconductor memory device according to the sixth aspect, the memory cell is a nonvolatile memory cell capable of electrically erasing and writing data.

The semiconductor memory device according to claim 8 is the semiconductor memory device according to claim 7, wherein the plurality of error correction circuits, a bit line provided for each error correction circuit, and a first line provided for each error correction circuit. To the N-th word line and word selecting means for selecting any of the plurality of error correction circuits by simultaneously setting the first to N-th word lines to the first level. The k-th (k is any integer from 1 to N) memory cell of the circuit includes a k-th cell selection transistor and a k-th memory transistor, and the k-th cell selection transistor is the k-th cell selection transistor. A gate connected to a word line; a first electrode connected to the bit line; and a second electrode. The gate is turned on when the word line is at a first level. A k-th memory transistor connected to a control gate to which a sense voltage is input, a floating gate for storing data, and the second electrode of the k-th cell selection transistor. A non-volatile memory transistor having a first electrode and a second electrode connected to an array ground.

According to a ninth aspect of the present invention, in the semiconductor memory device, a memory cell array in which first to Nth (N is an integer of 2 or more) redundant memory cells and a non-redundant memory cell forming an error correction circuit are formed. And a bit line to which the data output electrodes of the first to Nth redundant memory cells and the data output electrodes of the non-redundant memory cells are connected in common. Selecting the error correction circuit or the non-redundant memory cell, storing the data in the error correction circuit or the non-redundant memory cell,
Further, at the time of data reading, an error correction circuit or a non-redundant memory cell storing the data is selected, and the data is read from the error correction circuit or the non-redundant memory cell. The same input data is stored in the first to Nth redundant memory cells, and at the time of data reading, AND or O of N data stored in the first to Nth redundant memory cells is performed.
Data obtained by taking R is generated as error correction data on the bit line.

According to a tenth aspect of the present invention, in the semiconductor memory device according to the ninth aspect, the memory cell is a nonvolatile memory cell capable of electrically erasing and writing data.

The semiconductor memory device according to claim 11 is the semiconductor memory device according to claim 10, wherein the error correction circuit, the non-redundant memory cell, the bit line, and the first to An Nth word line, a (N + 1) th word line provided for the non-redundant memory cell, and word selecting means for selecting the first to (N + 1) th word lines. (K is 1 to N
) Is a kth cell selection transistor and a kth memory transistor, and the non-redundant memory cell is a (N + 1) th cell selection transistor and a (N + 1) th cell selection transistor. The i-th (i is an integer from 1 to (N + 1)) cell select transistor, comprising a memory transistor, a gate connected to the i-th word line, and a i-th cell select transistor connected to the bit line. A transistor having one electrode and a second electrode, being turned on when the word line is at a first level, and turned off when the word line is at a second level; A control gate to which a voltage is input, a floating gate for storing data, and a second electrode connected to the second electrode of the kth cell selection transistor. A non-volatile memory transistor having a first electrode and a second electrode connected to an array ground, wherein the word selecting means simultaneously sets the first to Nth word lines to a first level. And the non-redundant memory cell is selected by setting the (N + 1) th word line to the first level.

According to a twelfth aspect of the present invention, there is provided a semiconductor memory device, comprising: a memory cell array in which first to Nth (N is an integer of 2 or more) memory cells are formed; A data output electrode including a bit line connected in common, and when the external setting is the first setting,
The kth (where n is an integer from 1 to N) memory cells are selected as non-redundant memory cells from the Mth to Mth memory cells, and when the external setting is the second setting, the first to Nth memory cells are selected. Memory cells are simultaneously selected as redundant memory cells, and at the time of data storage, input data is stored in an error correction circuit composed of the redundant memory cells or the non-redundant memory cells. The data is read from the error correction circuit or the non-redundant memory cell storing the data, and the error correction circuit stores the same input data in the first to Nth redundant memory cells during data storage; When reading data, the first to Nth
Of M data stored in the redundant memory cell
Data obtained by taking D or OR is generated as error correction data on the bit line.

According to a thirteenth aspect of the present invention, in the semiconductor memory device according to the twelfth aspect, the memory cell is a nonvolatile memory cell capable of electrically erasing and writing data.

A semiconductor memory device according to a fourteenth aspect is the semiconductor memory device according to the thirteenth aspect, wherein the first to Nth memory cells, the bit lines, the first to Nth word lines, and the first and second memory cells are provided. And word selecting means for selecting the first to Nth word lines in accordance with the setting of (k).
) Of the memory cell includes a k-th cell selection transistor and a k-th memory transistor, and the k-th cell selection transistor has a gate connected to the k-th word line. A first electrode connected to the bit line, and a second electrode, the transistor being turned on when the word line is at a first level, and turned off when the word line is at a second level.
The k-th memory transistor has a control gate to which a sense voltage is input, a floating gate for storing data, a first electrode connected to the second electrode of the k-th cell selection transistor, and an array ground. A non-volatile memory transistor having a second electrode connected thereto, wherein the word selecting means sets the k-th word line to a first level during a first setting, thereby setting the k-th word line to a first level. A memory cell is selected, and at the time of the second setting, the first to Nth word lines are simultaneously set to the first level to simultaneously select the first to Nth memory cells. .

According to a fifteenth aspect of the present invention, there is provided a semiconductor memory device comprising:
A memory cell array in which first to Mth (M is an integer of 3 or more) memory cells are formed; and a bit line to which data output electrodes of the first to Mth memory cells are commonly connected. Is set to the first setting, the p-th (p is an integer from 1 to M) memory cell is selected as a non-redundant memory cell from the first to M-th memory cells, and an external setting is performed. Is the second setting, whether the first to qth memory cells (q is any integer from 2 to (M−1)) are simultaneously selected as redundant memory cells from the first to Mth memory cells. Or the r-th (r is an integer from (q + 1) to M) memory cell is selected as a non-redundant memory cell, and when the external setting is the third setting,
To M-th memory cells are simultaneously selected as redundant memory cells constituting an error correction circuit, and when data is stored, input data is stored in the error correction circuit including the redundant memory cells or the non-redundant memory cell. Also, at the time of data reading, the data is read from the error correction circuit or the non-redundant memory cell storing the data, and the error correction circuit stores the same input data in the redundant memory cell at the time of data storage. When storing and reading data, data obtained by ANDing or ORing the M data stored in the redundant memory cell is generated on the bit line as error correction data. .

A semiconductor memory device according to a sixteenth aspect is the semiconductor memory device according to the fifteenth aspect, wherein the memory cell is a nonvolatile memory cell capable of electrically erasing and writing data.

A semiconductor memory device according to a seventeenth aspect is the semiconductor memory device according to the sixteenth aspect, wherein the first to Mth memory cells, the bit lines, the first to Mth word lines, and the first to third Mth memory cells are provided. Word selecting means for selecting the first to Mth word lines in accordance with the setting of
S-th memory cell includes an s-th cell selection transistor and an s-th memory transistor, wherein the s-th cell selection transistor has a gate connected to the s-th word line. A first electrode connected to the bit line, and a second electrode, the transistor being turned on when the word line is at a first level, and turned off when the word line is at a second level.
The s-th memory transistor has a control gate to which a sense voltage is input, a floating gate for storing data, a first electrode connected to the second electrode of the k-th cell selection transistor, and an array ground. A non-volatile memory transistor having a second electrode connected thereto, wherein the word selecting means sets the p-th word line to a first level at the time of a first setting, thereby setting the p-th word line to a first level. By selecting a memory cell and, at the time of the second setting, simultaneously selecting the first to q-th word lines or selecting the r-th word line, By selecting the memory cells at the same time or selecting the r-th memory cell, and setting the first to M-th word lines to the first level at the time of the third setting. And selects the serial first to the memory cells of the M simultaneously.

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Before describing a first embodiment of the present invention, an EEPROM having no error correction function will be described. Figure 1 shows an EEPROM without error correction function
FIG. 3 is a diagram showing the configuration of FIG. Here, the address data is 2
8-bit (1 byte) word data with bit configuration
Configuration. The address bits of the address data are A1,
A0, and the word bits of the word data are D7, D6,.
D0. Address bit A0 is data for column selection, and address bit A1 is data for row selection. FIG. 1 shows only a circuit for performing a data read operation, and does not illustrate a circuit for performing a data storage operation.

The EEPROM shown in FIG. 1 has a memory cell array 5, two address buses AB0 and AB1, a row decode unit 2, a column decode unit 3, a sense amplifier unit 4, and eight data buses DB0, DB1 ... DB7 (D
B1 to DB6 are not shown). Address bus A
Address bit A0 is input to B0, and address bit A1 is input to address bus AB1.

The row decode unit 2 includes an address bit A1
To select the word line WL0 or WL1 in accordance with the address decoder A, and has address decoders ADR0 and ADR1. The output terminal of the address decoder ADR0 is connected to the word line WL0, and the output terminal of the address decoder ADR1 is connected to the word line WL1.

The column decode unit 3 has an address bit A
The bit lines BL00, BL01,.
Alternatively, bit lines BL10, BL11... BL17 are selected, and address decoders ADC0 and ADC0 are selected.
DC1 and column select transistors TC00, TC01
... TC07, TC10, TC11 ... TC17 (TC01
TC06 and TC11... TC16 are not shown).

In the memory cell array 5, memory cell units 500, 501, 510, and 511 having the same configuration and having a data storage capacity of 8 bits are arranged in a matrix. FIG. 1 shows a memory cell unit 500,
Only the internal configuration of 501 is shown. The memory cell unit 500 includes cell selection transistors TW0, TW1,.
TW7 (TW1 to TW6 are not shown), memory transistors TM0, TM1,..., TM7 (TM1 to TM6 are not shown), and a sense word select transistor TSW. The memory transistor TM is a transistor that has a floating gate and a control gate, and stores 1-bit data by injecting charges into or extracting charges from the floating gate. Memory transistor TMk
(K is an integer from 0 to 7) is a word bit Dk
Is stored.

In the memory cell unit 500, the gate electrodes of the cell selection transistors TW0 to TW7 and the sense word selection transistor TSW are all connected to the word line WL0. Cell selection transistor T
The drain electrode of Wk is connected to the bit line BL0k. The drain electrode of the sense word select transistor TSW is connected to the sense line SL0. The source electrode of the cell selection transistor TWk is connected to the drain electrode of the memory transistor TMk. The source electrode of the sense word select transistor TSW is connected to the commonly connected control gate electrodes of the memory transistors TM0 to TM7. The source electrode of the memory transistor TM is connected to the array ground AG.

In memory cell unit 500, a pair of cell select transistor TWk and memory transistor TMk form a memory cell. Therefore, the memory cell unit 500 has eight memory cells. Cell select transistor TWk and memory transistor TMk
Are stored in memory transistor TMk when memory cell unit 500 is selected in a data storage operation, and are stored in memory transistor TMk when memory cell unit 500 is selected in a data read operation. The word bit Dk stored in TMk is output to bit line BL0k.

The memory cell units 501, 510, 51
0 has the same internal configuration as that of the memory cell unit 500. However, the memory cell units 501, 510, 51
0 and the memory cell unit 500 are different in the following points.
In the memory cell units 501 and 511, the drain electrode of the cell selection transistor TWk is connected to the bit line BL1k, and the drain electrode of the sense word selection transistor TSW is connected to the sense line SL1. Also, memory cell units 110 and 11
In 1, the gate electrode of the cell selection transistor TW and the gate electrode of the sense word selection transistor TSW are connected to the word line WL1.

In the memory cell array 5, the row (word line WL) and the column (bit line BL) are selected according to the address data A0 and A1, respectively, so that the memory cell units 500, 501 and 51 are selected.
0 or 510 is selected. For example, when the address bits A0 are "0" and A1 is "1", the row selection signal R1 from the address decoder ADR1 becomes "1", and the column selection transistors TC00 to TC07 are turned on.
Thereby, the memory cell unit 510 is selected, and the cell selection transistors TW0 to TW7 and the sense word selection transistor TW of the memory cell unit 510 are selected.
SW turns on.

The sense amplifier unit 4 includes a memory cell array 5
, The word bits D0 to D7 stored in the selected memory cell unit are detected as "1" or "0", and these word bits D0 to D7 are transferred to the data bus DB.
0 to DB7, and eight sense amplifiers SA0, SA1,.
SA6 is not shown). The EEPR shown in FIG.
The OM further selects a word line WL during a data storage operation, applies a predetermined voltage to the selected word line WL, and performs a data storage operation during a data storage operation.
A column control circuit for applying a predetermined voltage to a selected bit line BL, and a sense control circuit for applying a predetermined sense voltage to a sense line SL corresponding to the selected bit line BL during data storage and read operations ,
A main control circuit for controlling a data storage operation and a data read operation in accordance with an external command;

First Embodiment FIG. 2 is a diagram showing a configuration of an EEPROM according to a first embodiment of the present invention. This EEPROM has an error correction function for stored data. Here, the address data has a 2-bit configuration, and the word data has an 8-bit (1 byte) configuration. Address bits are A0 and A1, and word bits are D0, D1... D7. Address bit A0 is bit data for column selection, and address bit A1 is bit data for row selection. FIG.
2 and the same reference numerals in FIG. 2 indicate the same components.

An EEPROM according to the first embodiment shown in FIG.
Is a memory cell array 1 and two address buses AB.
0, AB1, a row decode unit 2, a column decode unit 3, a sense amplifier unit 4, and eight data buses DB0 to DB0.
DB7 (DB1 to DB6 are not shown). Address bit A0 is input to address bus AB0, and address bit A1 is input to address bus AB1. Data bus DBk (k is an integer from 0 to 7)
Is a bus that handles word bits Dk. FIG. 2 shows only a circuit for performing a data read operation, and does not illustrate a circuit for performing a data storage operation.

Row decoder 2 has address decoders ADR0 and ADR1 whose input terminals are both connected to address bus AB1. The output terminals of the address decoder ADR0 are word lines WL0 and WL1.
And the output terminal of the address decoder ADR1 is connected to word lines WL2 and WL3.
The address decoder ADR0 outputs a row selection signal R0 according to the input address bit A1, and the address decoder ADR1 outputs a row selection signal R1 according to the input address bit A1. Address bit A
When 1 is "0", the row selection signal R0 is "1", R1
Becomes "0", and the word lines WL0 and WL1 are selected. When the address bit A1 is "0", the row selection signal R0 is "0", R1 is "1", and the word lines WL2 and WL3 are selected.

The column decoder 3 has address decoders ADC0 and ADC1 whose input terminals are both connected to the address bus AB1, and column select transistors TC00 to TC07, TC10 to TC17 (TC01).
To TC06 and TC11 to TC16 are not shown). The address decoder ADC0 outputs a column selection signal C0 according to the input address bit A1, and the address decoder ADC1 outputs a column selection signal C1 according to the input address bit A1. When the address bit A1 is "0", the column selection signal C0
Is "1" and C1 is "0". Address bit A1
Is "1", the column selection signal C0 is "0", C1
Becomes "1".

Column select transistors TC00 to TC0
7 are commonly connected, and this common gate electrode is connected to the output terminal of the address decoder ADC0. In addition, column selection transistors TC10 to TC1
The gate electrodes 7 are commonly connected, and this common gate electrode is connected to the output terminal of the address decoder ADC1. Column selection transistor TC0k (k is 0 to 7)
Source electrode of the bit line BL
0k, and the source electrode of the column select transistor TC1k is connected to the end of the bit line BL1k. The drain electrode of the column selection transistor TC0k and the drain electrode of the column selection transistor TC1k are commonly connected. The column selection transistors TC00 to TC07 and TC10 to TC17 turn on when the column selection signal input to the common gate electrode is "1" and turn off when the column selection signal is "0". Address bit A1
Is "0" (the column selection signal C0 is "1", C1
Is “0”), the column selection transistors TC00 to TC00
TC07 is ON, TC10 to TC17 are OFF,
Bit lines BL00 to BL07 are selected. When the address bit A1 is "1" (the column selection signal C0
Is "0" and C1 is "1"), the column selection transistors TC00 to TC07 are OFF, and TC10 to TC17.
Becomes ON, and the bit lines BL10 to BL17 are selected.

In the memory cell array 1, memory cell units 100, 101, 110, and 111 having the same configuration and having a data storage capacity of 16 bits are arranged in a matrix. FIG. 2 shows the memory cell unit 100.
Is shown only in FIG. Memory cell unit 1
00 denotes cell selection transistors TW10, TW11.
W17, TW20, TW21... TW27 (TW11 to TW27)
W16 and TW21 to TW26 are not shown), and memory transistors TM10, TM11... TM17, TM2
0, TM21 ... TM27 (TM11 to TM16 and T
M21 to M26 are not shown), and sense word select transistors TSW1 and TSW2.

In the memory cell unit 100, the gate electrodes of the cell selection transistors TW10 to TW17 and the sense word selection transistor TSW1 are commonly connected to a word line WL0, and the gate electrodes of the cell selection transistors TW20 to TW27 and the sense word selection transistor TSW2. Are commonly connected to a word line WL1. Cell select transistors TW1k and TW1k
The drain electrode of W2k is commonly connected to the bit line BL0k. Sense word select transistor TSW
1 and TSW2 are connected to the sense line SL
0 is commonly connected. Cell selection transistor TW1
k is connected to the drain electrode of the memory transistor TM1k, and the cell selection transistor TW
The 2k source electrode is connected to the drain electrode of the memory transistor TM2k. The source electrode of the sense word select transistor TSW1 is the memory transistor TM
10 to TM17 are connected to the commonly connected control gate electrodes, and the source electrode of the sense word select transistor TSW2 is connected to the memory transistor TM20.
To TM27 which are commonly connected to the control gate electrode. The source electrodes of the memory transistors TM are commonly connected to an array ground AG. The array ground AG is separated from the EEPROM ground. The cell selection transistor TW and the sense word selection transistor TSW are connected to the address bit A1.
Is "0" (the row selection signal R0 is "1"), that is, when the word lines WL0 and WL1 are selected, O
N, the address bit A1 becomes “1” (the row selection signal R0
Is OFF when is "0").

In the memory cell unit 100, the paired cell select transistor TW1k and the memory transistor TM1k constitute a memory cell MC1k, and the paired cell select transistor TW2k and the memory transistor TM2k constitute a memory cell MC2k. Therefore, the memory cell unit 100 has 16 memory cells MC1
0 to MC17 and MC20 to MC27.

Here, the above-mentioned cell selection transistor TW
And a memory cell MC including the memory transistor TM will be described. FIG. 3 is a diagram showing a detailed configuration of the memory cell MC. In FIG. 3, the cell selection transistor T
W has a gate electrode 61 connected to the word line WL in FIG. 2, a drain electrode 62 connected to the bit line BL in FIG. 2, and a source electrode 63. The memory transistor TM has a floating gate 71 and a floating gate 71 shown in FIG.
The control gate 72 connected to the sense line SL via the sense word select transistor TSW, the drain electrode 73 connected to the source electrode 63 of the cell select transistor TW, and the source electrode 74 connected to the array ground of FIG. And Memory transistor T
M is a transistor that stores 1-bit data by injecting charges into or extracting charges from the floating gate 71, and is a non-volatile memory transistor that can electrically rewrite stored data. is there. Memory transistor TM
Is, for example, a floating gate 71 of polysilicon.
A polysilicon control gate 72 is formed on the semiconductor device via an insulating film, and a tunnel oxide film is formed between the lower surface of the floating gate 71 and the channel surface of the transistor. Such a structure is called FLOTOX.
(Floating tunnel oxide) type.

In the memory transistor TM, injecting charges into the floating gate 71 is referred to as "writing data", and extracting charges from the floating gate 71 is referred to as "erasing data". Here, data writing is associated with data “0”, and data erasing is associated with data “1”. That is, data “0” is stored in the memory transistor TM (data of the memory transistor TM is rewritten to “0”).
This means that data is written to the memory transistor TM, and that the data “1” is stored in the memory transistor TM (the data of the memory transistor TM is rewritten to “1”). Means to erase.

When data "0" is stored in the memory transistor TM by writing data, for example,
The word line WL (gate electrode 61) and sense line SL (control gate 71) are set to 20 [V], and the bit line BL (drain electrode 62) and array ground AG (source electrode 74) are set to 0 [V]. At this time, since the cell selection transistor TW is turned on, the drain electrode 73 becomes 0 [V]. As a result, charges are injected from the source and drain of the memory transistor TM into the floating gate 71.

When data "1" is stored in the memory transistor TM by erasing the data, for example, the word line WL and the bit line BL are set to 20 bits.
[V], the sense line SL is set to 0 [V], and the array ground AG is opened. At this time, the cell selection transistor T
Since W is turned ON, the drain electrode 73 of the memory transistor TM becomes 20 [V]. As a result, charges are extracted from the floating gate 71 to the drain. The memory transistor TM turns on when the voltage applied to the control gate 72 is equal to or lower than the threshold voltage, and turns off when the voltage is equal to or higher than the threshold voltage. Memory transistor TM
, The threshold voltage Vt0 when data is written is the threshold voltage Vt0 when data is erased.
It is lower than 1.

When data stored in the memory transistor TM is read, for example, the word line WL is
[V], the sense voltage (the voltage of the sense line SL) is 2
[V], the array ground AG is set to 0 [V]. The sense voltage is set to be a voltage between the threshold voltages Vt0 and Vt1. At this time, the cell selection transistor TW turns on. The memory transistor TM is turned on when the storage data is “0”, and remains off when the storage data is “1”. Therefore, the bit line BL is
When the storage data is "0", it becomes 0 [V], and when the storage data is "1", it becomes open. That is, in the data reading, the storage data “1” and the O
FF and the stored data “0” and the transistor T
Corresponds to ON of W.

In memory cell unit 100, cell selection transistor TW1k and memory transistor TW
The memory cell MC1k composed of M1k and the memory cell MC2k composed of the cell selection transistor TW2k and the memory transistor TM2k are connected to the error correction circuit E of the present invention.
Ck. Therefore, the memory cell unit 100
Has eight error correction circuits EC0, EC1... EC7. The memory cells MC1k and MC2k are connected to the same bit line BL0k, and when the memory cell unit 100 is selected in the data storage operation, the word bit Dk is changed to the memory transistors TM1k and TM2k.
k, and when the memory cell unit 100 is selected in the data read operation, the word bit Dk stored in the memory transistor TM1k is stored.
And the word bit Dk stored in the memory transistor TM2k are both output to the bit line BL0k. That is, the same data is stored, and the stored data is simultaneously output to the same bit line.

Memory cell units 101, 110, 11
0 has the same internal configuration as the memory cell unit 100. However, the memory cell units 101, 110, 110 differ from the memory cell unit 100 in connection with the word line WL and the like in the following points. In the memory cell units 101 and 111, the cell selection transistor T
The drain electrodes of W1k and TW2k are bit lines B
L1k, and the drain electrode of the sense word select transistor TSW is connected to the sense line SL1. Also, the memory cell units 110 and 111
, The gate electrodes of the cell selection transistors TW10 to TW17 and the sense word selection transistor TSW
1 is commonly connected to the word line WL2, and the gate electrodes of the cell selection transistors TW20 to TW27 and the sense word selection transistor TSW2
Are commonly connected to a word line WL3.

In the memory cell array 1, the row (word line WL) and the column (bit line BL) are selected according to the address data A0 and A1, respectively, so that the memory cell units 100, 101 and 11 are selected.
Either 0 or 110 is selected. For example, address bit A0 is at logic level "0", and A1 is at logic level "
1 ", the row selection signal R1 from the address decoder ADR1 becomes" 1 "and the column selection transistor T
When C00 to TC07 are turned on, the memory cell unit 110 is selected, and the cell selection transistors TW10 to TW17 and TW20 to TW20 to TW20 of the memory cell unit 110 are selected.
TW27 and sense word select transistor TSW
1. TSW2 turns ON.

The sense amplifier unit 4 has eight sense amplifiers SA0 to SA7 (SA1 to SA6 are not shown) having the same configuration. The sense amplifier SAk (k is an integer from 0 to 7) determines whether the word bit Dk is “1”.
0 "is detected, and the input terminal IN
Is connected to the common drain electrode of the column selection transistors TC0k and TC1k, and has an output terminal OUT
Are connected to the data bus DBk.

FIG. 4 is a diagram showing the internal configuration of the sense amplifier SA. In FIG. 4, the sense amplifier SA includes a resistor R provided between the input terminal IN and the positive power supply VDD, and a resistor R provided in series between the input terminal IN and the output terminal OUT.
It consists of two inverters INV1 and INV2. The sense amplifier SA outputs an “L” level when the detection data is “0”, and outputs an “H” level when the detection data is “1”. When data is erased from the memory cell transistor TM (data “1” is stored in TM), the memory cell transistor TM is OFF and the bit line BL is open, so that the input terminal IN is connected to the resistor R
, And is pulled up to the power supply VDD, and becomes “H” level. When data is written to the memory cell transistor TM (data “0” is stored in TM), the memory cell transistor TM is ON and the bit line BL becomes 0 [V]. , A current flows through the memory cell, the input terminal IN becomes lower than the threshold voltage of the inverter INV2 due to the resistance R, and the output terminal OUT becomes “L” level.

That is, E of the first embodiment shown in FIG.
The EPROM is different from the EEPROM of FIG. 1 in that two word lines WL are connected to one address decoder ADR of the row decoding unit 2 so that two word lines WL can be simultaneously selected. The memory cell units 100 and 101 of the memory cell array 1
110 and 111 are connected to two word lines WL selected at the same time, respectively, and are constituted by an error correction circuit EC composed of two memory cells connected to the same bit line. Hereinafter, the memory cells forming the error correction circuit, such as the memory cells of the memory cell units 100, 101, 110, and 111, are referred to as redundant memory cells. The memory cell units 100, 101,
Since the error correction circuits EC of 110 and 111 are composed of 2-bit redundant memory cells, they are referred to as 2-bit redundant error correction circuits. Also, the memory cell units 100, 101, 11
A memory cell unit (memory for storing one-word input data) which is constituted by an error correction circuit like 0 and 111 and stores 1-bit input data in a plurality of (two in this case) redundant memory cells. Cell unit) is referred to as a redundant memory cell unit. On the other hand, EE in FIG.
PROM memory cell units 500, 501, 51
Memory cell units that store 1-bit input data in one memory cell, such as 0 and 511, are referred to as non-redundant memory cell units. Also, the memory cell unit 500,
Memory cells that do not form an error correction circuit, such as the memory cells 501, 510, and 511, are referred to as non-redundant memory cells.

Here, the principle of error correction of stored data in the error correction circuit EC of the present invention will be described. If the data read from the memory cell becomes erroneous due to a memory cell failure, the data stored as "0" is replaced by "0".
There is a case where the data is read as "1" and a case where the data stored as "1" is read as "0", which is a problem only in that the memory cell outputs the data stored as "0" as "1". When data is read out or when the data stored as "1" has a problem such that it is output only as "0", the 1-bit input data is stored in a plurality of memory cells and the data is read out. By using the data obtained by ANDing or ORing the data stored in these memory cells as the read data, it is possible to correct the error in the read data due to the failure of the memory cell.
It is extremely unlikely that a failure occurs in all of the plurality of memory cells. Even if a failure occurs in any of the plurality of memory cells storing the same data, AND or AND of the storage data of each of the plurality of memory cells is performed. This is because the ORed data becomes the same as the storage data of the normal memory cell, and is the inverted data of the data of the memory cell in which a failure has occurred. For example, in the case where a memory cell which causes a problem only to output data stored as "0" as "1" is used, if the storage data of each of the plurality of memory cells is ANDed, any one of Even if a failure occurs in the memory cell, correct data can be read. The memory cell MC shown in FIG.
A problem occurs only in that data stored as "1" is output as "1", and data stored as "1" is output as "0".
There is no problem such that the output is performed as the output.

The problem in the memory cell shown in FIG. 3 is that the control gate 71 of the memory transistor TM
This is caused only by the loss of the charge injected into the device. That is, a defect in the memory cell MC occurs when the memory transistor TM changes from a data write state (a state storing “0”) to a data erase state (a state storing “1”), and vice versa. Does not occur. When reading data, the memory transistor TM storing "0" is turned on and the memory transistor TM storing "1" is turned off. Therefore, the output terminals (a) of the plurality of memory cells MC forming the error correction circuit ( By commonly connecting (connecting to the same bit line BL) the rain terminal 62 of the cell selection transistor TW, data obtained by ANDing the storage data of each of the plurality of memory cells MC is transferred to the common connection terminal (the above-described common connection terminal). Bit line BL). Memory cell M
The probability of a data error occurring in an error correction circuit configured using two C's is one thousandth of that in the case where the memory cell shown in FIG. 3 is used alone.

Next, the EEP of the first embodiment shown in FIG.
The operation of the ROM will be described. First, the data storage operation will be described. One of the memory cell units is selected based on the address data A1 and A0, and all the memory transistors T of the selected memory cell unit are selected.
M data is erased, and then data buses DB7 to DB
The word data D7 to D0 input from 0 are written to the memory transistor TM. That is, charges are injected into the floating gates 71 of all the memory transistors TM, and thereafter, charges are extracted from the control gate 71 of the memory transistor TM corresponding to the word bit Dk of “1”. Word bit Dk is stored in two memory transistors TM1k and TM2k. For example,
When the address bit A1 is "0" and A0 is "0", the memory cell unit 100 is selected as follows, and the input word data D7 to D0 are stored in the memory cell 100.

The address decoder ADC0 outputs the column selection signal C0 of "1", and the column selection transistor TC
00 to TC07 are turned on, and bit lines BL00 to BL07 are turned on.
07 is selected. The word lines WL0 and WL1 are selected by a row control circuit (not shown), and the memory transistors TM are connected to these word lines WL0 and WL1.
A predetermined voltage (the voltage described above with reference to FIG. 3) for erasing data is applied. The sense control circuit (not shown) selects the sense line SL0. Selected bit lines BL00-BL07, word line WL
0, WL1, and a sense line SL0, a predetermined voltage (the voltage described above in FIG. 3) for erasing data of the memory transistor TM is applied by a column selection circuit, a row control circuit, and a sense control circuit (not shown). As a result, the cell selection transistors TW10 to TW17 and TW20 to TW27 of the memory cell unit 100 and the sense word selection transistors TSW1 and TSW2 are turned on, and the memory transistor TM10 of the memory cell unit 100 is turned on.
To TM17 and TM20 to TM27 from the floating gate 71 (memory cell unit 1).
“1” is stored in all the memory transistors TM of 00). Next, the row control circuit and the sense control circuit apply a predetermined voltage (the voltage described above with reference to FIG. 3) for writing data to the memory transistor TM to the word lines WL0 and WL1 and the sense line SL0. In addition, the column control circuit applies a predetermined voltage (the voltage described above in the description of FIG. 3) for writing data to the memory transistor TM to the bit line BLk corresponding to the word bit Dk of “1”. For example, the word bit D7
When D4 is "0" and D3 to D0 are "1", a voltage for writing data is applied to the bit lines BL07 to BL04. Thereby, the memory cell unit 10
0 memory transistors TM17 to TM14, TM27
To the floating gate 71 of TM24 ("0" is stored in these memory transistors TM of the memory cell unit 100). As described above, the memory cells MC17 to MC1 of the memory cell unit 100
4, “0” is stored in MC27 to MC24, and MC13
"1" is stored in .about.MC10 and MC23 to MC20. That is, the same data Dk is stored in the memory cells MC1k and MC2k forming the error correction circuit ECk. The data storage operation when another memory cell unit is selected is the same as described above.

Next, the data read operation will be described. One of the memory cell units is selected based on the address data A1 and A0, and the word data D7 to D0 stored in the selected memory cell unit are read. For example, if the address bit A1 is "0" and A0 is "
0 ", the memory cell unit 100 is selected as follows, and the word data D7 to D0 stored in the memory cell unit 100 are transferred to the data bus DB.
7 to DB0.

The address decoder ADR0 outputs a row selection signal R0 of "1", and the word lines WL0 and WL0 are output.
1 is selected, and the cell selection transistors TW10 to TW17, TW20 to TW27,
When the sense word select transistors TSW1 and TSW2 are O
N. Further, the address decoder ADC0 outputs the column selection signal C0 of "1", and the column selection transistor TC
00 to TC07 are turned on, and bit lines BL00 to BL07 are turned on.
07 is selected. Also, the sense line S is controlled by the control circuit.
L0 is selected, and a sense line voltage is applied to the sense line SL0. As described above in the description of FIG. 3, the sense line voltage is, for example, 2 [V]. Further, 0 [V] is applied to the array ground AG as described above in the description of FIG. As a result, in the memory cell unit 100, the memory transistor TM storing "0" is turned on, and the memory transistor TM storing "1" is kept off. Memory cell transistors TM17 to TM of memory cell unit 100
14, "0" is stored in TM27 to TM24, and TM1
Assuming that "1" is stored in TM3 to TM10 and TM23 to TM20, the memory transistors TM17 to TM17
M14 and TM27 to TM24 are turned ON. As a result, the sense amplifier SA7 is connected to the bit lines BL07 to BL04.
A current flows from the input terminals IN of .about.SA4, and the sense amplifiers SA7 to SA4 become "0" as word bits D7 to D4.
Is detected. Also, the bit lines BL03 to BL00 are released, no current flows through them, and the sense amplifier SA
3 to SA0 detect "1" as word bits D3 to D0. The sense amplifiers SA7 to SA0 transfer the detected word bits D7 to D0 to the data buses DB7 to DB0, respectively.
Output to That is, when the memory transistor TM is normal, the memory transistor T storing "0"
M1k and TM2k are both turned on, and the sense amplifier S
Ak detects "0". Further, both the memory transistors TM1k and TM2k storing "1" remain OFF, and the sense amplifier SAk detects "1".

Here, it is assumed that, in one of the memory transistors TM1k and TM2k storing "0", for example, the memory transistor TM17, charge is removed from the floating gate 71, and the stored data changes to "1". (As described above, the memory transistor TM
A defect occurs only so that the stored data "0" becomes "1"). At this time, the memory transistor TM17 is turned off.
F, but TM27, which constitutes the error correction circuit EC7 together with TM17, normally turns on.
A current normally flows from the sense amplifier SA7 to the bit line BL07, and the sense amplifier SA7 outputs the correct data.
0 "is detected. The sense amplifier SA7 performs an AND operation on the data stored in the memory transistors TM17 and TM27.
This means that data having the value D is detected, which means that correct data can be read. That is, the same data Dk is stored in the memory cells MC1k and MC2k, and data obtained by ANDing the data stored in the memory cells MC1k and MC2k is used as read data, whereby the memory transistors TM1k and T2
Even if a failure occurs in any of M2k, correct data stored in the normal memory transistor TM can be read. The memory transistors TM1k and TM2
A means for storing the same data in k does not need to be specially provided. For example, word lines W0 and W1 may be connected to the same address decoder ADR0 so that memory cells MC1k and MC2k are simultaneously selected. A above
Means for generating the ND data is the memory cell MC
This is the same bit line BLk to which the data output electrodes of 1k and MC2k are connected, and does not need to be specially provided.

As described above, according to the first embodiment, the same data is stored in a plurality of memory cells, and when data is read, the AND of each of the data stored in the plurality of memory cells is changed. By using the read data as the read data, the error rate of the memory cell becomes extremely low. In an EEPROM having no error correction function, the word lines of a plurality of memory cells are simultaneously set to "1". Error correction is possible with a very simple circuit configuration of connection.

Second Embodiment If the entire area of the memory cell array is a 2-bit redundant area as in the first embodiment, the data storage capacity of the memory cell array is twice as large as that of the EEPROM of FIG. Increase. Further, if the area is a 3-bit redundant area, it is required three times. Usually, a low error rate is often required only for a specific area of the memory cell array. In the second embodiment, an error correction circuit is provided in a specific area of a memory cell array as a redundant area and an error correction circuit is provided in this area, and the other area is set as a non-redundant area. It is characterized in that the error rate can be reduced.

FIG. 5 shows an EEPR according to a second embodiment of the present invention.
It is a figure showing composition of OM. Here, the address data has a 3-bit configuration, and the word data has an 8-bit configuration.
Address bits are A2, A1, and A0, and word bits are D7, D6,. Address bit A0 is bit data for selecting a column.
2. A1 is bit data for row selection. still,
In FIG. 5 and FIG. 2, the same reference numerals denote the same components.

The EEPROM of the second embodiment shown in FIG.
Is a memory cell array 6 and three address buses AB.
0, AB1, AB2, a row decode unit 7, a column decode unit 3, a sense amplifier unit 4, and eight data buses DB0 to DB7 (DB1 to DB6 are not shown). Address bit A0 is input to address bus AB0, and address bit A1 is input to address bus AB1. Address bus AB2 has address bits A2
Is entered. Note that FIG. 5 shows only a circuit for performing a data read operation, and does not illustrate a circuit for performing a data storage operation.

The row decoder 7 has address decoders ADR2, ADR3, ADR4, and ADR5 whose first input terminals are commonly connected to an address bus AB1 and whose second input terminals are commonly connected to an address bus AB2. Have. The output terminal of address decoder ADR2 is connected to word lines WL0 and WL1, the output terminal of address decoder ADR3 is connected to word line WL2, the output terminal of address decoder ADR4 is connected to word line WL3, and the output terminal of address decoder ADR5. Are connected to the word line WL4. The address decoders ADR2 to ADR5 supply row selection signals R0, R0 in response to the input address bits A2, A1, respectively.
1, R2 and R3 are output.

FIG. 6 shows address decoders ADR2 to ADR.
5 is a diagram showing an internal configuration of ADR2, FIG.
(B) is ADR3, (c) is ADR4, (d) is ADR
5 are shown. ADR2 is connected to inverter INV3,
It has an INV4 and an AND gate AND1, and outputs a row selection signal R0. The first input terminal of AND1 has I
Address bit A1 is input via NV3, and AND
The address bit A2 is input to the first second input terminal via INV4. ADR3 is the inverter INV5
And an AND gate AND2, and a row selection signal R1
Is output. An address bit A1 is input to a first input terminal of AND2, and I2 is input to a second input terminal of AND2.
Address bit A2 is input via NV5. AD
R4 has an inverter INV6 and an AND gate AND3.
And outputs a row selection signal R2. A first input terminal of AND3 has an address bit A1 via INV6.
Is input, and an address bit A2 is input to a second input terminal of the AND3. ADR5 is AND gate AN
D4, and outputs a row selection signal R3. AND4
The address bit A1 is input to the first input terminal of
The address bit A2 is input to a second input terminal of the AND4. When the address bits A2 and A1 are "0, 0", the row selection signal R0 is "1", R2 to R4 are "0", and the word lines WL0 and WL1 are selected.
Similarly, when A2 and A1 are "0, 1", only R1 becomes "1", and the word line WL2 is selected. A
When 2, A1 is "1, 0", only R2 becomes "1", and the word line WL3 is selected. A2, A1
Is "1, 1", only R3 becomes "1", and the word line WL4 is selected.

Returning to FIG. 5, the memory cell array 6 has redundant memory cell units 100 and 101 of the same configuration each having a data capacity of 16 bits, and non-redundant memory cell units 5 of the same configuration having a data capacity of 8 bits.
10, 511, 520, 521, 530, and 531 are arranged in a matrix. FIG. 5 shows only the internal configuration of the memory cell unit 100. The redundant memory cell units 100 and 101 are the same as the redundant memory cell units of the same reference numerals shown in FIG. The non-redundant memory cell units 510 and 511 are the same as the non-redundant memory cell units of the same reference numerals shown in FIG. The gate electrodes of the eight cell selection transistors and the gate electrodes of the cell selection transistors in the non-redundant memory cell units 520 and 521 are connected to the word line WL2, and are connected to the eight cell selection transistors in the non-redundant memory cell units 530 and 531. The gate electrode and the gate electrode of the cell selection transistor are connected to the word line WL3. The non-redundant memory cell unit 52
0, 530, the drain electrode of the cell selection transistor TWk is connected to the bit line BL0k,
The drains of the cell selection transistors TWk in the non-redundant memory cell units 521 and 531 are connected to the bit line BL1k.

That is, the EE of the second embodiment shown in FIG.
The PROM divides the memory cell array 6 into a redundant area and a non-redundant area, and the redundant memory cell unit 11
0 and 111 are provided, and non-redundant memory units 510, 511, 520, 521, 530, and 531 are provided in the non-redundant area.
EEPRO of the first embodiment.
This is different from M (see FIG. 2) in which the entire area of the memory cell array 1 is a redundant area. Word line W
To selectively select L0 and WL1, WL2, WL3, WL4, the address bits for column selection are set to 2 bits, an address bus AB2 is provided, and the row decode unit 7 can decode 2-bit address data. Like that.

Next, the operation of the EEPROM according to the second embodiment of the present invention shown in FIG. 5 will be described. First, the data read operation will be described. Address data A2, A1, A
0, one of the memory cell units is selected, and the word data D7 to D0 stored in the selected memory cell unit are read.

Address data A2, A1, A0 = “0,
When it is 0, 0 ", the redundant memory cell unit 100 is selected as follows. Address data A
2. Since A1 = "0,0", the address decoder ADR
In 2, the two input terminals of the AND gate AND1 both become "1", and the row selection signal R0 becomes "1". One of the two input terminals of the AND gates AND2 to AND4 of the address decoders ADR3 to ADR5 is "
0 ", and the row selection signals R1 to R3 become" 0 ".
As a result, the word lines WL0 and WL1 are selected. Since the address data A0 is "0", the address decoder ADC0 outputs a "1" column selection signal C0, and the column selection transistors TC00 to TC07 output O.
N, and the bit lines BL00 to BL are selected. The subsequent data read operation is the same as in the first embodiment, and two memory cells MC1k and MC1k constituting an error correction circuit ECk (k is any positive number from 0 to 7)
Data obtained by ANDing the respective data stored in 2k is read as word data Dk. When the address data A2, A1, A0 = "0, 0, 1", the redundant memory cell unit 100 is selected. The operation of reading data from the redundant memory cell unit 101 is the same as the operation of reading data from the redundant memory cell unit 100.

The address data A2, A1, A0
When "0, 1, 0", the non-redundant memory cell unit 510 is selected as follows. Since the address data A2, A1 = "0, 1", in the address decoder ADR3, the two input terminals of the AND gate AND2 both become "1" and the row selection signal R1 becomes "1".
1 ". Address decoders ADR2, ADR4, A
One of the two input terminals of the AND gates AND1, AND3, and AND4 of DR5 becomes "0", and the row selection signals R0, R2, R3 become "0". As a result, the word line WL2 is selected. Address data A0
Since "0", the bit lines BL00 to BL07 are selected. The subsequent data read operation is performed by the EE of FIG.
Similar to the PROM, the non-redundant memory cell unit 51
The data stored in the 0 memory cell transistor TMk is read as word data Dk. Address data A2, A1, A0 = “0, 1, 1”, “1,
0,0 "," 1,0,0 "," 1,1,0 "," 1,
1, 0 ", the non-redundant memory cell unit 51
0, 511, 520, 521, 530, and 531 are selected, respectively. The redundant memory cell units 100, 1
01 is the same as that of the first embodiment, and the non-redundant memory cell units 100 and 101
Are the same as in the first embodiment, and the non-redundant memory cell units 510 and 51
The data storage operation in 1, 520, 521, 530, 531 is the same as in the EEPROM of FIG.

3-bit address data A2, A1, A
On the other hand, when the entire area of the memory cell array is a redundant area as in the first embodiment, 16 bytes of memory cells are required in the memory cell array. However, addresses A2, A1, A0 = "0, 0, 0", "0,
The redundant memory cell units 100 and 101 are arranged with only the two areas 0, 1 "as the redundant areas, the error rate of these two areas is reduced, and the other areas are set as the non-redundant areas. 511, 520, 5
In the case of the second embodiment shown in FIG. 5 in which 21, 530, and 531 are arranged, the memory cell array can be composed of 10-byte memory cells.

As described above, according to the second embodiment, by dividing the memory cell array into a redundant region and a non-redundant region, an increase in chip area can be prevented, and a reduction in error rate can be achieved. Further, a memory cell array including a redundant region and a non-redundant region can be easily realized only by changing the connection so that a plurality of word lines corresponding to a plurality of memory cells desired to be a redundant region are simultaneously selected.

Similarly, the specific area of the memory cell array requiring extremely security can be a 3-byte redundant area or a 4-byte redundant area.

Third Embodiment In the second embodiment, since the redundant area in the memory cell array is predetermined, the redundant area cannot be changed depending on the application. Also, since the number of redundant bits (the number of memory cells constituting one error correction circuit) is fixed,
When the error rate is further reduced (for example, 3-bit redundancy)
Cannot be changed to The third embodiment is characterized in that the above-mentioned problem is solved by controlling the address decoding of the row selection in a programmable manner.

FIG. 7 shows an EEPR according to a third embodiment of the present invention.
It is a figure showing composition of OM. Address bit A0 is bit data for selecting a column.
2. A1 is bit data for row selection. still,
7 and FIG. 2 or FIG. 5 indicate the same components.

An EEPROM according to the third embodiment shown in FIG.
Is a memory cell array 8 and three address buses AB.
0, AB1, AB2, a row decode unit 9, a column decode unit 3, a sense amplifier unit 4, and eight data buses DB0 to DB7 (DB1 to DB6 are not shown). Note that FIG. 7 shows only a circuit for performing a data read operation, and does not illustrate a circuit for performing a data storage operation.

The row decoder 9 comprises a decoder control circuit DC and address decoders ADR6, ADR7,
ADR8. Decoder control circuit DC
Outputs control signals E1, E2, E3 of "0" or "1" according to the setting from the outside. Here, “0” and “L” level are associated, and “1” and “H”
Make the levels correspond.

Address bits A2 and A1 are respectively input to two input terminals of the address decoder ADR6, and an output terminal of the ADR6 is connected to the word line WL0. The ADR 6 outputs a row selection signal R0. The three input terminals of the address decoder ADR7 are:
Address bits A2, A1, a row selection signal R0, and a control signal E1 are input, and an output terminal of ADR7 is connected to word line WL1. This ADR
7 outputs a row selection signal R1. Address decoder A
The six input terminals of DR8 have address bits A2, A2
1, row selection signals R0, R1, control signal E2,
E3 is input, and the output terminal of ADR8 is connected to word line WL2. The ADR 8 outputs a row selection signal R2.

FIG. 8 shows address decoders ADR6 to ADR.
8A and 8B are diagrams showing the internal configuration of ADR6, FIG.
(B) shows ADR7, and (c) shows ADR8. The address decoder ADR6 is connected to the inverter INV
7, an INV8 and an AND gate AND5. A
An address bit A1 is input to a first input terminal of ND5 via INV7, and an address bit A2 is input to a second input terminal of AND5 via INV8.

The address decoder ADR7 includes inverters INV9 and INV10 and AND gates AND6 to AN6.
D8 and an OR gate OR1. The first of AND6
The address bit A1 is input to the input terminal of
The address bit A2 is input to the second input terminal 6 via INV9. A low selection signal R1 is input to a first input terminal of AND7, and a control signal E1 is input to a second input terminal of AND7. A control signal E1 is input to a first input terminal of AND8 via INV10, and a second input terminal of AND8 is AND6.
Output terminal. The two input terminals of OR1 are connected to the output terminals of AND7 and AND8, respectively.

The address decoder ADR8 includes inverters INV11-INV13 and AND gates AND9-A.
ND15 and an OR gate OR2. An address bit A1 is input to a first input terminal of AND9 via INV11, and an address bit A2 is input to a second input terminal of AND9. The control signal E3 is input to a first input terminal of the AND10, and the control signal E2 is input to the second input terminal of the AND10 via the INV13. A control signal E3 is input to a first input terminal of AND11 via INV12,
The control signal E2 is input to the second input terminal. The control signal E3 is input to the first input terminal of the AND12 via the INV12, and the control signal E2 is input to the second input terminal via the INV13. The first input terminal of the AND 13 has a row selection signal R1
And the second input terminal of AND13 is AND10
Output terminal. A row selection signal R0 is input to a first input terminal of the AND 14, and a second input terminal of the AND 14 is connected to an output terminal of the AND 11. A first input terminal of AND15 is connected to an output terminal of AND9, and a second input terminal of AND15 is connected to AN15.
It is connected to the output terminal of D12. The three input terminals of OR2 are connected to the output terminals of AND13, AND14, and AND15, respectively.

The address decoders ADR6 to ADR8
Performs different operations according to the settings of the control signals E1 to E3. Control signals E1, E2, E3 = "
L, L, L "are set as first settings. E1, E2,
E3 = “H, L, L”, “L, H, L” or “L,
L, H ", as the second setting. E1, E2, E
The operation when 3 = “H, H, L” or “H, L, H” is the third setting. In the first setting, one of the word lines WL0 to WL2 is selected according to the address bits A2 and A1. At the time of the second setting, two of the three word lines are simultaneously selected according to the address bits A2 and A1. For example, E1, E2, E3
= ”L, H, L”, the word lines WL0 and WL
2 are simultaneously selected. At the time of the third setting, three word lines are simultaneously selected according to the address bits A2 and A1.

Returning to FIG. 7, in the memory cell array 8, memory cell units 800 and 801 having the same configuration and having a data capacity of 24 bits are arranged.
FIG. 7 shows only the internal configuration of the memory cell unit 800. The memory cell unit 800 is the same as the memory cell unit 100 shown in FIGS. 2 and 5 except that the cell selection transistors TW30, TW31... TW37, the memory transistors TM30, TM31. . Similarly, the memory cell unit 801 is different from the memory cell unit 101 shown in FIGS.
0 to TW37, TM30 to TM37, and TWS3. Cell selection transistors TW30 to TW
W37 and the gate electrode of the sense word select transistor TSW3 are commonly connected to a word line WL2. Memory transistor TM3k has the same structure as memory transistors TM1k and TM2k (see FIG. 3).

That is, E of the third embodiment shown in FIG.
The EPROM is configured so that the memory cell units 800 and 801 arranged in the memory cell array 8 can be operated by a redundant memory cell unit or a non-redundant memory cell unit in a programmable manner. As shown in FIG. 5 (see FIG. 5),
The redundant region and the non-redundant region in the memory cell array 6 are different from those determined in advance. The row decode unit 9 selects one of the word lines WL0 to WL3,
Alternatively, they can be selected at the same time.

Next, the operation of the EEPROM according to the third embodiment of the present invention shown in FIG. 7 will be described. First, the data read operation will be described. Here, an operation until a memory from which data is read is selected will be mainly described. The operation of reading data from the selected memory cell is the same as in the second embodiment. A memory cell selection operation in a data storage operation is similar to a selection operation in a read operation described below.

In the EEPROM shown in FIG. 7, one of the memory cell units is selected based on the address data A2, A1, A0, and the word line WL is selected.
0, WL1, and WL2, or all or two of them, the 2 in the memory cell unit is selected.
A 4-bit memory cell, a 16-bit memory cell, or an 8-bit memory cell is selected, and the word data D7 to D0 stored in the selected memory cell are divided by three.
Bit redundant reading, 2-bit redundant reading, or non-redundant reading. Word lines WL0, WL1, W
How L2 is selected depends on the control signals E1, E2, E3 output from the decoder control circuit DC.
Is determined based on which of the first, second, and third settings described above.

First, the control signals E1, E2, E3
Are the first settings, ie, E1, E2, E3 = “L, L,
The data read operation when L "is described.
Is a setting in which one of the word lines WL0, WL1, and WL2 is alternatively selected to perform non-redundant read. At this time, the address decoder ADR6 (see FIG. 8) sets the row selection signal to "1" only when the address data A2, A1 = "L, L". In the address decoder ADR7, the control signal E1 = ""
L ”, the output of AND7 is always“ L ”, and
The first input terminal of D8 is always "H". Therefore, the address decoder ADR7 outputs the output signal of AND6 as the row selection signal R1, and outputs the address data A2, A1.
= “L, H”, the row selection signal R1 is set to “1”.
To Also, in the address decoder ADR8, since the control signals E2 and E3 = "L, L", AND
10 and AND11 are always "L", AND12
Is always "H", whereby the outputs of AND13 and AND14 are always "L", and the second input terminal of AND15 is always "H". Therefore, the address decoder ADR8 outputs the output signal of the AND9 as the row selection signal R2, and sets the row selection signal R2 to "1" only when the address data A2, A1 = "H, L".

That is, in the first setting, when the address data A2, A1 = "L, L", the word line W
L0 is selected, and the data stored in the memory cells MC10 to MC17 is read non-redundantly. Similarly, when the address data A2, A1 = "L, H", the word line WL1 is selected and the memory cells MC20 to MC2 are selected.
7 is read non-redundantly, and when the address data A2, A1 = "H, L", the word line WL2 is selected and the memory cells MC30-MC
The data stored in 37 is read non-redundantly.

Next, the control signals E1, E2, E3
Are the second settings, that is, E1, E2, E3 = “H, L,
The data read operation when L "," L, H, L "or" L, L, H "is described.The second setting is, for example, E1, E2, E3 =" H, L, L " At this time, the word lines WL0 and WL1 are simultaneously selected to perform 2-bit redundant reading, and the word line WL2 is independently selected to perform non-redundant reading.
In the setting of 1, E2, E3 = "H, L, L", the address decoder ADR6 outputs the address data A2, A1.
= "L, L", the row selection signal R0 is set to "1".
To In the address decoder ADR7, since the control signal E1 = "H", the output of the AND8 is always "L" and the first input terminal of the AND7 is always "H".
H ”. Therefore, the address decoder ADR7 outputs
The output signal of D7, that is, the row selection signal R0 is output as the row selection signal R1, and R1 is output only when the row selection signal R0 is "1" regardless of the address data A2 and A1.
To “1”. Further, the address decoder ADR8 performs the same operation as that of the first setting because the control signals E2 and E3 = "L, L", and the address data A
2. Only when A1 = "H, L", the row selection signal R2
To “1”.

That is, in the second setting, when the address data A2, A1 = "L, L", the word line W
L0 and WL1 are simultaneously selected, and memory cell MC1 is selected.
Word data D0 to D7 stored in 0 to MC17 and MC20 to MC27 are redundantly read. When the address data A2, A1 = "H, L", the word line WL2 is selected, and the data stored in the memory cells MC30 to MC37 is read non-redundantly. In the same manner as above, when setting E1, E2, E3 = “L, H, L”, the address data A2, A1 = “L,
When "L", the word lines WL0 and WL2 are simultaneously selected. When E1, E2, E3 = "L, L, H", the address data A2, A1 = "L,
When "H", the word lines WL1 and WL2 are simultaneously selected.

Next, the control signals E1, E2, E3
Are the third setting, that is, E1, E2, E3 = “H, H,
A description will be given of a data read operation when the word line WL is "L" or "H, L, H."
This is a setting in which 0, WL1, and WL2 are simultaneously selected to perform 3-bit redundant reading. E1, E2, E3 = "
In the setting of "H, H, L", the address decoder ADR
No. 6 sets the row selection signal to "1" only when the address data A2, A1 = "L, L". Since the address decoder ADR7 has the control signal E1 = "H", the second setting (E1, E2, E3 = "H, L,
L "), the address data A2,
Regardless of A1, R1 is set to "1" only when the row selection signal R0 is "1". Address decoder ADR
8, the control signals E2 and E3 = "H,
Since the output of AND10 and AND12 is always "L" and the output of AND11 is always "H", the outputs of AND13 and AND15 are always "L".
L ", the second input terminal of the AND 14 is always" L. "Therefore, the address decoder ADR8 outputs the row selection signal R0 as R2, and outputs the address data A2, A1.
= "L, L", the row selection signal R2 is set to "1".
To

That is, in the third setting, when the address data A2, A1 = "L, L", the word line W
L0, WL1, and WL2 are simultaneously selected, and the memory cells MC10 to MC17, MC20 to MC27, MC3
0 to word data D0 to D7 stored in MC37.
Is read out three bits redundantly. In addition, E1, E2, E3
The same applies to the setting of "H, L, H".

As described above, according to the third embodiment, how the word line is selected can be externally controlled, so that the redundant area can be freely selected, and the redundant bit can be selected. The number can be freely selected.

[0092]

As described above, according to the error correction circuit and the semiconductor memory device of the present invention, the same data is stored in a plurality of memory cells, and the data stored in the plurality of memory cells is ANDed. By using data as read data, there is an effect that a bit error of an arbitrary memory cell can be corrected with a simple circuit configuration.

Further, according to the semiconductor memory device of the ninth to seventeenth aspects, dividing the memory cell array into a redundant area and a non-redundant area has an effect that an increase in chip area can be prevented.

Furthermore, according to the semiconductor memory device of the twelfth to seventeenth aspects, it is possible to externally control how the word line is selected, so that the redundant area can be freely selected. And the number of redundant bits can be freely selected.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of an EEPROM having no error correction function.

FIG. 2 is a diagram showing a configuration of an EEPROM according to the first embodiment of the present invention.

FIG. 3 is a diagram showing a detailed configuration of a memory cell in the EEPROM.

FIG. 4 is a diagram showing an internal configuration of a sense amplifier in the EEPROM.

FIG. 5 is a diagram showing a configuration of an EEPROM according to a second embodiment of the present invention.

FIG. 6 is a diagram illustrating a configuration of an address decoder of a row decode unit in an EEPROM according to a second embodiment of the present invention.

FIG. 7 is a diagram showing a configuration of an EEPROM according to a third embodiment of the present invention.

FIG. 8 is a diagram showing a configuration of an address decoder of a row decode unit in an EEPROM according to a third embodiment of the present invention.

[Explanation of symbols]

1,6,8 memory cell array, 2,7,9 row decode unit, TM memory transistor, TW cell select transistor, BL bit line, WL word line, ADR address decoder.

Claims (17)

[Claims] 1. The same data is stored in first to Nth (N is an integer of 2 or more) memory cells, and the N data stored in the first to Nth memory cells are ANDed or ORed. An error correction circuit for outputting the corrected data as error correction data. 2. The AND or OR circuit is connected by commonly connecting data output electrodes of the first to Nth memory cells and simultaneously outputting the N data from the first to Nth memory cells. 2. The error correction circuit according to claim 1, wherein the generated error data is generated. 3. The error correction circuit according to claim 2, wherein said memory cell is a nonvolatile memory cell capable of electrically erasing and writing data. 4. A semiconductor device comprising: the first to Nth memory cells; a bit line; and a first to Nth word lines which are simultaneously at a first level. The memory cell of any of integers includes a k-th cell selection transistor and a k-th memory transistor, and the k-th cell selection transistor includes a gate connected to the k-th word line, and a bit line. A transistor having a first electrode connected to the word line and a second electrode, turned on when the word line is at a first level, and turned off when the word line is at a second level; The memory transistor includes a control gate to which a sense voltage is input, a floating gate for storing data, and a first electrode connected to the second electrode of the k-th word select transistor. When error correction circuit according to claim 3, characterized in that a non-volatile memory transistor having a second electrode connected to the array ground. 5. A memory cell array in which a plurality of error correction circuits each having first to Nth (N is an integer of 2 or more) memory cells are formed. Select one error correction circuit, and store the data in the error correction circuit. When reading data, select an error correction circuit in which the data is stored, and read out the data from the error correction circuit. The selected error correction circuit stores the same input data in the first to Nth memory cells when storing data, and stores the same input data in the first to Nth memory cells when reading data. A semiconductor memory device for outputting data obtained by ANDing or ORing stored N data as error correction data. 6. The error correction circuit connects data output electrodes of the first to Nth memory cells to the same bit line, and simultaneously transmits the N data from the first to Nth memory cells. 6. The semiconductor memory device according to claim 5, wherein said ANDed or ORed data is generated on said bit line by outputting. 7. The semiconductor memory device according to claim 6, wherein said memory cell is a nonvolatile memory cell capable of electrically erasing and writing data. 8. The plurality of error correction circuits, a bit line provided for each of the error correction circuits, first to N-th word lines provided for each of the error correction circuits, Word selecting means for simultaneously selecting one of the plurality of error correction circuits by simultaneously setting the N word lines to the first level, wherein the k-th (k is 1 to N) The memory cell of any of integers includes a k-th cell selection transistor and a k-th memory transistor, and the k-th cell selection transistor has a gate connected to the k-th word line and a k-th memory cell. A transistor having a first electrode and a second electrode connected thereto, the transistor being turned on when the word line is at a first level, and turned off when the word line is at a second level; The k-th memory transistor includes a control gate to which a sense voltage is input, a floating gate for storing data, a first electrode connected to the second electrode of the k-th word selection transistor, and a connection to an array ground. 8. The semiconductor memory device according to claim 7, wherein the semiconductor memory device is a nonvolatile memory transistor having a second electrode. 9. The first to Nth (N
Is an integer of 2 or more), a memory cell array in which a redundant memory cell and a non-redundant memory cell are formed, and a data output electrode of the first to Nth redundant memory cells and a data output electrode of the non-redundant memory cell. And a bit line connected in common. When storing data, the error correction circuit or the non-redundant memory cell is selected for one input data, and the data is stored in the error correction circuit or the non-redundant memory cell. And, at the time of data reading, select an error correction circuit or a non-redundant memory cell storing the data,
The data is read from the error correction circuit or the non-redundant memory cell. The error correction circuit stores the same input data in the first to Nth redundant memory cells when storing data, and reads the data when reading data. To
A semiconductor memory device, wherein data obtained by ANDing or ORing N data stored in the first to Nth redundant memory cells is generated on the bit line as error correction data. . 10. The semiconductor memory device according to claim 9, wherein said memory cell is a nonvolatile memory cell capable of electrically erasing and writing data. 11. The error correction circuit, the non-redundant memory cell, the bit line, first to Nth word lines provided for the error correction circuit, and (N + 1) provided
And a word selection means for selecting the first to (N + 1) th word lines. The k-th (k is any integer from 1 to N) redundant memory cell is a k-th redundant memory cell. The (n + 1) th cell selection transistor and the (N + 1) th memory transistor, and the non-redundant memory cell comprises the (N + 1) th cell selection transistor and the (N + 1) th memory transistor. ))
Has a gate connected to the i-th word line, a first electrode connected to the bit line, and a second electrode, and is turned on when the word line is at a first level. And a transistor that is turned off when the word line is at a second level, the i-th memory transistor includes a control gate to which a sense voltage is input, a floating gate that stores data, and a k-th word selection. A non-volatile memory transistor having a first electrode connected to the second electrode of the transistor and a second electrode connected to an array ground, wherein the word selecting means includes the first to Nth word lines At the same time as the first level, thereby selecting the error correction circuit, and setting the (N + 1) th word line to the first level. The semiconductor memory device according to claim 10, wherein the selecting the non-redundant memory cells by setting. 12. A memory cell array in which first to Nth (N is an integer of 2 or more) memory cells are formed, and a bit line to which data output electrodes of the first to Nth memory cells are commonly connected. And selecting the k-th (where n is an integer of 1 to N) memory cells from the first to Mth memory cells as non-redundant memory cells when the external setting is the first setting When the external setting is the second setting, the first to Nth memory cells are simultaneously selected as redundant memory cells, and at the time of data storage, input data is error-corrected by the redundant memory cells. Alternatively, the data is stored in the non-redundant memory cell, and at the time of data reading, the data is read from the error correction circuit or the non-redundant memory cell storing the data. The same input data is stored in the first to Nth redundant memory cells, and when reading data,
A semiconductor memory device, wherein data obtained by ANDing or ORing M data stored in the first to Nth redundant memory cells is generated on the bit line as error correction data. . 13. The semiconductor memory device according to claim 12, wherein said memory cell is a nonvolatile memory cell capable of electrically erasing and writing data. 14. The first to Nth memory cells, the bit line, the first to Nth word lines, and the first to Nth word lines according to the first and second settings. A word selecting means for selecting, the k-th (k is any integer from 1 to N) memory cell comprises a k-th cell selection transistor and a k-th memory transistor, and the k-th cell The selection transistor has a gate connected to the k-th word line, a first electrode connected to the bit line, and a second electrode, and turns on when the word line is at a first level; A transistor that turns off when the word line is at a second level, the k-th memory transistor includes a control gate to which a sense voltage is input, and a floating gate to store data A non-volatile memory transistor having a first electrode connected to the second electrode of the k-th word selection transistor, and a second electrode connected to an array ground; In the setting, the k-th memory cell is selected by setting the k-th word line to the first level, and in the second setting, the first to N-th word lines are simultaneously set to the first level. 14. The 1st to Nth memory cells are selected at the same time by setting to 1 level.
13. The semiconductor memory device according to claim 1. 15. A memory cell array in which first to Mth (M is an integer of 3 or more) memory cells are formed, and a bit line to which data output electrodes of the first to Mth memory cells are commonly connected. And selecting a p-th (p is an integer from 1 to M) memory cell from the first to M-th memory cells as a non-redundant memory cell when the external setting is the first setting. When the external setting is the second setting, the first to qth (q is any integer from 2 to (M−1)) memory cells are replaced with the redundant memory cells from the first to Mth memory cells. Or the rth (r is any integer from (q + 1) to M) memory cell is selected as a non-redundant memory cell, and when the external setting is the third setting, The first to Mth memory cells are replaced by a redundant memo constituting an error correction circuit. Cells are selected at the same time, and at the time of data storage, the input data is stored in an error correction circuit comprising the redundant memory cells or the non-redundant memory cells. Reading the data from a correction circuit or a non-redundant memory cell, the error correction circuit stores the same input data in the redundant memory cell when storing data, and stores the same input data in the redundant memory cell when reading data. AND O of M data
A semiconductor memory device wherein data obtained by taking R is generated as error correction data on the bit line. 16. The semiconductor memory device according to claim 15, wherein said memory cell is a nonvolatile memory cell capable of electrically erasing and writing data. 17. The first to M-th memory cells, the bit lines, the first to M-th word lines, and the first to M-th word lines according to the first to third settings. A s-th memory cell, wherein the s-th (s is an integer from 1 to M) memory cell comprises an s-th cell selection transistor and an s-th memory transistor; The selection transistor has a gate connected to the s-th word line, a first electrode connected to the bit line, and a second electrode, and turns on when the word line is at a first level. A transistor that is turned off when the word line is at a second level, wherein the s-th memory transistor is a control gate to which a sense voltage is input, and a floating gate that stores data. A non-volatile memory transistor having a first electrode connected to the second electrode of the k-th word selection transistor, and a second electrode connected to an array ground; In the setting, the p-th word line is set to the first level to select the p-th memory cell, and in the second setting, the first to q-th word lines are simultaneously selected. Or by selecting the r-th word line, thereby simultaneously selecting the first to q-th memory cells, or selecting the r-th memory cell. 17. The method according to claim 16, wherein the first to Mth memory cells are simultaneously selected by simultaneously setting the first to Mth word lines to the first level.
13. The semiconductor memory device according to claim 1.