JPH1185471A - Calculation method and calculation device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the circuit scale of a digit adjusting means and to efficiently realize a double precision multiplication. SOLUTION: In a binary fixed point system for setting up a most significant bit(MSB) as a code bit S and a point between the MSB and a bit just under the MSB as a binary point position, respective products between the higher word HX/lower word XL of a double precision multiplicand and the higher word YH/lower word YL of a double precision multiplier are found out by using a single precision multiplier, and in the case of executing the adjusting addition of respective found products to obtain a double precision multiplied result, respective products between the higher word XH/lower word XL of a double precision multiplicand and the higher word YH/lower word YL of a double precision multiplier are set up so as to have at least two digits higher than the binary point position, so that the double precision multiplied result can be found out by bit width more than double precision bit width at least one bit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a calculation method and a calculation device for performing double precision multiplication using a single precision multiplier.

[0002]

2. Description of the Related Art As a conventional double precision multiplication method, a single precision multiplier is used to find the product of each of the upper word / lower word of the double precision multiplicand and the upper word / lower word of the double precision multiplier. There is a method of performing digit-matching addition on a product to obtain a double-precision multiplication result. This method is disclosed in, for example, Japanese Patent Application Laid-Open No. H8-30439. In the conventional example described in Japanese Patent Application Laid-Open No. Hei 8-30439, means for holding the most significant bit of the double precision multiplier lower word is provided, and the most significant bit of the double precision multiplier lower word is used for encoding the double precision multiplier upper word. In this case, the double precision multiplier lower word is treated as a signed binary number. Further, in order to perform multiplication of the double precision multiplicand lower word, a multiplication means having a function capable of performing multiplication even when the multiplicand is an unsigned binary number is provided. In this conventional example, the double precision multiplication is realized without lowering the precision by the above.

[0003]

However, in the conventional example described in Japanese Patent Application Laid-Open No. H8-30439, when a multiplicand is treated as an unsigned binary number by a multiplication means, one bit higher than the most significant bit of the multiplicand is used. Is assumed to be a positive number. Therefore, the digit position of the sign of the multiplication result is different from the multiplication result with the multiplicand, which is a signed binary number. For this reason, the number of shifts of the digit alignment when adding the products of the upper word / lower word of the double precision multiplicand and the upper word / lower word of the double precision multiplier is different, and the circuit scale of the digit alignment means becomes large. Had.

[0004] The present invention solves the above problems,
It is an object of the present invention to provide an arithmetic method and an arithmetic device which realize a double-precision multiplication efficiently by reducing the circuit scale of the digit aligning means.

[0005]

The arithmetic method according to the present invention provides a single-precision binary fixed-point number system in which the most significant bit is a sign bit and the decimal point position is between the most significant bit and one lower bit. When obtaining the product of each of the high-order word / low-order word of the double-precision multiplicand and the high-order word / low-order word of the double-precision multiplier using the multiplier, and performing digit-alignment addition on the obtained products to obtain a double-precision multiplication result The product of each of the high-order word / low-order word of the double precision multiplicand and the high-order word / low-order word of the double precision multiplicand has at least two or more digits above the decimal point position, so that It is obtained with a bit width that is one bit larger (claim 1).

As described above, by having at least two or more digits higher than the decimal place, the shift number for digit alignment of each product obtained with a bit width at least one bit larger than the double precision bit width is as follows: The bit widths are relatively limited to the same bit width, and the circuit scale of the digit aligning means can be reduced, and the double precision multiplication can be efficiently realized. Here, the product of each of the high-order word / low-order word of the double precision multiplicand and the high-order word / low-order word of the double-precision multiplier is calculated from the bit width of the double precision by having at least three or more digits above the decimal point. Finding with a bit width of 2 bits, 3 bits, or more increases the sign scale of the product obtained with a bit width of 1 bit, which only increases the circuit size. It is sufficient to obtain a bit width one bit larger than the double precision bit width by having two digits. In the following, the calculation method of the present invention will be described on the assumption that the product of each of the upper word / lower word of the double precision multiplicand and the upper word / lower word of the double precision multiplier is obtained with a bit width one bit larger than the double precision bit width. I do.

In this case, in the above calculation method, when obtaining the product of the double precision multiplicand lower word and the double precision multiplier lower word, for example, a positive number is indicated one bit higher than the most significant bit of the double precision multiplicand lower word. Multiplies the data to which the sign bit is added by the data in which the most significant bit of the double precision multiplier lower word is the sign bit, and adds a value “0” one bit lower than the least significant bit of the multiplication result. Is output as the product to be obtained (claim 2).

When calculating the product of the double-precision multiplicand upper word and the double-precision multiplier lower word, for example, data obtained by sign-extending the sign bit of the upper-order bit of the double-precision multiplicand upper word by one bit and double-precision multiplier lower The word is multiplied with the data having the most significant bit as the sign bit, and a value obtained by adding a value “0” to the least significant bit one bit lower than the least significant bit is output as a product to be obtained (claim 3).

When calculating the product of the double-precision multiplicand lower word and the double-precision multiplier upper word, for example, data obtained by adding a sign bit indicating a positive number one bit higher than the uppermost bit of the double-precision multiplicand lower word is used. Is multiplied by data obtained by adding data having the same value as the most significant bit of the double precision multiplier lower word to the digit position of the least significant bit of the double precision multiplier upper word, and one bit lower than the least significant bit of the multiplication result The value obtained by adding the value "0" to the output is output as the product to be obtained (claim 4).

When calculating the product of the double-precision multiplicand high-order word and the double-precision multiplier high-order word, for example, data obtained by sign-extending the sign bit of the double-precision multiplicand high-order word by 1 bit and double-precision multiplier high-order The multiplication is performed by multiplying the digit position of the least significant bit of the word by data having the same value as the most significant bit of the double precision multiplier low word, and adding the value “0” to the least significant bit of the multiplication result by one bit lower. Is output as the product to be obtained (claim 5).

Here, the normally used single precision multiplier is 2
Multiplication of two single-precision numbers is performed, and the multiplication result is obtained as data having a bit width one bit less than double precision. However, since the decimal point is aligned and the result is output in double precision bit width, the multiplication result is obtained. The value “0” is added one bit lower than the least significant bit of, and double precision data is output as a product.

Further, a single-precision multiplier for calculating the product of each of the upper word / lower word of the double precision multiplicand and the upper word / lower word of the double precision multiplier.
In 5), since the sign is extended one bit higher than the most significant bit of the multiplicand or a sign bit indicating a positive number is added, the multiplication result has the same bit width as double precision. However, even if sign extension or a sign bit indicating a positive number is added, the decimal point position of the multiplicand does not change, so that the multiplication result obtained by the above single precision multiplier is compared with the multiplication result of the conventional single precision multiplier. By having at least two or more digits higher than the decimal point position, it is possible to obtain data having one bit more data. The single-precision multiplier described above uses the least significant bit 1 of the multiplication result as described above from the relationship of the digit position.
A value “0” is added to the lower bits, and two digits are provided above the decimal point, thereby obtaining a product with a bit width one bit larger than the double precision bit width.

The arithmetic unit according to the present invention executes double precision multiplication using a single precision multiplier for multiplying two signed binary fixed-point data, and holds an MSB holding the most significant bit of the multiplier. Means, a data selection means for selecting and outputting one of the data held by the MSB holding means and the value "0", and a multiplier encoding means for encoding and outputting the multiplier using the multiplier and the output data of the data selection means If the multiplicand determination signal is inactive, the sign bit, which is the most significant bit of the multiplicand, is extended by one bit to obtain the result of multiplication with the output data of the multiplier encoding means. A sign bit indicating a positive number is added to the upper bit of the upper bit to obtain a result of multiplication with the output data of the multiplier encoding means. Multiplying means having at least two or more higher-order digits to output at a bit width at least one bit larger than the double precision bit width; output data of the multiplication means being an addend, and being at least one bit greater than the double precision bit width; An adding means for performing addition with an addend having a bit width larger than a bit and outputting an addition result having a bit width at least one bit larger than the double precision bit width, and an addition result holding the addition result output from the adding means And a digit matching means for selecting one of the data held by the addition result holding means and the value “0”, performing a digit matching process, and outputting the result as an augend of the adding means. Claim 6).

According to this configuration, since the multiplying means has at least two digits higher than the decimal point, and outputs the multiplication result with a bit width at least one bit larger than the double precision bit width, The number of shifts for digit alignment of the multiplication result is relatively limited to the same bit width, so that the circuit scale of the digit alignment means can be reduced and double-precision multiplication can be efficiently realized.

In this case, in the above-mentioned arithmetic unit, the operation of the MSB holding means at the time of performing the double precision multiplication includes, for example, a double precision multiplier lower word and a double precision multiplicand upper word /
When calculating the product with the lower word, the most significant bit of the double precision multiplier lower word is retained.
Further, in the above arithmetic device, as an operation of the data selecting means at the time of performing the double precision multiplication, for example, a value “0” is obtained when obtaining a product of a double precision multiplier lower word and a double precision multiplicand upper word / lower word. To select and output the most significant bit of the double precision multiplier lower word held by the MSB holding means when obtaining the product of the double precision multiplier upper word and the double precision multiplicand upper word / lower word. (Claim 8).

In the above arithmetic unit, the operation of the multiplier encoding means when performing double precision multiplication includes, for example, a double precision multiplier lower word and a double precision multiplicand upper word / word.
The double precision multiplier lower word input when calculating the product of the lower word and the output data of the value “0” selected by the data selection means are encoded and output by the Booth algorithm, and the double precision multiplier upper word and the double precision multiplier are output. MSB selected by the data selection means when obtaining the product of the multiplicand upper word / lower word
The output data of the most significant bit of the double-precision multiplier low-order word held by the holding means is encoded by the Booth algorithm and output.

Further, in the above-described arithmetic unit, the multiplying means includes:
For example, if the multiplicand determination signal is active, the input multiplicand is determined to be the lower word of the double-precision multiplicand, and a sign bit indicating a positive number is added one bit higher than the most significant bit of the multiplicand, and the multiplier encode means Find the partial product with the output data of, if the multiplicand determination signal is inactive, determine that the input multiplicand is the upper word of the double precision multiplicand,
There is provided partial product generation means for extending the sign bit, which is the most significant bit of the multiplicand, by one bit and obtaining a partial product with output data of the multiplier encoding means.
The multiplying means includes at least two partial product generating means, adds the partial products, which are output data of the plurality of partial product generating means, at the same digit position, and adds one bit lower than the least significant bit of the partial product addition result. May be output as a product obtained by adding data of a value “0” to the data (claim 11).

In the above arithmetic device, a multiplication result holding means for temporarily holding the output data of the multiplication means and outputting it as an addend of the addition means may be provided so that the multiplication means and the addition means can operate in parallel ( Claim 12). As a result, the operation time can be reduced. Further, in the arithmetic device described above, the multiplier encoding means may have a function of forcibly setting the least significant bit of the multiplier as input data to the value “0” (claim 13). A function may be provided for forcibly setting the least significant bit of the multiplicand, which is input data, to the value "0".

The purpose of the present invention is to efficiently perform high-precision double-precision multiplication. However, in some applications that are currently in practical use, the standard is determined for low-precision double-precision multiplication. For example, a voice coding process used in a digital mobile phone or the like is the same. Therefore, as described above, the function of forcibly setting the least significant bits of the multiplier and the multiplicand to the value “0” (claims 13 and 14)
Has compatibility with applications using low-precision double-precision multiplication.

Here, what is called low-precision double-precision multiplication is that, when performing double-precision multiplier lower word or double-precision multiplicand lower word data in double-precision multiplication, double-precision multiplication is performed. The multiplier lower word or double-precision multiplicand lower word is shifted one bit to the right, and data in which a sign bit indicating a positive number is inserted in the digit position of the most significant bit is created in advance, and the data is converted to the double-precision multiplier lower word or double. This is double-precision multiplication in which multiplication is performed using data of the lower word of the precision multiplicand. The sign bits of the double-precision multiplier and the double-precision multiplicand correspond to the most significant bits of the double-precision multiplier upper word and the double-precision multiplicand upper word, respectively.The double-precision multiplier lower-order word and double-precision multiplicand lower-order word are all data bits having no sign bit. It will be data.

An ordinary single-precision multiplier that handles signed binary fixed-point numbers is not configured to handle all data bits. Therefore, since the double precision multiplier lower word and the double precision multiplicand lower word are considered to be positive data, respectively, it is considered to add a sign bit indicating a positive number. Since the number of bits is increased by one, the data of the least significant bit is truncated by shifting the data to the right by one bit, and the data width is reduced to a single precision bit width. In other words, since the data of the least significant bit of the double precision multiplier lower word and the double precision multiplicand lower word is discarded, the precision is deteriorated accordingly. The shift in the digit position caused by this one-bit right shift is absorbed in the digit alignment processing when adding the products of the double precision multiplier upper word / lower word and the double precision multiplicand upper word / lower word. doing.

Further, in the above arithmetic device, the MSB holding means replaces the means for holding the most significant bit of the multiplier, which is a signed binary number, but the most significant bit of the multiplier and the value “0”.
And means for selecting and holding one of them (claim 15). This makes it possible to use a common instruction for multiplication of double-precision data and double-precision data and for multiplication of double-precision data and single-precision data, thereby reducing the number of instructions.

[0023]

BEST MODE FOR CARRYING OUT THE INVENTION

[First Embodiment] Hereinafter, a first embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a diagram showing a configuration of an arithmetic unit according to an embodiment of the present invention. In FIG. 1, an MSB holding unit 10 holds the most significant bit of a multiplier that is a signed binary fixed-point number. The data selection means 11 selects and outputs the output of the MSB holding means 10 or the value "0". The multiplier encoding means 12 encodes the multiplier and the output of the data selecting means 11 by a secondary Booth algorithm.

The multiplying means 13 inputs the multiplicand which is a signed binary fixed-point number, the output of the multiplier encoding means 12 and the multiplicand discrimination signal C1, and if the multiplicand discrimination signal C1 is a value "0" and is in an inactive state, the multiplicand Is determined as the double precision multiplicand upper word, the sign bit that is the most significant bit of the multiplicand is sign-extended by 1 bit, and the result of multiplication with the output data of the multiplier encoding means 12 is obtained. On the other hand, if the multiplicand discrimination signal C1 is in the active state with the value “1”, the multiplicand is discriminated as the double precision multiplicand lower word, and the sign bit of the value “0” as a sign indicating a positive number one bit higher than the most significant bit of the multiplicand To obtain the result of multiplication with the output data of the multiplier encoding means 12. Then, the data obtained by adding the data of value “0” one bit lower than the least significant bit of the obtained multiplication result has at least two or more digits higher than the decimal point position, so that the data is at least one bit larger than the double precision bit width. Output as a product with more bits.

Here, in the present invention, as a representation of single precision data and double precision data, the most significant bit is a sign bit, and the decimal point position is between the most significant bit and one bit lower than the most significant bit. I am thinking of a binary fixed-point number system. Normally, there is only one bit serving as a sign bit above the decimal point position. In other words, the expression "having at least two or more digits higher than the decimal point position" and the expression "having a bit width at least one bit larger than the double precision bit width" state the same thing.

The adding means 14 uses the output of the multiplying means 13 as an addend. The addend has at least two digits higher than the decimal point, thereby adding an addend having a bit width at least one bit larger than the double precision bit width. And outputs an addition result having a bit width that is at least one bit larger than the double precision bit width by having at least two digits higher than the decimal point position. The addition result holding means 15 holds the output of the addition means 14. The digit aligning means 16 outputs the output of the addition result holding means 15 without shifting when the digit aligning control signal C2 expressed by 2 bits is (C2-1, C2-0) = (0, 1). When the alignment control signal C2 is (C2-1, C2-0) = (1, 0), the output of the addition result holding means 15 is shifted right by 16 bits and output.
When the digit adjustment control signal C2 is (C2-1, C2-0) = (0,
0), the value “0” is selected and output.

Symbols C2-1 and C2-0 denote bit components of the digit alignment control signal C2, respectively. Code 20
Is storage means serving as a source and a destination of each operation instruction executed by the operation device of the present embodiment. Here, the multiplication result holding means 17 and the selection means 1
8 and 19 do not exist, and the output of the multiplication means 13 is
4, the output of the addition result holding means 15 is directly input to the digit matching means 16. Further, the multiplication result holding means 17 and the selection means 18,
19 will be described later.

In FIG. 1, the multiplication encoding means 1
The multiplier control signal C3 input to 2 and the multiplicand control signal C4 input to the multiplying means 13 are necessary signals in the second embodiment, and are unnecessary in the first embodiment. Further, the value “0” and the held data selection signal C5 input to the MSB holding unit 10 are necessary signals in the third embodiment, and are not required in the first embodiment.

The operation of the arithmetic unit configured as described above will be described. For simplicity, a 16-bit signed binary fixed-point number is defined as single-precision data, and a 32-bit signed binary fixed-point number is defined as double-precision data. A case where multiplication of double-precision data and double-precision data is performed will be described. It is assumed that a double-precision multiplicand includes an upper word XH and a lower word XL, and a double-precision multiplier includes an upper word YH and a lower word YL. In this case, the data selecting means 11 selects the value "0" when performing the multiplication on the double precision multiplier lower word YL, and selects the MSB holding means 10 when performing the multiplication on the double precision multiplier upper word YH.
Shall be selected. The multiplicand determination signal C
1 is a signal which becomes active when the value is "1" when multiplication is performed on the double precision multiplicand lower word XL, and becomes inactive when the value is "0" when multiplication is performed on the double precision multiplicand upper word XH.

First, the product (hereinafter, XL × YL) of the double precision multiplicand lower word XL and the double precision multiplier lower word YL is obtained. The double precision multiplier lower word YL is a multiplier encoding means 1
2, the most significant bit of which is input to the MSB holding means 10
Is held. The data selector 11 selects the value “0” and outputs it to the multiplier encoder 12. The multiplier encoding means 12 encodes the double precision multiplier lower word YL and the output data of the data selection means 11 using the Booth algorithm, and the value “0” output from the data selection means 11 is lower than the double precision multiplier lower word YL. Used for 2-bit encoding. The multiplicand determination signal C1 is active at a value of "1", indicating that the input multiplicand is the double precision multiplicand lower word XL. The multiplication means 13 adds a sign bit of a value “0” as a sign indicating that it is a positive number to one bit higher than the most significant bit of the double precision multiplicand lower word XL based on the multiplicand discrimination signal C 1, And outputs it in a 33-bit width.

At this time, the digit alignment control signal C2 becomes (C2
(-1, C2-0) = (0, 0), and the digit matching means 16 selects and outputs the value "0". The adding means 14 is a multiplying means 13
The result of addition of the product XL × YL, which is the output of, and the value “0”, which is the output of the digit matching means 16, is output. The addition result holding means 15 holds the product XL × YL which is the output of the addition means 14.

Next, the product of the double precision multiplicand upper word XH and the double precision multiplier lower word YL (hereinafter XH × YL) is determined. The double-precision multiplier lower word YL is input to the double-precision multiplier encoding unit 12, and the most significant bit thereof is held in the MSB holding unit 10. The data selector 11 selects the value “0” and outputs it to the multiplier encoder 12. The multiplier encoding means 12 encodes the double precision multiplier lower word YL and the output data of the data selecting means 11 using the Booth algorithm, and outputs the value “0” which is the output of the data selecting means 11.
Is used for encoding the lower 2 bits of the double precision multiplier lower word YL. The multiplicand determination signal C1 is inactive at a value "0", and the input multiplicand is the double precision multiplicand upper word X
H. The multiplication means 13 outputs the multiplicand determination signal C
The sign bit which is the most significant bit of the double precision multiplicand upper word XH is sign-extended by 1 bit by 1, and the product with the output of the multiplier encoding means 12 is obtained and output with a 33-bit width.

At this time, the digit adjustment control signal C2 becomes (C2
(-1, C2-0) = (1, 0), and the digit matching means 16 selects the product XL × YL held by the addition result holding means 15 and shifts it by 16 bits to the right for digit alignment and outputs the result. I do. The adding means 14 outputs the product XH ×
An addition result of YL and a product XL × YL output from the digit matching means 16 is output. The addition result holding means 15 holds XL × YL + XH × YL output from the addition means 14.

Next, the product of the double precision multiplicand lower word XL and the double precision multiplier upper word YH (hereinafter, XL × YH) is obtained. Double precision multiplier upper word YH is multiplier encoding means 1
2 is input. The data selection means 11 selects the output of the MSB holding means 10 and outputs the data of the most significant bit of the double precision multiplier lower word YL held by the MSB holding means 10 to the multiplier encoding means 12. The multiplier encoding means 12 includes the double precision multiplier upper word YH and the data selecting means 1
1 is encoded using Booth's algorithm, and the data of the most significant bit of the double precision multiplier lower word YL output from the data selector 11 is used for encoding the lower 2 bits of the double precision multiplier upper word YH. Can be The multiplicand determination signal C1 is active at a value of "1", indicating that the input multiplicand is the double precision multiplicand lower word XL. The multiplication means 13 adds a sign bit of a value “0” as a sign indicating that it is a positive number to one bit higher than the most significant bit of the double precision multiplicand lower word XL based on the multiplicand discrimination signal C 1, And outputs it in a 33-bit width.

At this time, the digit alignment control signal C2 becomes (C2
−1, C2−0) = (0, 1), and the digit aligning means 16 calculates XL × YL + XH × Y held by the addition result holding means 15.
Select and output L. The adding means 14 outputs the result of adding the product XL × YH output from the multiplying means 13 and XL × YL + XH × YL output from the digit matching means 16. The addition result holding means 15 is XL × Y which is the output of the addition means 14.
L + XH × YL + XL × YH is held.

Finally, the product of the double-precision multiplicand upper word XH and the double-precision multiplier upper word YH (hereinafter XH × YH) is obtained. Double precision multiplier upper word YH is multiplier encoding means 1
2 is input. The data selection means 11 selects the output of the MSB holding means 10 and outputs the data of the most significant bit of the double precision multiplier lower word YL held by the MSB holding means 10 to the multiplier encoding means 12. The multiplier encoding means 12 includes the double precision multiplier upper word YH and the data selecting means 1
1 is encoded using Booth's algorithm, and the multiplier lower word Y
The data of the most significant bit of L is used for encoding the lower two bits of the multiplier upper word YH. The multiplicand determination signal C1 is inactive at a value of "0", indicating that the input multiplicand is the double precision multiplicand upper word XH. Multiplication means 13
Is the double-precision multiplicand upper word X based on the multiplicand discrimination signal C1.
The sign bit which is the most significant bit of H is sign-extended by 1 bit, and the product of the sign bit and the output of the multiplier encoding means 12 is obtained and output with a 33-bit width.

At this time, the digit alignment control signal C2 becomes (C2
−1, C2−0) = (1, 0), and the digit aligning means 16 stores XL × YL + XH × Y held by the addition result holding means 15.
L + XL × YH is selected, right-shifted by 16 bits for digit alignment, and output. The adding means 14 adds the product XH × YH output from the multiplying means 13 and XL × YL + XH × YL + XL × YH output from the digit matching means 16 and outputs an addition result. XL which is the output of the adding means 14
× YL + XH × YL + XL × YH + XH × YH is the product required for the double precision multiplication.

In the above embodiment, when the product of the double-precision multiplicand upper word XH / lower word XL and the double-precision multiplier upper word YH / lower word YL are obtained and digit-alignment addition is performed, the double-precision multiplier upper word is used. At least one double-precision multiplier lower word YL before calculating the product of words YH
It is sufficient to hold the most significant bit of the double precision multiplier lower word YL in the MSB holding means 10. In this embodiment, the order in which the multiplication and the digit addition are performed to obtain the product XH × YL and the product XL × YH is as follows. May be interchanged. Multiplication of double-precision data and single-precision data is based on the assumption that single-precision data does not have data in the lower word of double-precision data, and the process of obtaining the product of the double-precision lower words can be omitted. Can be performed in the same way as

In the above description, as described above, the multiplication result holding means 17 and the selection means 18 and 19 are not provided.
The multiplication result holding means 17 for holding the multiplication result may be arranged between the control unit 4 and the control unit 4 so that the multiplication process and the addition process can be operated in parallel. The selecting means 18 and 19 shown in FIG.
These are used to supply data from the bus when the multiplier and the double-precision adder operate alone, and are not directly related to the present invention.

The details of the internal configuration and operation of the components in the present embodiment will be further described below with reference to FIGS.
This will be described with reference to FIG. FIG. 2 is a schematic diagram for explaining data division of a double precision multiplier when performing double precision multiplication.
The dashed line in FIG. 2 indicates that the bit is a bit having a negative weight. The data sequence shown in the upper row indicates a double precision multiplier. Here, Y31 to Y0 indicate data at each digit position, and the most significant bit, Y31, is a sign bit and has a negative weight. The meaning of “having a negative weight” means that if the bit is 1, it indicates the value “−1”, and if the bit is 0, it indicates the value “0”. Shown in the middle is a schematic diagram when the double precision multiplier is transformed based on Booth's algorithm. Here, three data items enclosed by a box indicate the encoded values of one booth, and -2 is set at an even digit position.
Take a value in the range of +2. However, an object of the present invention is to efficiently perform high-precision double-precision multiplication using a single-precision multiplier, and it is not possible to encode a double-precision multiplier at a time by the Booth algorithm. Focusing on data at the boundary between the double precision multiplier upper word and the lower precision word, Y15, which is the most significant bit of the double precision multiplier lower word,
Can be used for encoding the double-precision multiplier high-order word, the encoding of the double-precision multiplier can be performed well. The lower part shows the data supply of the double precision multiplier in the present invention. First, an operation for obtaining the product of the double precision multiplier lower words is performed. At this time, Y15, which is the most significant bit of the double precision multiplier lower words, is held. Next, when obtaining the product of the double precision multiplier upper word, the most significant bit Y15 of the stored double precision multiplier lower word is used for encoding the double precision multiplier upper word. Here, YH and YL in FIG. 2 indicate a double precision multiplier upper word and a lower precision multiplier word, respectively.

FIG. 3 is a diagram for explaining a data output format at the time of performing multiplication of the double precision multiplicand upper word XH and the double precision multiplier upper word YH / lower word YL. The dashed line in FIG. 3 indicates that the bit is a bit having a negative weight, and the symbol S indicates a sign bit, but if there is a masked S, the masked symbol S is a sign-extended code. A sign S, which is one bit lower, indicates that it is not a sign bit but a data bit having the same value as the sign bit. Further, 2 ¹ symbol 0 indicates that it is added the value "0" as the data is shown on top, 2 ^0, 2 ^-1, ..., 2 ^-31 is at each digit position Indicates the scale.

[0042] Here, if the multiplication of the normal two single-precision data, obtains the multiplication results with the sign bit in the digit position of the 2 ^0, 31 bits with data bits from the 2 ^-1 digit position of the 2 ^-30 It becomes width data. Therefore, a value “0” is added to the digit position of 2 ⁻³¹ and output as 32-bit width double precision data. In the present invention Yes and 1 bit sign extension multiplicand upper word YH, it obtains the multiplication result is obtained as a 1-bit sign-extended sign bit of the digit positions of 2 ⁰ to 2 ¹ digit position. If this result is output with a bit width of 32 bits, "32-bit output" is shown in FIG. 3 to ensure consistency with the data output when the multiplication of the single precision data described above is executed. It is better to output within the range. At this time, 2 ⁰ digit position is the sign bit. In the present invention, data is output with a bit width that is at least one bit larger than the double precision bit width by having at least two digits higher than the decimal point position. Here, outputting with a bit width of 2 bits, 3 bits, or more requires only sign expansion of the product obtained with a bit width of 1 bit more, which simply increases the circuit scale.
In the present embodiment, hereinafter, the description will be made assuming that the product to be obtained has a 33-bit width that is one bit larger than the double precision bit width by having at least two digits higher than the decimal point position. Also, by dividing the double precision multiplier into data as shown in FIG. 2, the double precision multiplier lower word YL
Can be treated as data having a negative weight, so when calculating the product of the double-precision multiplicand upper word XH and the double-precision multiplier lower word YL, the double-precision multiplier lower word YL is directly encoded by Booth's algorithm. Can be On the other hand, when calculating the product of the double precision multiplicand upper word XH and the double precision multiplier upper word YH, the data of the most significant bit Y15 of the double precision multiplier lower word YL is used to encode the double precision multiplier upper word YH. From the above, in FIG. 3, the double precision multiplier lower word YL is represented in the same manner as a single precision signed binary fixed point number, and in the case of multiplication of the double precision multiplier upper word YH, the double precision multiplier lower word is used. Y
Although the data of the most significant bit Y15 of L must be shown, it is omitted here for the sake of simplicity because the purpose is to explain the data output format.

FIG. 4 is a schematic diagram for explaining a data output format at the time of performing multiplication of the double precision multiplicand lower word XL and the double precision multiplier upper word YH / lower word YL. FIG.
The middle dashed line indicates that the bit is a bit having a negative weight, and the symbol S indicates a sign bit. Symbol 0 indicates that a value “0” is added as data, and the uppermost 2 ¹ , 2 ⁰ , 2 ⁻¹ ,..., 2 ⁻³¹
Indicates the scale at each digit position.

In the present invention, since the most significant bit of the double-precision multiplicand lower word is a data bit, a sign bit of a value "0" is added as a sign indicating a positive number one bit higher. ¹ digit position is the sign bit, 32 with data bits from the 2 ⁰ digit position of the 2 ^-30
Obtained as bit-width data. If this result is output with a bit width of 32 bits, it must be output in the range indicated as "32-bit output" in FIG. Comparing this output range with the range of "32-bit output" shown in FIG. 3, it can be seen that the output digit position is shifted by one digit. In other words, it can be seen that a means for switching the output range is required for “32-bit output”. On the other hand, in the present invention, data is output with a 33-bit width that is one bit larger than the double-precision bit width by having at least two digits higher than the decimal point position. Can be output in exactly the same digit position relationship as "." Here, as described in the description of FIG. 3, since there is no data obtained by multiplication at the digit position of ^2-31 , a value "0" is added and output.

Also, as in FIG. 3, the double precision multiplier lower word YL is expressed in the same manner as a single precision signed binary fixed point number, and in the case of multiplication of the double precision multiplier upper word YH, the double precision multiplier lower word YL is used. Although the data of the most significant bit Y15 of the word YL must be shown, it is omitted here for the sake of simplicity because the purpose is to explain the data output format. FIG. 5 is a schematic diagram for explaining a conventional digit shift bit shift for outputting a multiplication result with a 32-bit width. When data is output with a 32-bit width as shown in FIGS. 3 and 4, the relationship between the digit positions of the product of the double-precision multiplicand upper word XH and the product of the double-precision multiplicand lower word XL is shifted by 1 bit.
As shown in (1), the shift numbers for digit alignment when obtaining the double precision multiplication result are different from each other.

FIG. 6 is a diagram for explaining the digit shift bit shift of the present invention for outputting a multiplication result with a width of 33 bits. When the data is output in a 33-bit width, the relationship between the product of the double precision multiplicand upper word XH and the digit position of the product of the double precision multiplicand lower word XL becomes relatively the same, and as shown in FIG. It can be seen that the shift number for digit alignment when obtaining the multiplication result is relatively limited to a single precision bit width. Therefore, the circuit scale of the digit aligning means 16 can be reduced as compared with the conventional example which outputs data with a 32-bit width.

FIG. 7 is a circuit diagram showing a circuit configuration of the multiplier encoding means 12. Reference numeral 200 in FIG. 7 denotes Booth encoding means for generating one encoded value. The multiplier is 2
Encoded by the next Booth algorithm. The encoding result BEi takes five values of -2, -1, 0, 1, and 2, and the value is expressed by 3 bits of 1Ei, 2Ei and SEi, and the absolute value of the value is expressed by 2 bits of 2Ei and 1Ei. When the value is 1 when the value is negative, the sign of the value is SEi.
Indicated by Note that NSEi is an inverted signal of SEi that is output for use in generating a partial product. Here, i is 0, 2, 4, 6, 8, 10, 12, and 14, and the output of the data selecting means 11 is input to Y-1.

FIG. 8 is a block diagram showing the structure of the multiplying means 13. Reference numeral 300 in FIG. 8 indicates a multiplicand extension unit, reference numeral 301 indicates a partial product generation unit, and reference numeral 302 indicates a partial product addition unit. Multiplicand expansion means 300
Outputs the most significant bit X [15] of the multiplicand when the multiplicand determination signal C1 takes a value "0", and outputs the value "0" when the multiplicand determination signal C1 takes a value "1". The partial product generation means 301 generates a partial product from the output of the multiplier encoding means 12, the output of the multiplicand expansion means 300, and the multiplicand X. The partial product addition means 302 adds the partial products generated by the partial product generation means 301 to obtain a multiplication result. Since there is no data obtained by multiplication at the digit position of bit 0 which is the least significant bit, the value "0" is obtained. Is added and output.

FIG. 9 shows the multiplicand expanding means 30 of the multiplying means 13.
FIG. 3 is a circuit diagram showing a circuit configuration of a zero and partial product generation means 301. Reference numeral 303 in FIG. 9 denotes a partial product sign bit inversion generating circuit that generates a bit inversion of the sign bit of the generated partial product, reference numeral 304 denotes a partial product generation circuit per bit, and reference numeral 305 denotes a correction term. 5 shows a partial product correction term generation circuit that generates PPH. 1 of the most significant bit of the multiplicand
When the multiplicand discrimination signal C1 has a value "0", the sign bit of the multiplicand is output as it is, and when the multiplicand discrimination signal C1 has a value "1", a value "0" is output. When the encoding result BEi is positive, the sign-extended multiplicand is selected as it is, and when it is negative, bit inversion is selected. The composite gate outputs the selected value of each bit when the encoding result BEi is 1 or -1, and outputs the selected value one bit lower when the encoding result BEi is 2 or -2.
When i is 0, 0 is output. The output of the composite gate is the output PPOn of bit n of the partial product to be generated. The correction term PPH for two's complement is calculated by the control signals NSEi, 2Ei and 1Ei
It is generated by taking the logical AND of negation. This is true when the encoding result BEi is -1 or -2, and is output at the least significant bit digit position of the generated partial product.

FIG. 10 is a schematic diagram for explaining the multiplication process.
It is. In FIG. 10, symbols D, E, F, G, H,
I, J, and K indicate the generated eight partial products, respectively.
The symbol Z is the product of the multiplicand X and the multiplier Y. In FIG.
2 shown at the top of¹, 2 ⁰, 2^-1, ..., 2^-31Is
The scale at each digit position is shown. Also show the data
The horizontal line above the symbol indicates bit inversion. Where the figure
The value “1” shown in 10 is added in place of sign extension.
It is the data to be calculated.

By adding the value "1" shown in FIG. 10 to the bit inversion of the sign bit of each partial product indicated by the preceding line, the digit position of the sign bit is adjusted when the partial products are added. Processing equivalent to the sign extension that needs to be performed. This is a commonly used method and will not be described in detail here. In the multiplication means 13, partial products are generated by a partial product generation means 301 as shown in FIG. 10, and they are added by a partial product addition means 302. Note that the relationship between the numbers assigned to the respective partial product components in FIG. 10 and the numbers assigned to the components of the output data Z is shifted by one bit due to the position of the decimal point. Furthermore, each of the partial products to digit position of 2 ^-31 is output is always the value "0" in Z0 since no data.

Here, in the arithmetic unit of this embodiment in which the multiplication result holding means 17 for holding the multiplication result is arranged between the multiplication means 13 and the addition means 14, the multiplication of the double precision data by the double precision data Table 1 shows instructions for executing multiplication of precision data and single precision data.

[0053]

[Table 1] By sequentially executing the instructions A to D shown in Table 1, four products XL × YL, XH × YL, XL × YH,
XH × YH are sequentially obtained, and the multiplication of the double-precision data and the double-precision data is performed by digit-aligning and adding them. Further, by sequentially executing the instructions of E and F shown in Table 1, two products XL × YH and XH × YH are sequentially obtained, and multiplication of the double precision data and the single precision data is performed by adding digits. . Table 1 shows data flows and processing contents in the multiplier encoding process by the MSB holding unit 10, the data selection unit 11, and the multiplier encoding unit 12, the multiplication process by the multiplication unit 13, and the addition process by the addition unit 14 and the digit matching unit 16. Is shown. Here, R0 in Table 1 indicates the MSB holding unit 10, R1 indicates the multiplication result holding unit 17, and R2 indicates the addition result holding unit 15.

In Table 1, each instruction is a two-cycle instruction. In the column of the encoding process, data stored in the MSB holding unit 10 and data selected by the data selecting unit 11 are shown, and the description in parentheses (YL in the instructions C and D) is shown.
[15]) indicates data held in the MSB holding means 10 at the time of execution of the instruction. In the column of the multiplication process, the multiplication result obtained by the multiplication means 13 is shown. In the column of addition processing, the data selected by the digit alignment means 16 and the presence / absence of 16-bit right shift processing for digit alignment,
4 shows the addition result obtained.

As described above, according to the first embodiment,
The multiplication result of the multiplication means 13 is output with a bit width at least one bit larger than the double precision bit width by having at least two or more digits higher than the decimal point position. When the multiplication using the multiplicand lower word as the source is performed, the circuit scale of the digit aligning means 16 is smaller than that of the conventional example such that the shift number for Therefore, the 1-bit right shift means required to output the multiplication result with 32-bit precision becomes unnecessary.

Further, by providing the multiplication result holding means 17 and operating the multiplication means 13 and the addition means 14 in parallel, the calculation time can be reduced. [Second Embodiment] A second embodiment of the present invention will be described below. The configuration of the second embodiment is different from the first embodiment in that the multiplier encoding means 12 forcibly sets the least significant bit of the multiplier input when the multiplier control signal C3 takes the value "1" to the value. The multiplication means 13 is configured to have a function of setting to “0”, and the multiplication means 13
Has a function of forcibly setting the least significant bit of the multiplicand that is input when takes a value “1” to a value “0”.

FIG. 11 is a diagram showing a circuit configuration of the multiplier encoding means 12 according to the second embodiment. Reference numeral 201 in FIG. 11 denotes multiplier control means for forcibly setting the least significant bit of the multiplier to a value "0" when the multiplier control signal C3 takes a value "1". When the multiplier control signal C3 takes a value "1", the multiplier control means 201 performs a logical product of the least significant bit Y0 of the multiplier and the logical inversion of the multiplier control signal C3. Y0 is forcibly set to the value "0".

FIG. 12 is a block diagram showing a configuration of the multiplying means 13 in the second embodiment. Reference numeral 306 in FIG. 12 indicates that when the multiplicand control signal C4 takes a value “1”,
The multiplicand control means forcibly sets the least significant bit of the multiplicand to a value “0”. The multiplicand control means 306 calculates the logical product of the least significant bit X0 of the multiplicand and the logical inversion of the multiplicand control signal C4, so that when the multiplicand control signal C4 takes the value "1", the least significant bit X0 of the multiplicand. Is forcibly set to the value “0”.

The operation of the arithmetic unit configured as described above will be described. The following method is often used as a method for performing double precision multiplication using a single precision multiplier. In order to treat the multiplier lower word and the multiplicand lower word as single-precision signed binary fixed-point numbers, respectively, shift right by one bit and add a sign bit of a value “0” to the most significant bit as a sign indicating a positive number. , The least significant bit is truncated. For this reason, the result of multiplication of the double precision data and the double precision data is 31 bits × 31 bits, and the result of multiplication of the double precision data and the single precision data is 31 bits × 16 bits.

In the first embodiment, the multiplication of double-precision data and double-precision data can be performed with 32-bit × 32-bit precision, and the multiplication of double-precision data with single-precision data can be performed with 32-bit × 16-bit precision. it can. According to the second embodiment, in the configuration of the first embodiment, the multiplier encoding means 12 is provided with the multiplier control means 201 and the multiplier means 13 is provided with the multiplier means 13.
By adding a small circuit of providing a multiplicand control means 306 to the
Double precision multiplication of 1 bit × 16 bit precision can be executed.

By using the second embodiment, the arithmetic unit of the present invention has the function of forcibly setting the least significant bits of the multiplier and the multiplicand to the value "0", respectively.
Compatibility with applications using low-precision double-precision multiplication can be achieved. [Third Embodiment] A third embodiment of the present invention will be described below.

The configuration of the third embodiment is different from that of the first embodiment in that the MSB holding means 10 selects and holds the most significant bit of the multiplier when the held data selection signal C5 takes the value "1". When the held data selection signal C5 takes the value "0", the function of selecting and holding the value "0" is provided. Here, in the arithmetic device of the present embodiment in which the multiplication result holding means 17 for holding the multiplication result is arranged between the multiplication means 13 and the addition means 14, the multiplication of the double precision data and the double precision data, Table 2 shows instructions for executing multiplication of single precision data.

[0063]

[Table 2] By sequentially executing the instructions A to D shown in Table 2, the four products XL × YL, XH × YL, XL × YH,
XH × YH are sequentially obtained, and the multiplication of the double-precision data and the double-precision data is performed by digit-aligning and adding them. Further, by sequentially executing the instructions of A (E) and D (F) shown in Table 2, two products XL × YH and XH × YH are sequentially obtained, and double-precision data and single-precision data are obtained by adding digits. Is performed. Table 2 shows MSB holding means 10, data selecting means 11, multiplier encoding means 12
2 shows the flow of data and the contents of processing in the multiplier encoding process by the multiplication unit 13, the multiplication process by the multiplication unit 13, and the addition process by the addition unit 14 and the digit matching unit 16. Here, R0 in Table 2 indicates the MSB holding unit 10, R1 indicates the multiplication result holding unit 17, and R2 indicates the addition result holding unit 15.

In Table 2, each instruction is a two-cycle instruction. In the column of the encoding process, data stored in the MSB holding unit 10 and data selected by the data selecting unit 11 are shown, and the description in parentheses (YL in the instructions C and D) is shown.
[15] and 0) in the instruction D (F)
2 shows data held in the SB holding unit 10. In the column of the multiplication process, the multiplication result obtained by the multiplication means 13 is shown. In the column of the addition processing, the data selected by the digit alignment means 16, the presence / absence of 16-bit right shift processing for digit alignment, and the addition result obtained by the addition means 14 are shown.

Here, in comparison with Table 1 shown above, in Table 2, the data stored in the MSB holding means 10 by the instruction A is set to the value “0”. Thus, the multiplication of the double precision data and the single precision data can be realized by the combination of the instruction A and the instruction D. Therefore, according to the third embodiment, the number of instructions required to execute multiplication of double-precision data and double-precision data and multiplication of double-precision data and single-precision data can be reduced by sharing instructions. .

[0066]

According to the operation method of the present invention, the digit alignment of each product obtained with a bit width at least one bit larger than the double precision bit width by having at least two digits higher than the decimal point position. The number of shifts is relatively limited to the same bit width, so that the circuit scale of the digit aligning means can be reduced and double precision multiplication can be realized efficiently.

According to the arithmetic unit of the present invention, since the multiplication means has at least two or more digits higher than the decimal place, the multiplication means outputs the multiplication result with a bit width at least one bit larger than the double precision bit width. The number of shifts for digit alignment of each multiplication result is relatively limited to the same bit width, so that the circuit scale of the digit alignment means can be reduced and efficient double precision multiplication can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an arithmetic device according to a first embodiment of this invention.

FIG. 2 is a schematic diagram for explaining data division of a double precision multiplier.

FIG. 3 is a schematic diagram for explaining a data output format of a product of a multiplicand upper word and a multiplier upper word / lower word.

FIG. 4 is a schematic diagram for explaining a data output format of a product of a multiplicand lower word and a multiplier upper word / lower word.

FIG. 5 is a schematic diagram for explaining a conventional digit alignment bit shift.

FIG. 6 is a schematic diagram for explaining a digit alignment bit shift according to the first embodiment of this invention.

FIG. 7 is a circuit diagram showing a circuit configuration of multiplier encoding means.

FIG. 8 is a block diagram illustrating a configuration of a multiplication unit.

FIG. 9 is a circuit diagram showing a circuit configuration of a multiplicand expansion unit and a partial product generation unit of the multiplication unit.

FIG. 10 is a schematic diagram for explaining a multiplication process.

FIG. 11 is a circuit diagram showing a circuit configuration of multiplier encoding means according to the second embodiment of the present invention.

FIG. 12 is a block diagram illustrating a configuration of a multiplying unit according to a second embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 MSB holding means 11 Data selection means 12 Multiplier edge code means 13 Multiplication means 14 Addition means 15 Addition result holding means 16 Digit alignment means 17 Multiplication result selection means 18, 19 Selection means 20 Storage means 200 Booth encoding means 201 Multiplier control means 300 Multiplicand expansion means 301 Partial product generation means 302 Partial product addition means 303 Partial product sign bit inversion generation circuit 304 Partial product generation circuit 305 Partial product correction term generation circuit 306 Multiplicand control means

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[Procedure amendment]

[Submission date] September 10, 1998

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0053

[Correction method] Change

[Correction contents]

[0053]

[Table 1] By sequentially executing the instructions A to D shown in Table 1, 4
Product XL × YL, XH × YL, XL × YH, XH × Y
By multiplying the double precision data and the double precision data by sequentially obtaining H and digit-aligning and adding them, multiplication is performed. Also,
By sequentially executing the instructions E and F shown in Table 1, two products XL × YH and XH × YH are sequentially obtained, and multiplication of the double precision data and the single precision data is performed by adding digits. Table 1 shows the data flow and processing contents in the multiplier encoding process by the MSB holding unit 10, the data selection unit 11, and the multiplication encoding unit 12, the multiplication process by the multiplication unit 13, and the addition process by the addition unit 14 and the digit matching unit 16. Is shown. Here, R0 in Table 1 is MS
The B holding means 10 is shown, R1 is the multiplication result holding means 17, and R2 is the addition result holding means 15.

[Procedure amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0063

[Correction method] Change

[Correction contents]

[0063]

[Table 2] By sequentially executing the instructions A to D shown in Table 2, 4
Product XL × YL, XH × YL, XL × YH, XH × Y
By multiplying the double precision data and the double precision data by sequentially obtaining H and digit-aligning and adding them, multiplication is performed. Also,
By sequentially executing the instructions of A (E) and D (F) shown in Table 2, two products XL × YH and XH × YH are sequentially obtained.
The multiplication of the double precision data and the single precision data is performed by performing the digit addition. Table 2 shows the data flow and processing contents in the multiplier encoding process by the MSB holding unit 10, the data selection unit 11, and the multiplication encoding unit 12, the multiplication process by the multiplication unit 13, and the addition process by the addition unit 14 and the digit matching unit 16. Is shown. Here, R0 in Table 2 indicates the MSB holding unit 10, R1 indicates the multiplication result holding unit 17, and R2 indicates the addition result holding unit 15.

Claims (15)

[Claims] 1. A binary fixed-point number system in which a most significant bit is a sign bit and a decimal point position is between the most significant bit and one bit lower than the most significant bit, using a single precision multiplier. High-order word of double precision multiplicand /
An arithmetic method for obtaining a product of each of a lower word and an upper word / lower word of a double precision multiplier, and performing a digit-matching addition on each of the obtained products to obtain a double precision multiplication result, wherein the upper word of the double precision multiplicand is obtained. The product of each of the / lower word and the upper word / lower word of the double precision multiplier has a bit width at least one bit larger than the double precision bit width by having at least two digits higher than the decimal point position. Characteristic calculation method. 2. The single-precision multiplier, when calculating the product of the lower word of the double-precision multiplicand and the lower word of the double-precision multiplicand, adds a positive number one bit higher than the most significant bit of the lower word of the double-precision multiplicand. The multiplication of data having a bit width that is one bit larger than the single precision bit width and a single precision bit width data having the most significant bit of the lower word of the double precision multiplier as a sign bit having a sign bit indicating that Then, data of a value “0” is added to the lower bit of the least significant bit of the multiplication result having the double precision bit width, and data having a bit width one bit larger than the double precision bit width is added to the lower word of the double precision multiplicand. 2. The method according to claim 1, wherein the output is performed as a product of lower words of the double precision multiplier. 3. The single-precision multiplier, when calculating a product of an upper word of the double-precision multiplicand and a lower word of the double-precision multiplicand, encodes a sign bit of an upper-order word of the double-precision multiplicand by a one-bit code. Multiplying the expanded data having a bit width one bit larger than the single precision bit width and single precision bit width data having the most significant bit of the lower word of the double precision multiplier as a sign bit, The data having a value “0” is added to the lower one bit of the least significant bit of the multiplication result, and the data having a bit width one bit larger than the double precision bit width is transferred to the upper word of the double precision multiplicand and the lower word of the double precision multiplier The method according to claim 1, wherein the output is a product of 4. When calculating the product of the lower word of the double-precision multiplicand and the upper word of the double-precision multiplier, the single-precision multiplier adds a positive number one bit higher than the most significant bit of the lower word of the double-precision multiplicand. Having a sign bit indicating that the bit width is one bit larger than the single precision bit width, and the same as the least significant bit of the lower word of the double precision multiplier at the digit position of the lower word of the upper word of the double precision multiplier Multiplies data with a single-precision bit width to which data having a value is added, and adds data with a value “0” to the lower bit of the multiplication result having a double-precision bit width, and adds data with a value “0” to the double-precision bit The method according to claim 1, wherein data having a bit width one bit larger than the width is output as a product of a lower word of the double precision multiplicand and an upper word of the double precision multiplier. 5. The single-precision multiplier, when calculating the product of the high-order word of the double-precision multiplicand and the high-order word of the double-precision multiplicand, codes the sign bit of the high-order word of the double-precision multiplicand by one bit. Expanded data having a bit width one bit larger than the single precision bit width, and data having the same value as the least significant bit of the lower word of the double precision multiplier are added to the digit position of the lower word of the upper word of the double precision multiplier. , Multiplies with single precision bit width data, adds the value “0” to the least significant bit one bit lower than the least significant bit of the multiplication result having double precision bit width, and increases the bit width by one bit larger than the double precision bit width 2. The method according to claim 1, wherein the data is output as a product of an upper word of the double precision multiplicand and an upper word of the double precision multiplier. 6. An arithmetic unit for performing double-precision multiplication using a single-precision multiplier for multiplying two signed binary fixed-point data, comprising: MSB holding means for holding the most significant bit of the multiplier; A data selecting means for selecting and outputting one of the data held by the MSB holding means and a value “0”; and a multiplier for encoding and outputting the multiplier using the multiplier and output data of the data selecting means. Encoding means, a multiplicand, output data of the multiplier encoding means, and a multiplicand discrimination signal are input, and if the multiplicand discrimination signal is in an inactive state, the most significant bit of the multiplicand is set to 1
The bit code is extended to obtain a result of multiplication with the output data of the multiplier encoding means. If the multiplicand discrimination signal is in an active state, a sign bit indicating that it is a positive number one bit higher than the most significant bit of the multiplicand is added. In addition, a multiplication result with the output data of the multiplier encoding means is obtained, and the obtained multiplication result has at least two or more digits higher than the decimal point position, so that at least one digit is larger than the double precision bit width.
A multiplication means for outputting with a bit width larger than a bit, an output data of the multiplication means being an addend, and having at least two or more digits higher than the decimal point, thereby providing a bit width at least one bit larger than the double precision bit width. An addition means for performing addition with the augend to have the addition and outputting an addition result having a bit width at least one bit larger than a double precision bit width by having at least two digits higher than the decimal point position; An addition result holding means for holding the addition result output by the means; and one of the data held by the addition result holding means and the value "0" is selected, digit alignment processing is performed, and the result is output as the augend of the addition means. An arithmetic unit comprising a digit matching unit. 7. The MSB holding means holds the most significant bit of the double-precision multiplier low word when calculating the product of the double-precision multiplier low word and the double-precision multiplicand high word / low word in the execution of double-precision multiplication. The arithmetic device according to claim 6, wherein: 8. The data selecting means selects and outputs the value “0” when calculating the product of the double precision multiplier lower word and the double precision multiplicand upper word / lower word in the execution of the double precision multiplication, and outputs the value “0”. Word and double precision multiplicand high word /
7. The arithmetic unit according to claim 6, wherein when calculating the product with the lower word, the most significant bit of the double precision multiplier lower word held by the MSB holding means is selectively output. 9. The multiplier encoding means includes: a double-precision multiplier low-order word input when calculating a product of a double-precision multiplier low-order word and a double-precision multiplicand high-order word / low-order word in performing double-precision multiplication; The output data of the selected value “0” is encoded and output by Booth's algorithm, and the data selected by the data selection means when the product of the double precision multiplier upper word and the double precision multiplicand upper word / lower word is obtained. 7. The arithmetic unit according to claim 6, wherein the output data of the most significant bit of the double precision multiplier low-order word held by the MSB holding means is encoded by a Booth algorithm and output. 10. The multiplication means determines that the input multiplicand is the lower word of the double precision multiplicand if the multiplicand discrimination signal is active in the execution of the double precision multiplication, and outputs one bit of the most significant bit of the multiplicand. A sign bit indicating a positive number is added to the upper part to obtain a partial product with the output data of the multiplier encoding means. If the multiplicand discrimination signal is inactive, the input multiplicand is the upper word of the double precision multiplicand. 7. A partial product generation means for determining a partial product with output data of the multiplier encoding means by performing one-bit sign extension of a code bit which is a most significant bit of the multiplicand. Arithmetic unit. 11. The multiplication means includes at least two of the partial product generation means, adds partial products, which are output data of the plurality of partial product generation means, at the same digit positions, and adds the least significant bit of the addition result. 7. The arithmetic unit according to claim 6, wherein data of a value "0" is added one bit lower and output as a product. 12. The output data of the multiplication means is temporarily stored,
7. The arithmetic unit according to claim 6, further comprising a multiplication result holding unit that outputs the result as an addend of the addition unit, wherein the multiplication unit and the addition unit can operate in parallel. 13. The arithmetic unit according to claim 6, wherein the multiplier encoding means has a function of forcibly setting a least significant bit of the multiplier as input data to a value “0”. 14. The arithmetic unit according to claim 6, wherein the multiplying means has a function of forcibly setting the least significant bit of the multiplicand as input data to a value “0”. 15. The MSB holding means is means for selecting and holding one of the most significant bit of the multiplier and a value “0” instead of the means for holding the most significant bit of the multiplier. The arithmetic unit according to claim 6.