JPH1185672A - Data transmission equipment - Google Patents

Abstract

(57) [Summary] [PROBLEMS] To provide a data transmission device for arranging an interface on a data bus of a computer system and inputting / outputting data, in which data transmission is performed mainly by a main memory frequently accessed by a CPU. And sufficient performance cannot be obtained due to contention for access to the main memory. An object of the present invention is to provide a data transmission device capable of fully utilizing the data transmission capability of a bus without being limited by such restrictions. SOLUTION: A bus is provided with a data-only memory which can be written and read from a disk interface and an AV interface.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer apparatus for storing and supplying a plurality of image and audio data simultaneously in response to an external request, and more particularly to a video server.

[0002]

2. Description of the Related Art With the rapid development of microcomputer technology, video and audio data handled by dedicated hardware can now be handled by general-purpose computer hardware. Similarly, in a data transmission device called a video server, a configuration based on computer hardware as shown in the block diagram of FIG. 10 as an example has become possible (for example, Japanese Patent Application No. Hei 8-30890).
No. 3).

[0003] That is, a CPU 1001, a bus 1002, and a main memory 1003 are provided.
04 tied. On the bus 1002, there is a communication interface 10 for receiving a command for data transmission from outside.
05 and a disk interface 1007 which is an interface between the disk device 1006 where data is recorded and reproduced.
And an AV interface 1008 for exchanging data with an external data transmission / reception device 1009. Each interface placed on these buses 1002 is a CPU
An interrupt signal is used to request 1001 to start processing for each interface. An interrupt signal output from each interface is input to an interrupt controller 1010, where the interrupt signal is subjected to processing such as prioritization, and then sent to the CPU 1001 to make an interrupt request to the CPU 1001.

[0004] A process in which the data transmission device shown in FIG. 10 records data on the disk device 1006 will be described.

First, a recording command is transmitted to the communication interface 1005. The communication interface 1005 generates an interrupt signal to notify the CPU 1001 that the command has been received. The interrupt signal generated by the communication interface 1005 passes through the interrupt controller 1010 to the CP.
In response to this, the CPU 1001 responds to the command and arrives at the communication interface.
Through 04, read from the communication interface 1005 on the bus 1002.

[0006] The CPU 10 understands that the command is a record.
01 is a main memory for transmitting data sent from an external data transmitting / receiving device 1009 to the AV interface 1008.
Command to write to 1003. After receiving the data, the AV interface 1008 acquires the right to use the bus 1002, and writes the data received through the bus interface 1004 to the main memory 1003. When the writing is completed, an interrupt signal is generated to notify the CPU 1001 of the completion. The interrupt signal generated by the AV interface 1008 is transmitted to the CPU 1001 via the interrupt controller 1010.

In response to this, the CPU 1001 sends the AV interface 10 to the disk interface 1007.
08 is instructed to write the data written in the main memory 1003 to a predetermined position of the disk device 1006. The disk interface 1007 obtains the right to use the bus 1002, and reads data from the main memory 1003 through the bus interface 1004. Then, the read data is written to the position specified by the CPU 1001 of the disk device 1006. When the writing is completed, an interrupt signal is generated to notify the CPU 1001 of the completion. The interrupt signal generated by the disk interface 1007 is transmitted to the CPU 1001 via the interrupt controller 1010. Through the above series of operations, data is recorded from the external data transmitting / receiving apparatus 1009 to the data transmission apparatus.

[0008] Next, a process in which the data transmission apparatus shown in FIG. 10 reproduces data to the data transmission / reception apparatus 1009 will be described.
First, a reproduction command is transmitted to the communication interface 1005. The communication interface 1005 generates an interrupt signal to notify the CPU 1001 that the command has been received. The interrupt signal generated by the communication interface 1005 is transmitted to the CPU 1001 via the interrupt controller 1010, and the CPU 1001 responds to the instruction and reaches the communication interface via the bus interface 1004.
Read from communication interface 1005 on bus 1002.

The CPU 10 that understands that the command is a record
01 instructs the disk interface 1007 to write data recorded at a predetermined position of the disk device 1006 to the main memory 1003. After reading the data from the disk device 1006, the disk interface 1007 acquires the right to use the bus 1002, and writes the data received through the bus interface 1004 to the main memory 1003. When the writing is completed, an interrupt signal is generated to notify the CPU 1001 of the completion. The interrupt signal generated by the disk interface 1007 is transmitted to the CPU 1001 via the interrupt controller 1010.

[0010] In response to this, the CPU 1001 sends a disc interface 10 to the AV interface 1008.
An instruction is issued to output the data on the main memory 1003 written by 07 to the external data transmitting / receiving device 1009. The AV interface 1008 obtains the right to use the bus 1002 and transfers data to the main memory 10 through the bus interface 1004.
Read from 03. Then, the read data is output to the data transmitting / receiving device 1008. When this is completed,
An interrupt signal is generated to notify U1001. AV
The interrupt signal generated by the interface 1008 is transmitted to the CPU 1001 via the interrupt controller 1010.

By the above series of operations, the disk drive 10
From 06, data is reproduced to the external data transmission / reception device 1009.

[0012]

The main memory 1003 contains command words executed by the CPU 1001 and data different from those handled as the data transmission device described above.
At the same time, the main memory 1003 is
Receive write and read from various interfaces on 02. That is, the bus interface 1004
An access request from the PU 1001 to the main memory 1003,
It arbitrates for access requests from the bus 1002 and responds to access requests from both parties.

However, in recent years, as the functions of the CPU 1001 have become more sophisticated, the frequency of access to the main memory 1003 by the CPU 1001 has been increased, and a hierarchical storage mechanism, that is, a cache memory mechanism has been incorporated.
Therefore, the priority of the access request to the main memory 1003 tends to decrease. As a result, the response time to the write and read requests from the interfaces on the bus 1002 to the main memory is lengthened, and the speed of the write and read itself is reduced. This indicates that the amount of data that can be handled per unit time in the operation as the data transmission device described above decreases. Although there is enough room for the transfer capability of the bus, the data transmission capability is restricted due to access competition in the main memory.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problem, and is intended to provide a bus transfer capability to a main memory.
An object of the present invention is to provide a data transmission device that is not restricted by access competition with a PU.

[0015]

According to a first aspect of the present invention, there is provided a communication interface connected to a bus and receiving an external data transmission command.
A disk device for recording and reproducing data, a disk interface for interfacing the disk device with the bus, an AV interface for interfacing the external data transmitting and receiving device with the bus, a bus interface directly connected to the bus, and data from the disk interface and the AV interface An AV data memory for writing and reading data, and a CP for receiving an interrupt request signal issued from the communication interface, the disk interface, and the AV interface.
It has an interrupt controller for transmitting to U.

According to a second aspect of the present invention, there is provided a disk device for recording and reproducing data, a disk interface for interfacing the disk device with a bus, and an A for interfacing an external data transmitting and receiving device with a bus.
A V interface, an AV data memory directly connected to the bus, for writing and reading data from the bus interface, the disk interface and the AV interface, and an external data transmission command connected to the bus for receiving the external data transmission command. A communication interface for reading and writing data; and an interrupt controller for receiving an interrupt request signal issued from the communication interface, the disk interface, and the AV interface and transmitting the interrupt request signal to the CPU.

According to a third aspect of the present invention, there is provided a communication interface connected to a bus for receiving an external data transmission command, a disk device for recording and reproducing data, and a disk interface for interfacing the disk device with the bus. An AV interface for interfacing with an external data transmission / reception device, and two ports, one of which is directly connected to a bus for writing and reading data from a bus interface and a disk interface, and the other of which is an AV interface An AV data memory for writing and reading data from and an AV data memory interrupt for generating an interrupt signal when the condition is satisfied by comparing the writing and reading status to the AV data memory with a preset condition The CP receives the means, the interrupt request signal generated from the communication interface and the disk interface and AV data memory interrupt generation means
It has an interrupt controller for transmitting to U.

According to a fourth aspect of the present invention, there is provided a communication interface connected to a bus for receiving an external data transmission command, a disk device for recording and reproducing data, and a disk interface for interfacing the disk device with the bus. An AV interface for interfacing a bus with an external data transmission / reception device, an AV data memory directly connected to the bus for writing and reading data from the bus interface, a disk interface and the AV interface, a communication interface, a disk interface and an AV A first interrupt controller for receiving an interrupt request signal issued from the interface and transmitting the interrupt request signal to the CPU; A second interrupt controller for receiving an interrupt request signal and transmitting the interrupt request signal to a communication interface, and an interrupt signal selecting means for distributing an interrupt request signal issued from the disk interface and the AV interface to the first interrupt controller or the second interrupt controller. It is.

According to the above configuration, the data transmission capability according to the transfer capability of the bus can be exhibited without being limited by the access state of the CPU to the main memory.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to FIGS. It should be noted that recording and reproduction are performed in exactly the reverse steps in the present invention, and thus the following description will be given of the reproduction process. Further, in a form called a normal video server, a plurality of data transmissions are usually performed simultaneously and in parallel, but in the following description, one channel will be described.

(Embodiment 1) FIG. 1 shows (Embodiment 1).
1 is a block diagram of a data transmission device of the present invention in FIG.

In FIG. 1, components having the same functions as those in FIG. 10 are denoted by the same reference numerals as in FIG. 10, and description thereof will be omitted. In FIG. 1, reference numeral 101 denotes an AV data memory,
Data is written and read from the CPU 1001 via the disk interface 1007, the AV interface 1008, and the bus interface 1004 on the bus 1002.

The operation of the data transmission apparatus configured as described above will be described below. FIG. 2 is a flowchart showing the operation of the data transmission device of FIG.

In step 201, each interface on the bus 1002 is initialized. The following initialization is performed on the AV data memory 101. Since the address of the AV data memory 101 can be freely rearranged by changing the set value of an internally provided address register, the CPU 1001 determines the address used by the main memory 1003 and the address used by the AV data memory. The address of the AV data memory is set so that the addresses to be copied do not overlap. And
The set address is stored so that it can be referred to in the processing described later.

In step 202, the flow waits for an interrupt signal generated by the communication interface 1005 due to the arrival of an external command. If an interrupt signal arrives, the process proceeds to step 203 to read the reproduction instruction that has arrived at the communication interface.

In the process 204, the position of the data to be reproduced in the disk device 1006 is calculated,
The address of the V data memory 101 to which the data is to be written is determined.

In process 205, the disk interface 1
007 is instructed to read from the disk device 1006 based on the result obtained in the process 204.

In process 206, the disk interface 1
007 reads data from the disk device 1006 and
After the work of writing to a predetermined address of the data memory 101 is completed, the process waits for an interrupt signal to be generated. When an interrupt signal is generated, the process proceeds to step 207.

In the process 207, the contents of the data to be reproduced are rewritten for the portions that need to be rewritten for the reproduction. For example, time code information including reproduction time information, and information called a sequence number indicating the order of reproduction need to be newly rewritten for each reproduction.

In process 208, the AV interface 1008
Is instructed to read data from the AV data memory 101 and output it to the external data transmitting / receiving device 1009.

In process 209, the AV interface 1008
Waits for data to be read from the AV data memory 101 and output to the data transmission / reception device 1009. Upon completion, the process returns to the process 202 and waits for the arrival of a command from the outside to the communication interface 1005 again.

By performing a series of processes as described above, data transmission can be performed without storing data to be output from the AV interface in the main memory 1003. As a result, the data moves only on the bus 1002 without competing with the access from the CPU 1001 to the main memory 1003.Therefore, the transfer speed of the data is restricted by the writing and reading speed to and from the main memory 1003. I do not receive.

(Embodiment 2) FIG. 3 shows (Embodiment 2)
1 is a block diagram of a data transmission device of the present invention in FIG.
As in (Embodiment 1), components in FIG. 3 that perform the same functions as in FIG. 1 are given the same numbers as in FIG.
Description is omitted.

The difference between (Embodiment 2) and (Embodiment 1) is that, in (Embodiment 2), a bus master circuit (hereinafter, referred to as a BM circuit) is provided in a communication interface 1005 as shown in FIG. It has 301). The BM circuit adds a function of actively reading and writing to the AV data memory 101 and the main memory 1003 on the bus 1002 to the block. That is,
Bus interface 1004, disk interface
1007 and the AV interface 1008 are already included in the conventional example of FIG. In FIG. 3 (Embodiment 2), this BM circuit is also provided in the communication interface 1005.

The operation of the data transmission apparatus configured as described above will be described below. FIG. 4 is a flowchart showing the operation of the data transmission device of FIG.

In the process 401, each interface on the bus 1002 is initialized. With respect to the AV data memory 101, the address can be freely rearranged by the set value of the register in the AV data memory 101, so that the CPU 1001 stores the AV address in the address position where the address does not overlap with the main memory 1003. Set the data memory address.

In the process 402, the A set in the process 401
Communication interface 1
Notify 005. In the process 403, the process waits for an interrupt signal generated by the communication interface 1005 to arrive. In the second embodiment, the communication interface generates an interrupt under two conditions, that is, when an external command is received and when rewriting of data in the AV data memory is completed. When an interrupt signal arrives, the process proceeds to step 404,
Reads the cause of the interrupt generated by the communication interface.

The process 405 branches depending on the cause of the interrupt read in the process 404. If the interruption from the communication interface 1005 is related to the reception of an external command, the process proceeds to step 406, and if the rewriting of the AV data memory 101 is completed, the process proceeds to step 410.

In the process 406, the position of the data to be reproduced in the disk device 1006 is calculated, and
The address of the V data memory 101 to which the data is to be written is determined.

In process 407, the disk interface 1
007 is instructed to read from the disk device 1006 based on the result obtained in the process 406.

In process 408, the disk interface 1
007 reads data from the disk device 1006 and
After the work of writing to a predetermined address of the data memory 101 is completed, the process waits for an interrupt signal to be generated. If an interrupt signal is generated, the process moves to processing 409.

In the process 409, the communication interface 1005 issues a command to rewrite the contents of the data to be reproduced based on the contents notified in the process 402, for the portion that needs to be rewritten in the reproduction.
The process 403 waits for the completion.

In process 410, the AV interface 1008
Is instructed to read data from the AV data memory 101 and output it to the external data transmitting / receiving device 1009.

In the process 411, the AV interface 1008
Waits for data to be read from the AV data memory 101 and output to the data transmission / reception device 1009. Upon completion, the process returns to step 403 and waits for the arrival of a command from the communication interface 1005 again.

By performing a series of processes as described above, the main memory 1003 stores A in the same manner as in the first embodiment.
Data transmission can be performed without storing data to be output from the V interface. Therefore, the transfer speed of the data is not restricted by the writing speed and reading speed of the main memory 1003.

Further, since the data rewriting process performed in the process 409 is performed by the communication interface 1005, the CPU 1001 does not need to be involved in the data exchanged between the disk device 1006 and the AV interface 1008 at all. Therefore, even during the rewriting process by the communication interface 1005, the main memory 10
03 can be accessed, and it is possible to perform processing other than the series of processing shown in FIG. 4, for example, processing related to data transfer of another channel that is performed simultaneously and in parallel. Can be processed more, and the number of data transmissions that can be handled simultaneously can be improved.

(Embodiment 3) FIG. 5 shows (Embodiment 3)
1 is a block diagram of a data transmission device of the present invention in FIG.
As in (Embodiment 1), components in FIG. 5 that perform the same functions as in FIG. 1 are given the same numbers as in FIG.
Description is omitted.

The difference between (Embodiment 3) and (Embodiment 1) is that, as shown in FIG. 5, in (Embodiment 3), an AV data memory 501 having two ports,
It has an AV data memory interrupt generation circuit 502 that generates an interrupt signal based on the write / read status to / from the V data memory 501, and the AV interface 1008 is connected to the port on the opposite side of the bus 1002 of the AV data memory 501 That is being done.

FIG. 6 is a block diagram showing the configuration of the AV data memory interrupt generation circuit. In FIG. 6, reference numeral 601 denotes an address decoder, which decodes an address sent via the bus 1002, and sends the address to the preset register 602 via the bus 1002 when the address matches the address of the preset register 602. An enable signal is generated so as to hold incoming address data. The address comparator 603 reads and writes addresses to and from the AV data memory and a preset register.
The address data stored in 602 is compared, and if they match, an interrupt signal is generated.

The operation of the data transmission apparatus configured as described above will be described below. FIG. 7 is a flowchart showing the operation of the data transmission device of FIG.

In the process 701, each interface on the bus 1002 and the AV data memory interrupt generation circuit 502 are initialized. The following initialization is performed on the AV data memory 101. The address of the AV data memory 101 can be freely rearranged by changing the set value of an internally provided address register.
1001 sets the address of the AV data memory so that the address used by the main memory 1003 and the address used by the AV data memory do not overlap. Then, the set address is stored so that it can be referred to in processing described later.

The following initialization is performed on the AV data memory interrupt generation circuit 502. AV interface 1008
Sets the address data when reading from the AV data memory 501 is completed in the preset register 602 in the AV data memory interrupt generation circuit 502. As a result, when the reading of the AV interface 1008 is completed, an interrupt signal is generated.

In the process 702, the flow waits for an interrupt signal generated by the communication interface 1005 due to the arrival of a command from the outside. If an interrupt signal arrives, the process proceeds to step 703, where a reproduction command that has arrived at the communication interface is read.

In the process 704, the position of the data to be reproduced in the disk device 1006 is calculated, and
The address of the V data memory 501 to which the data is to be written is determined.

In processing 705, the disk interface 1
007 is instructed to read from the disk device 1006 based on the result obtained in the process 704.

In processing 706, the disk interface 1
007 reads data from the disk device 1006 and
After the work of writing to a predetermined address of the data memory 501 is completed, the process waits for an interrupt signal to be generated. When an interrupt signal is generated, the process proceeds to step 707.

In the process 707, the contents of the data to be reproduced are rewritten for the portions which need to be rewritten for the reproduction. For example, time code information including reproduction time information, and information called a sequence number indicating the order of reproduction need to be newly rewritten for each reproduction.

In processing 708, the AV interface 1008
Reads data from the AV data memory 501 and waits for data to be output to the data transmitting / receiving apparatus 1009. Upon completion, since the AV data memory interrupt generation circuit 502 generates an interrupt signal, the process returns to step 702 and waits for the arrival of an external command to the communication interface 1005 again.

By performing a series of processes as described above, the main memory 1003 stores A in the same manner as in the first embodiment.
Data transmission can be performed without storing data to be output from the V interface. Therefore, the transfer speed of the data is not restricted by the writing speed and reading speed of the main memory 1003.

Further, since the AV data memory 501 has two ports, the data rewriting processing 707 for the AV data memory 501 and the reading of the AV interface 1008 can be performed in an overlapping manner. Since the data read from the disk device 1006 can be output from the AV interface 1008 with a shorter time delay, the number of data transmissions that can be handled simultaneously can be further improved.

As shown in (Embodiment 2), in FIG.
A circuit may be provided, and the data rewriting process 707 in FIG. 7 may be performed by the communication interface 1005. In this case, the effect obtained in (Embodiment 2) can also be obtained.

(Embodiment 4) FIG. 8 shows (Embodiment 4)
1 is a block diagram of a data transmission device of the present invention in FIG.
In FIG. 8, components that perform the same functions as those in the above-described embodiment are given the same reference numerals, and descriptions thereof will be omitted.

The difference between (Embodiment 4) and (Embodiment 1) is that, in (Embodiment 4), as shown in FIG. 8, an interrupt signal generated by the disk interface 1007 and the AV interface 1008 is generated. And a second interrupt controller 802 for receiving an interrupt signal from the selector 801. The communication interface 803 includes a second interrupt controller 802.
A microcomputer circuit (hereinafter referred to as MC circuit) 804 and a bus master circuit (hereinafter referred to as BM circuit) that operate based on a program built independently of the CPU 1001 at the same time as receiving an interrupt signal from the CPU 1001 It is.

The operation of the data transmission apparatus configured as described above will be described below. FIG. 9 is a flowchart showing the operation of the data transmission device of FIG. In the data transmission apparatus according to the fourth embodiment, there are two components that perform processing based on a program: the CPU 1001 and the MC circuit 804 in the communication interface 803. FIG. 9A shows the CPU 10
FIG. 9B is a flowchart of the MC circuit 804.

First, the flowchart of the CPU shown in FIG. 9A will be described. In the process 901, each interface on the bus 1002 is initialized. AV data memory
For 101, the address is the AV data memory 101
The CPU 1001 sets the address of the AV data memory at an address position where the address does not overlap with that of the main memory 1003 because the register can be freely rearranged by the setting value of the register inside the register.

In process 902, the A set in process 901
The address of the V data memory 101, the address of a register for giving a command necessary for reading and writing data to the disk interface 1007, and the command for reading and writing data to the AV interface 1008 The communication interface 1005 is notified of the addresses of the registers for this purpose.

In processing 903, the selector 801 is provided with a disk interface 1007 and an AV interface 10
08 from the second interrupt controller
Command to send to 802. As a result, the interrupt signal generated when the disc interface 1007 and the AV interface 1008 complete the processing instructed is C
The information is transmitted to the communication interface 803 via the second interrupt controller 802 instead of the PU 1001.

In the process 904, an interrupt from the communication interface 803 is waited. Processing when an interrupt signal arrives
Move to 905.

In the process 905, the contents of the inquiry from the communication interface 803 are recognized by reading the register in the communication interface 803. In accordance with the contents of the inquiry, the position of the data to be reproduced in the disk device 1006 is calculated, and the AV data memory 10
Determine which address of 1 to write the data to. Then, it is notified to the communication interface 803 by writing it into a register in the communication interface 803. Upon completion of the process, the process returns to the process 904 again and waits for an interrupt from the communication interface 803.

Next, the flowchart of the MC circuit shown in FIG. 9B will be described. In step 906, the process waits for the arrival of a command from the outside to the communication interface 803.
If a command arrives, the process moves to step 907, where the reproduction command arrived at the communication interface is read.

In the process 908, the information indicating the position of the data to be reproduced on the disk device 1006 and the data read from the disk device 1006 are stored in the AV data memory 101.
The CPU 1001 is inquired of information on which address to write to. Communication interface 80
3 prepares the contents of the inquiry in its internal register, and then generates an interrupt signal. The interrupt signal is transmitted to the CPU 1001 via the first interrupt controller 1010.

In the process 909, a response from the CPU 1001 is waited. If the answer is notified, the process moves to step 910.

In the process 910, the disk interface 1
007 is instructed to read from the disk device 1006 based on the result obtained in the process 908.

In process 911, the disk interface 1
007 reads data from the disk device 1006 and
After the work of writing to a predetermined address of the data memory 101 is completed, the process waits for an interrupt signal to be generated. When an interrupt signal is generated, the process proceeds to step 912.

In the process 912, the communication interface 803 performs processing based on the contents notified in the process 901 in FIG.
A rewriting process is performed on a portion that needs to be rewritten for reproduction.

In the process 913, the AV interface 1008
Is instructed to read data from the AV data memory 101 and output it to the external data transmitting / receiving device 1009.

In the process 914, the AV interface 1008
Waits for data to be read from the AV data memory 101 and output to the data transmission / reception device 1009. Upon completion, the process returns to step 906 and waits for the arrival of an external command to the communication interface 1005 again.

By performing the above-described series of processing, the main memory 1003 stores A in the same manner as in the first embodiment.
Data transmission can be performed without storing data to be output from the V interface. Therefore, the transfer speed of the data is not restricted by the writing speed and reading speed of the main memory 1003. Further, since all processing related to transmitting the data itself is performed by the communication interface 1005, the CP
It is possible to dedicate the capacity of U1001 solely to file system management processing on how data should be arranged on the disk device 1006. As a result, access to the disk device 1006 can be further optimized, and the number of data transmissions that can be handled simultaneously can be improved.

[0079]

As described above, according to the present invention, by eliminating the bottleneck portion of the structure of the existing computer, it is possible to further improve the performance while using the structure of the existing computer as it is.

[Brief description of the drawings]

FIG. 1 is a block diagram of a data transmission device according to a first embodiment of the present invention.

FIG. 2 is a flowchart showing a flow of an operation according to the first embodiment of the present invention;

FIG. 3 is a block diagram of a data transmission device according to a second embodiment of the present invention.

FIG. 4 is a flowchart showing a flow of an operation according to (Embodiment 2) of the present invention;

FIG. 5 is a block diagram of a data transmission device according to a third embodiment of the present invention.

FIG. 6 is a block diagram of an AV data memory interrupt generation circuit;

FIG. 7 is a flowchart showing an operation flow according to the third embodiment of the present invention.

FIG. 8 is a block diagram of a data transmission device according to (Embodiment 4) of the present invention;

FIG. 9 is a flowchart showing an operation flow according to (Embodiment 4) of the present invention;

FIG. 10 is a block diagram of a data transmission device according to a conventional example.

[Description of Signs] 101 AV data memory 301 Bus master circuit 501 AV data memory 502 AV data memory interrupt generation circuit 601 Address decoder 602 Preset register 603 Address comparator 801 Selector 802 Second interrupt controller 803 Communication interface 804 Microcomputer circuit 1001 CPU 1002 Bus 1003 Main memory 1004 Bus interface 1005 Communication interface 1006 Disk device 1007 Disk interface 1008 AV interface 1009 Data transceiver 1010 Interrupt controller

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Yoshihiro Morioka 1006 Kazuma Kadoma, Osaka Prefecture Matsushita Electric Industrial Co., Ltd.

Claims (4)

[Claims] At least one or more CPUs, and the CPU
A main memory for storing command words executed by the CPU and data processed by the CPU, a bus for exchanging data between a plurality of peripheral interfaces, and an interface between the CPU, the main memory, and the bus A data transmission device comprising a bus interface for performing data communication, a communication interface connected to the bus and receiving an external data transmission command, a disk device for recording and reproducing data, and an interface between the disk device and the bus. A disk interface, an AV interface for interfacing the bus with an external data transmitting / receiving device, and writing data from the bus interface, the disk interface, and the AV interface directly connected to the bus. A carried out write and read
A V data memory; an interrupt controller for receiving an interrupt request signal issued from the communication interface, the disk interface, and the AV interface, and transmitting the interrupt request signal to the CPU; data is transferred from the AV interface to the disk via the disk interface; When inputting and outputting, data is not stored in the main memory, but is performed through the AV data memory, and a correction operation of data stored in the AV data memory is performed by the CPU. Characteristic data transmission device. 2. At least one or more CPUs, and said CPU
A main memory for storing command words executed by the CPU and data processed by the CPU, a bus for exchanging data between a plurality of peripheral interfaces, and an interface between the CPU, the main memory, and the bus A data transmission device comprising a bus interface for performing data communication, a communication interface connected to the bus and receiving an external data transmission command, a disk device for recording and reproducing data, and an interface between the disk device and the bus. A disk interface, an AV interface for interfacing the bus with an external data transmitting / receiving device, and writing data from the bus interface, the disk interface, and the AV interface directly connected to the bus. A carried out write and read
A V data memory; an interrupt controller for receiving an interrupt request signal issued from the communication interface, the disk interface, and the AV interface, and transmitting the interrupt request signal to the CPU; data is transferred from the AV interface to the disk via the disk interface; When inputting and outputting data, the data is not stored in the main memory but is performed through the AV data memory, and the operation of correcting the data stored in the AV data memory is performed by the communication interface. A data transmission device characterized by the above-mentioned. 3. At least one or more CPUs, and said CPU
A main memory for storing command words executed by the CPU and data processed by the CPU, a bus for exchanging data between a plurality of peripheral interfaces, and an interface between the CPU, the main memory, and the bus A data transmission device comprising a bus interface for performing data communication, a communication interface connected to the bus and receiving an external data transmission command, a disk device for recording and reproducing data, and an interface between the disk device and the bus. A disk interface, an AV interface for interfacing with an external data transmission / reception device, and two ports, one of which is directly connected to the bus to write and read data from the bus interface and the disk interface. It performed the read, and the AV data memory other port which is performed the read write and data from the AV interface, the A
An AV data memory interrupt generating means for comparing a write / read situation to the V data memory with a preset condition and generating an interrupt signal when the condition is satisfied; and a communication interface, the disk interface and the AV data memory interrupt generating means. An interrupt controller for receiving the generated interrupt request signal and transmitting the interrupt request signal to the CPU; when data is input / output to / from the disk from the AV interface, the data is not stored in the main memory but is transmitted through the AV data memory via the AV data memory; And writing and reading from the AV interface to the AV data memory and writing and reading from the disk interface to the AV data memory are performed independently. Over data transmission equipment. 4. At least one or more CPUs, and said CPU
A main memory for storing command words executed by the CPU and data processed by the CPU, a bus for exchanging data between a plurality of peripheral interfaces, and an interface between the CPU, the main memory, and the bus A data transmission device comprising a bus interface for performing data communication, a communication interface connected to the bus and receiving an external data transmission command, a disk device for recording and reproducing data, and an interface between the disk device and the bus. A disk interface, an AV interface for interfacing the bus with an external data transmitting / receiving device, and writing data from the bus interface, the disk interface, and the AV interface directly connected to the bus. An AV data memory for reading and writing data, a first interrupt controller for receiving an interrupt request signal issued from the communication interface, the disk interface, and the AV interface to the CPU, and the disk interface and the AV interface. A second interrupt controller that receives an interrupt request signal issued from the controller and transmits the interrupt request signal to the communication interface, and distributes an interrupt request signal issued from the disk interface and the AV interface to the first interrupt controller or the second interrupt controller. Interrupt signal selection means for inputting / outputting data to / from the disk from the AV interface via the disk interface. In this case, data is not stored in the main memory but is transmitted through the AV data memory, and commands for writing and reading data to and from the disk interface and the AV interface are performed by the communication interface. Characteristic data transmission device.