JPH1185708A - How to synchronize software - Google Patents

Abstract

(57) [Problem] To provide a software synchronous execution method of a multiprocessor system in which data transmission / reception is performed in synchronization with a real-time clock and data transmission / reception is performed at high speed. A real-time clock (RTC) input to a plurality of CPU systems (1), (2) and (3) has a short-period clock generated in the system in synchronization with the real-time clock (RTC). It performs writing and reading of the common memory 4.

Description

DETAILED DESCRIPTION OF THE INVENTION

The present invention relates to an access method of a common RAM of a programmable controller constituted by a multiprocessor system.

[0002]

2. Description of the Related Art Conventionally, in a system using a common RAM, after writing data to the common RAM, an interrupt is issued to a transfer destination CPU to urge data to be taken. Alternatively, a method has been adopted in which data is transmitted and received in synchronization with a real-time clock (hereinafter, referred to as “/ RTC”). In the processing by the single synchronization of / RTC, a stable operation is possible, but the transfer delay is large due to the low speed.
Multi-CPU with distributed system requiring high-speed processing
Since there is a problem in the programmable controller of the system, various attempts have been conventionally made to generate a high-speed clock with a short cycle in the system in synchronization with the / RTC to increase the speed. FIG. 5 shows one of such conventional proposals for speeding up the clock.
56862 is a block diagram of a counter synchronization circuit in "Synchronization method of multiprocessor system". The counter 10 counts the clock pulse CP having a shorter period and a higher speed than * RTC, and outputs an interrupt signal * INTL from the RC pin when it overflows. On the other hand, CPU
The interrupt signal * RTC of the period T10 by the real-time clock is input to the load pin LD of the counter to preset the count value of the counter 10 to 0,
It is sent out on the bus as an interrupt signal. Therefore, the counter 10 alternately repeats the overflow and the preset, and generates the fast interrupt signal * INTL of the predetermined cycle T2. Since the cycle ratio between the cycle T10 of the interrupt signal * RTC and the cycle T20 of the interrupt signal * INTL is preset to be equal to T10 / T20 = integer value N as shown in FIG. The interrupt signals * RTC and * INTL should be output simultaneously at a rate of once every N cycles of * INTL. However, actually 2
2 during the synchronization period when two interrupt signals are output simultaneously
* RT as shown in FIG.
A phase shift occurs between C and * INTL, causing a so-called double interrupt in which two interrupt signals appear. In order to avoid this, for example, if the period T10 of * RTC is 8 ms and the period T20 of interrupt signal * INTL is 2 ms, which interpolates this, the pulse width adjustment circuit 30 sets the pulse width of the interrupt signal * RTC to about 4 μs. Is expanding.

[0003]

However, in the above-mentioned prior art, in the former method in which data is written to the common RAM and then the CPU of the transfer destination is interrupted to prompt the data fetch, the occurrence of the interrupt is random. There has been a problem in that the processing is disturbed and a bug occurs, and it is impossible to perform guess control of the execution processing. In the latter case, the speed of the interrupt signal * INTL can be increased even if the cycle is about 2 ms.
Is not sufficient for the semaphore processing and the like. To avoid double interrupts, the period ratio T10 / T20 of the two signals is
Calculating and adjusting the pulse width of the signal * RTC every time also has the problem that the circuit becomes complicated and it takes time. Accordingly, the present invention simplifies the system so that data transfer to and from the common RAM is performed in synchronization with the real-time clock / RTC of the CPU, suppresses the occurrence of bugs, and executes software execution timing by a highly reliable synchronization method. It is an object of the present invention to provide a synchronous execution method of software that can accurately capture the information.

[0004]

In order to achieve the above object, according to the first aspect of the present invention, a real-time clock RTC input to a plurality of CPU systems and a clock generated in each of the CPU systems in synchronism therewith. And a clock having a short cycle, and writing and reading of the common memory are performed in synchronization with the interruption of the short clock. According to a second aspect of the present invention, in the method for synchronously executing software, a plurality of Cs are set by setting up a semaphore at the time of interruption of the short-period clock, confirming this with a normal program, and executing post-processing.
It is characterized in that PU synchronization is enabled. Also,
The invention according to claim 3, wherein in the software synchronous execution method, when the real-time clock RTC is loaded into the counter for synchronization, the data to be loaded is an intermediate value of the counter, and the overflow value of the counter is used. Is characterized by including a short-period clock generated in synchronization with the real-time clock RTC. According to the above configuration, a clock synchronized with / RTC can be generated in each CPU module, which can transfer data at a higher speed than the data transfer by / RTC, and an interrupt is generated to the CPU by this short cycle clock. By transferring data in synchronization with the interrupt, the operation of the RAM semaphore, which requires high-speed processing of the multiprocessor system, can be performed without any trouble by highly reliable synchronous processing, and double interrupts can be generated. Can be avoided.

[0005]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a configuration diagram of a multiprocessor system according to an embodiment of the present invention, FIG. 2 is a timing chart of clocks in the system shown in FIG. 1, and FIG. 3 generates a clock shown in FIG. FIG. 4 is a block diagram of a counter synchronization circuit.
4 is a timing chart of the clock shown in FIG. 3. FIG.
In the multi-processor type programmable controller, a common RAM 4 is mounted on a back board 6 on which only normal connectors are arranged,
A RAM semaphore system or the like is configured in which a board on which U2 and CPU 3 are mounted is mounted, and a memory area is requested (set) and released (cleared) by a semaphore from each CPU to a common RAM. Next, the operation will be described. A basic real-time clock / RTC 5 is output from the master CPU 1 to the backboard 6.
The input is made to the other CPUs 2 and 3. Within each CPU module, an interrupt signal / RTD having a short cycle synchronized with / RTC5 as shown in FIG. 2 is generated. In the conventional example shown in FIG. 5, the pulse width of the / RTD is prevented from deviating from / RTC, so to speak. In the present invention, the time T2 sufficient for memory transfer by shortening the period of / RTD is set as the interrupt period of / RTD,
If the period T1 of the RTC is 4 ms, the speed of T2 is increased to about 250 μs so as to follow the common RAM system. Using such a high-speed / RTD, for example, the CPU 1 writes data to the common RAM 4 in synchronization with the / RTD next to the / RTC at the beginning in FIG.
The semaphore bit in the common RAM 4 is set up.
The semaphore bit is a semaphore indicating that data from the CPU 1 to the CPU 2 has been written to the common RAM 4. Therefore, at the time of the next / RTD, that is, T4, the CPU
2 checks the semaphore bit, takes in the contents of the common RAM, and clears the semaphore bit. This gives C
Data transfer between PUs is consequently performed at high speed in synchronization with / RTC. As shown in FIG. 3, the synchronous circuit in this case uses the interrupt signal / INT of the conventional circuit shown in FIG.
Compared to L, etc., a much faster clock / RTD is generated so that it can follow the RAM semaphore, and the double interrupt prevention method is not a method of expanding the pulse width, but a double interruption prevention method by a synchronization pull-in point delay method. Has been improved to increase reliability. In the counter synchronous circuit of the present invention, since the high-speed pulse / RTD has a period of 250 μs, and the 8-bit counter that reduces the 1 MHz clock to 1/250 counts 256, 0006H is loaded into the counter 7 by overflow. To obtain 256-6 = 250 counters. That is, 0006H is set in the uppermost counter of the counter 7, and
O6H start is counted. By repeating this count, / RTD outputs a clock having a period of 250 μs. This 250 μs cycle / RTD
Is divided by 16 by the bottom counter, and each C
Same cycle as / RTC used for other processing inside PU 4
Create ms clock / iRTC. External / RTC
Although there is a difference of 8 μs from this, this is not a problem. In the present invention, by setting the synchronization pull-in point away from the overflow point, double interruptions occurring within the synchronization period are prevented. In other words, the synchronization of the two clocks is conventionally performed at the overflow point (synchronization cycle), but the synchronization pull-in point is shifted from the overflow point by several bits to obtain an intermediate value of the counter. Specifically, as shown in FIG. 4, / RTC is loaded into the counter 7, and in this case, if the data loaded by the / RTC is 000EH, the counter 1 becomes 000EH when the value of the counter 1 is almost this value, and from the overflow point. The pull-in operation is performed at the shifted position. This prevents double interrupts and also establishes synchronization between / RTC and / RTD. Note that the synchronization pull-in point 000EH is not limited to this, and an optimum value may be selected from the period ratio T1 / T2. Up to this point, an example of a multiprocessor system configured by mounting a plurality of CPU modules on a backboard of a rack has been described. However, the present invention is not limited to this. Dedicated programming device, FA monitor device connected via
The present invention can be applied to other forms of distributed systems such as a general-purpose personal computer.

[0006]

As described above, according to the present invention,
Faster than basic / RTC data transfer, and
A clock synchronized with / RTC is created inside each CPU module, thereby generating an interrupt to the CPU,
Since the data is transferred in synchronization with the interrupt, the data is transferred in synchronization with the / RTC without sending a plurality of interrupt signals to the backboard. It is possible to suppress the occurrence and accurately grasp the execution timing of the software.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a multiprocessor system according to an embodiment of the present invention.

FIG. 2 is a timing chart of a clock in the system shown in FIG. 1;

FIG. 3 is a block diagram of a counter circuit that generates a clock shown in FIG. 2;

FIG. 4 is a timing chart of the clock shown in FIG. 3;

FIG. 5 is a block diagram of a conventional counter circuit.

6 is a timing chart of the clock shown in FIG.

[Explanation of symbols]

 1 CPU1 2 CPU2 3 CPU3 4 Common RAM 5 RTC 6 Backboard 7 Counter

Claims (3)

[Claims] 1. A real-time clock RTC input to a plurality of CPU systems, and each of the CPUs
A clock with a short cycle generated inside the system,
A synchronous execution method of software, wherein writing and reading of the common memory are performed in synchronization with the interruption of the short clock. 2. The method of synchronous execution of software, wherein a semaphore is set at the time of interruption of the clock having a short cycle, a semaphore is checked by a normal program, and post-processing is executed to enable synchronization of a plurality of CPUs. 2. The method for synchronously executing software according to claim 1, wherein: 3. In the method for synchronously executing software, when the real-time clock RTC is loaded into a counter for synchronization, the data to be loaded is an intermediate value of the counter, and the overflow value of the counter is the real-time clock. 2. The software synchronous execution method according to claim 1, further comprising a clock having a short cycle generated in synchronization with the RTC.