JPH1187721A - Thin film transistor, liquid crystal display device having the same, and method of manufacturing TFT array substrate - Google Patents

Abstract

(57) [Problem] To provide a thin film transistor having excellent on-characteristics and a large screen and high definition liquid crystal display device using the thin film transistor. SOLUTION: After a gate electrode line 2 is formed on a glass substrate 1, iaS which becomes a channel via a gate insulating film 3 is provided.
The i-layer 4 is formed to a thickness of 80 to 120 nm, and the na-Si layer 5 for forming source / drain contacts is formed to a thickness of 30 nm. The ia-Si layer 4 and the na-Si layer 5 are patterned into an island shape to form a pixel electrode 8.
Next, a source electrode line 6 and a drain electrode 7 are formed,
Using these as masks, unnecessary na-Si on the channel
The layer 5 is removed by dry etching or the like. As mentioned above,
Ia-Si at source / drain contact part
By reducing the thickness of the layer, a parasitic resistance (series resistance) due to this can be reduced, and a thin film transistor having excellent on-state characteristics can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a thin film transistor and a TFT array substrate used in a liquid crystal display device.

[0002]

2. Description of the Related Art A liquid crystal display device generally has a TFT array substrate having switching elements including thin film transistors (TFTs) and display elements controlled through the switching elements, a color filter, a black matrix, a counter electrode, and the like. In addition, a driving circuit for a switching element and a counter electrode substrate which sandwiches liquid crystal between the TFT array substrate and the TFT array substrate are provided, and a voltage is selectively applied to the liquid crystal. FIG. 5 is a sectional view showing a structure of a pixel portion of a conventional inverted stagger type TFT array substrate. In the figure, 1 is a transparent insulating substrate, for example, a glass substrate, 2 is a gate electrode line, 3 is a gate insulating film, 4 is an ia-Si (non-doped amorphous silicon) layer serving as a channel, and 5 is ia An n-a-Si (phosphorus-doped amorphous silicon) layer provided at a source / drain contact portion on the -Si layer 4, 6 a source electrode line, 7 a drain electrode, 8 a pixel electrode made of a transparent conductive film, 9 Indicates a protective film.

[0003] The inverted stagger type TF configured as described above.
For the T-array substrate, the process is simple,
A back channel etch type TFT is often used. A method of manufacturing a conventional back channel etch type TFT will be described with reference to the drawings. First, a gate electrode line 2 is formed on a glass substrate 1 with Cr or the like, and then the gate insulating films 3 and 200 are formed.
i-a-Si layer 4 having a thickness of 50 nm or more and n-
An a-Si layer 5 is formed. Thereafter, the ia-Si layer 4 and the na-Si layer 5 are patterned into an island shape to form a pixel electrode 8 made of a transparent conductive film. Further, a source electrode line 6 and a drain electrode 7 are formed, and unnecessary na-Si layer 5 on the channel is removed by dry etching or the like using these as a mask (BCE: back channel etching). To form a TFT array.

[0004]

As described above, in the back channel etch type TFT, the channel region is formed by removing the na-Si layer 5 by etching or the like. Etching is performed up to the -Si layer 4. Therefore, conventionally, i-
In order to always secure a sufficient film thickness of the a-Si layer irrespective of process variations, the ia-Si layer 4 has a thickness of 200 nm.
m or more. For this reason, the parasitic resistance (hereinafter referred to as series resistance) caused by the ia-Si layer 4 in the source / drain contact portion increases,
There is a problem in that the characteristics of the TFT, particularly the on-characteristics, are degraded, and in driving a large-area, high-definition liquid crystal display device, the writing characteristics are insufficient and the display characteristics are degraded. In addition, in order to reduce the series resistance, it is necessary to increase the area of the overlapping portion (contact portion) of the source electrode, the drain electrode, and the gate electrode, thereby increasing the parasitic capacitance of the TFT and deteriorating the display characteristics. there were.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a thin film transistor having excellent ON characteristics and a large-screen, high-definition liquid crystal display using the thin film transistor. Another object of the present invention is to provide a method of manufacturing a TFT array substrate having the above-mentioned thin film transistor.

[0006]

According to the present invention, there is provided a thin film transistor comprising: a gate electrode formed on a transparent insulating substrate; and an ia-channel serving as a channel portion provided on the gate electrode via a gate insulating film. Si layer and this ia-Si
N- provided on the source / drain contact portion on the layer.
a semiconductor layer comprising an a-Si layer; source and drain electrodes forming a semiconductor element together with the semiconductor layer;
The thickness is set to 0 nm or more and 120 nm or less. Also, n
-The thickness of the a-Si layer is 20 nm or more and 50 nm or less. In addition, the thickness of the ia-Si layer in the channel portion is 30 nm or more and 80 nm or less. Further, the overlap length of the gate electrode, the source electrode, and the drain electrode is set to 2 μm or more and 5 μm or less. Further, a liquid crystal display device according to the present invention comprises a TFT array substrate having a switching element including any one of the above-described thin film transistors and a display element controlled via the switching element, and a liquid crystal interposed between the TFT array substrate. It comprises a counter electrode substrate to be sandwiched and a drive circuit for a switching element.

Further, a method of manufacturing a TFT array substrate according to the present invention comprises the steps of forming a metal thin film such as Cr on a transparent insulating substrate, forming a gate electrode line by pattern formation, and forming a gate electrode line on the gate electrode line. I-a-S with a thickness of 80 nm or more and 120 nm or less serving as a channel via an insulating film
Thickness 2 for i-layer and source / drain contact layers
A step of continuously forming a na-Si layer having a thickness of 0 nm or more and 50 nm or less and patterning it in an island shape, and a step of forming a transparent conductive film by a method such as sputtering and forming a pixel electrode by pattern formation. Forming a metal thin film of Al, Cr, or the like by a sputtering method, and forming a source electrode line and a drain electrode by pattern formation;
While controlling the over-etching amount of the na-Si layer so that the remaining film amount of the ia-Si layer in the channel portion is 30 nm or more and 80 nm or less, the unnecessary na-Si layer on the channel is controlled. The manufacturing method includes a step of removing a layer by dry etching or the like and a step of forming a protective film.

[0008]

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment 1 FIG. Hereinafter, a method for manufacturing a thin film transistor (TFT) according to the first embodiment of the present invention and a TFT array substrate including the same will be described with reference to the drawings. FIG. 1 is a sectional view showing a structure of a pixel portion of a TFT array substrate according to the first embodiment of the present invention. In the figure, 1 is a transparent insulating substrate, for example, a glass substrate, 2 is a gate electrode line, 3 is a gate insulating film, 4 is an ia-Si (non-doped amorphous silicon) layer serving as a channel, and 5 is ia- N- provided on the source / drain contact portion on the Si layer 4
a-Si (phosphorus-doped amorphous silicon) layer, 6 is a source electrode line, 7 is a drain electrode, 8 is a pixel electrode made of a transparent conductive film, 9 is a protective film, L is gate electrode 2 and source electrode 6 and drain electrode 7 And the length of the overlap.

The thin film transistor according to the present embodiment has an ia-Si layer 4 serving as a channel portion and a source / source layer.
A semiconductor layer composed of an n-a-Si layer 5 provided in a drain contact portion, and a source electrode 6 and a drain electrode 7
To form a semiconductor element. Further, a switching element including the thin film transistor and a display element controlled through the switching element, here, a TFT array substrate having a pixel electrode 8, a color filter, a black matrix, a counter electrode, and the like are provided.
A liquid crystal display device is composed of a counter electrode substrate that sandwiches liquid crystal between the FT array substrate and a driving circuit of a switching element.

Hereinafter, a method of manufacturing an inverted staggered TFT array substrate having a thin film transistor according to the present embodiment will be described. First, a metal thin film having a single-layer structure such as Cr or a multilayer structure such as Cr / Al is formed on a glass substrate 1.
The gate electrode line 2 is formed by pattern formation. next,
After the gate insulating film 3 is formed, the ia-
The Si layer 4 is formed with a thickness of 80 to 120 nm. Further continuously, n- to form source / drain contacts
The a-Si layer 5 is formed with a thickness of 30 nm. In the present embodiment, the thickness of the na-Si layer 5 is set to 30 nm, but may be in the range of 20 nm to 50 nm. The thickness of these semiconductor layers (a-Si) is i
-Ensure that the a-Si layer always has a sufficient thickness irrespective of process variations, and reduce the parasitic resistance (hereinafter referred to as series resistance) caused by the ia-Si layer 4 in the source / drain contact portions. It has been optimized to be able to

Thereafter, the ia-Si layer 4 and the na-
The Si layer 5 is patterned into an island shape, a transparent conductive film is formed by a method such as sputtering, and the pixel electrode 8 is formed by pattern formation. Further, a metal thin film such as Cr, Al / Cr or Cr / Al / Cr is formed by a sputtering method or the like, and the source electrode line 6 and the drain electrode 7 are formed by pattern formation. At this time, the overlap length L of the gate electrode 2 and the source electrode 6 and the drain electrode 7
Is designed to be 2 μm or more and 5 μm or less, the parasitic capacitance of the TFT can be reduced without deteriorating characteristics due to an increase in series resistance. Further, using the source electrode 6 and the drain electrode 7 as masks, unnecessary naS
The i-layer 5 is removed by dry etching or the like (BCE: back channel etching). At this time, the ia-Si layer 4
N so that the remaining film amount of
-Etching is performed while controlling the over-etching amount of the a-Si layer 5. Finally, the protection film 9 is formed of SiN or the like, and a TFT array substrate is manufactured.

FIG. 2 is a diagram showing the relationship between the ia-Si film thickness and the series resistance, and FIG. 3 is a diagram showing the relationship between the ia-Si film thickness, the mobility and the threshold voltage. In the figure, the horizontal axis is the ia-Si film thickness (nm), and the vertical axis is Rseries.
(M ohms) indicates series resistance, μfe (cm ² / VS) indicates mobility, and Vth (V) indicates threshold voltage. From these experimental results, it is clear that as the ia-Si film thickness increases, the series resistance increases and the TFT characteristics deteriorate, and the effect of thinning the ia-Si film according to the present invention is shown. ing. In addition, according to the TFT array substrate of the present invention, the mobility can be reduced by 30% or more in the linear region (low Vd region) compared with the conventional back channel etching type TFT, so that the writing time is shortened and the writing is insufficient. Display defects and variations can be reduced.
FIG. 4 is an experimental result showing the dependence of the mobility and the threshold voltage on the na-Si film thickness in the linear region (Vd = 1 V). Suggests the possibility. By making the na-Si layer 5 thinner, there is an advantage that the threshold voltage is reduced. However, since the mobility is also reduced, it is necessary to set the film thickness in consideration of both. In the present embodiment, na-Si
When the layer 5 is etched, the na-Si layer 5 is replaced with a conventional 50n in order to reduce the deterioration of the TFT characteristics due to the damage of the ia-Si layer 4 by over-etching.
The thickness is reduced from m to 30 nm to reduce the amount of over-etching.

As described above, in the present embodiment, the thickness of the ia-Si layer 4 at the source / drain contact portion is reduced from the conventional 200 nm to 80 nm or more and 120 nm or less. Layer 5 is made of conventional 50n
Since the film thickness was reduced from m to 30 nm, a thin film transistor having small series resistance, high mobility in a linear region, and small parasitic capacitance was obtained. Also, the ia-Si layer 4
As a result, the size of the thin film transistor can be reduced, so that the aperture ratio of the pixel can be increased. Further, by providing the thin film transistor, a large-area and high-definition liquid crystal display device can be realized.

[0014]

As described above, according to the present invention, ia
-Si that the thickness of the Si layer was reduced to 80 nm or more and 120 nm or less, i
Parasitic resistance due to the -a-Si layer can be reduced, and a thin film transistor with excellent on characteristics can be obtained. Further, by providing the thin film transistor, a large-area and high-definition liquid crystal display device can be realized.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a pixel portion of a TFT array substrate according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a relationship between an ia-Si film thickness and a series resistance.

FIG. 3 is a diagram showing the relationship between ia-Si film thickness, mobility, and threshold voltage.

FIG. 4 shows mobility and threshold voltage n in a linear region.
It is a figure which shows the -a-Si film thickness dependence.

FIG. 5 is a sectional view showing a pixel portion of a conventional TFT array substrate.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 glass substrate, 2 gate electrode line, 3 gate insulating film, 4 ia-Si (non-doped amorphous silicon) layer, 5 na-Si (phosphorus-doped amorphous silicon) layer, 6 source electrode line, 7 drain electrode, 8
Pixel electrode, 9 protective film.

Claims (6)

[Claims] A gate electrode formed on a transparent insulating substrate; an ia-Si layer serving as a channel provided on the gate electrode via a gate insulating film; and the ia-Si layer Na provided in the upper source / drain contact portion
A semiconductor layer composed of a Si layer, a source and a drain electrode forming a semiconductor element together with the semiconductor layer, and a thickness of the ia-Si layer in a source / drain contact portion is set to be 80 nm or more and 120 nm or less. Thin film transistor. 2. The method according to claim 1, wherein the thickness of the na-Si layer is 20 nm or more.
2. The thin film transistor according to claim 1, wherein the thickness is 0 nm or less. 3. The thickness of the ia-Si layer in the channel portion is 3
The thin film transistor according to claim 1, wherein the thickness is 0 nm or more and 80 nm or less. 4. The thin film transistor according to claim 1, wherein an overlap length of the gate electrode, the source electrode, and the drain electrode is 2 μm or more and 5 μm or less. 5. A TFT array substrate having a switching element including the thin film transistor according to claim 1 and a display element controlled via the switching element, and a TFT array substrate. A liquid crystal display device comprising: a counter electrode substrate having liquid crystal interposed therebetween; and a drive circuit for the switching element. 6. A step of forming a metal thin film of Cr or the like on a transparent insulating substrate and forming a gate electrode line by pattern formation, and forming a channel on the gate electrode line via a gate insulating film to a thickness of 80 nm or more and 120 nm or more. The following ia-Si layer and film thickness of 20 n to be source / drain contact layers
a step of continuously forming a na-Si layer having a thickness of not less than m and not more than 50 nm and patterning it into an island shape; a step of forming a transparent conductive film by a method such as sputtering and forming a pixel electrode by pattern formation; Forming a source electrode line and a drain electrode by pattern formation by forming a thin metal film such as Cr, Cr or the like by a sputtering method, etc., and the remaining film amount of the ia-Si layer in the channel portion becomes 30 nm to 80 nm. As described above, while controlling the over-etching amount of the na-Si layer, a step of removing the unnecessary na-Si layer on the channel by dry etching or the like, and a step of forming a protective film are provided. Manufacturing method of a TFT array substrate.