JPS6273670A - Method for manufacturing thin film transistor device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a thin film transistor (TPT) device using amorphous silicon (a-8i) or the like.

[Summary of the invention]

The present invention is a method for manufacturing an inverted staggered TPT.

(1) Formation of a gate electrode and wiring on a transparent insulating substrate, (
2) Successive deposition of multiple semiconductor films including gate insulating film, high resistance semiconductor thin film, and low resistance semiconductor thin film, (3) selective etching of multilayer semiconductor film, (4) deposition of transparent conductive film, (5) gate electrode wiring This process consists of forming sous and drain electrodes using a transparent conductive film by exposing the back side of the substrate using a gold mask, (6) removing unnecessary portions of the transparent 4-conductor film, and (7) removing the exposed low-resistance semiconductor thin film. Since the channel length fluctuates in a self-aligned manner, it is ideal for large area TFT devices and short channel TFTs.

[Conventional technology]

A-8i TFTs are being applied to liquid crystal display devices and the like, but there are several problems with conventional manufacturing methods when increasing the screen size. The conventional method will be explained with reference to FIG. This example is a cross-sectional view of a TFT shown in 1989-18966, in which the gate electrode 12 is completely formed on the insulating substrate 1, and the gate M! A process of depositing the 3R film 13 and the semiconductor thin film 14 and leaving the semiconductor thin film 14 in a predetermined shape, a process of selectively removing the thin film 50 gold strips so as to cover the semiconductor 1Q14, depositing a transparent conductive film 6 and leaving the semiconductor thin film 14 in a predetermined shape. The transparent conductive film 6 and the metal film 50 on the semiconductor film 14, which will become a channel, are
Remove the source electrode 25, drain '1! , the electrode wiring 55 and 56 formed by the electrode 26 and the transparent groove 1 [film 6] are formed. Although the process is simple, the following problems arise when producing a large-sized device such as A4. (1
) Source or drain electrode 25°26 and gate electrode 1
2 and the planar overlap dimension Δt1. The minimum value of t2 is determined by the alignment accuracy between layers of the aligner, and is usually 5.
Although it is necessary to have a value of .mu.m or more, this value is too large in terms of TPT performance because it increases the capacitance. On the other hand (2), the channel length also depends on the resolving power of the aligner and is normally 10 μm or more, but if yield is taken into account, it is necessary to be about 20 μm, which is not long enough to achieve the desired TF'T characteristics. Furthermore, if all of this example is applied to the short channel TEL'T, the capacitance will be large due to the presence of Δ4 and Δt2, which will limit the high-speed characteristics. A similar problem can be found in Japanese Unexamined Patent Publication No. 60-4
Also available in 2868 and 60-50963.

[Problem that the invention seeks to solve]

The present invention has been made to solve the above-mentioned problems, and provides a method for manufacturing a TFT that can easily be made to have a large area and short channels.

[Means for solving problems]

In the present invention, a transparent conductive film is used for the source and drain electrodes, and all of the source and drain electrodes are formed in a self-aligned manner by exposure to light from the back side of the substrate using the gate electrode as a mask. The process consists of (1) formation of a gate electrode/wiring using an opaque first conductive layer on a transparent insulating substrate, (2)
Gate insulating film, continuous deposition of a multilayer semiconductor film consisting of a high resistance semiconductor thin film and a low resistance semiconductor thin film, (3) selective etching that leaves the multi-semiconductor film in the form of islands on the gate' electrode, (4) preparation of a transparent conductive film. (5) Remove the transparent conductive film on the channel by applying the negative resist completely and exposing from the back side of the substrate as described above. (6) Remove the transparent conductive film from unnecessary parts? removing to form source and drain electrodes, (7) exposed low resistance semiconductor N;
consisting of the removal of the membrane. Selective etching of a multilayer semiconductor film can also be performed in a self-aligned manner by exposing from the back side of the substrate coated with body resist.

[Effect]

In the present invention, since the source and drain electrodes are formed by using fog light on the back surface of the substrate with the entire gate electrode as a mask, it is not affected by the interlayer positioning accuracy and power of the aligner. In other processes, the performance limitations of the upper two aligners are hardly imposed, so it is easy to make the substrate larger in area and the channels shorter. Further, the above-mentioned backside exposure is made possible by making the entire thickness of the multilayer semiconductor film sufficiently thin and using transparent conductive films for the source and drain electrodes.

〔Example〕

(a) Example I Tll'T manufacturing process sectional view (FIG. 1) FIG. 1 shows a sectional view along the manufacturing process of TPT according to the present invention. In FIG. 1(a), an opaque first conductive film 2 is formed on a transparent insulating substrate 1 to form a gate ′ [electrode/wiring 1
2 Complete formation and state of mind. The substrate 1 is made of glass, quartz, etc., and the film 2 is mainly a metal film containing Cr, MO,
W, Ta, Ni, At, etc. are used, and for example, in the case of a Cr film, it is 0.1 to (12 μm4).

Figure 1 (b) h, gate insulation fit3, high resistance a-8
A state in which soil film 5 and na-8i film 5 are continuously deposited is shown. These layers can be deposited by plasma CVD, original CVD, etc., and an 810X or 5iNX film is used for the gate insulating film 15. The thickness of the high resistance A-8I film 4 and the NA-8I film 5 is 500A or less and 30A or less, respectively, so that ultraviolet light can pass through sufficiently.
OA or lower is usually selected.

FIG. 1(c) shows a high resistance a-8i film 4 and a na-8i film 5.
The TFT portion of the two-layer semiconductor @10 consisting of is shown in a cross section selectively etched into an island shape. The width of the two-layer semiconductor film 10 is preferably equal to or larger than the width of the gate electrode 12, but a width of about 2 to 6 μm is permissible.
The gate [i12'
The resist 8 is patterned on the i-mask, and then the transparent conductive film 6 is selectively etched to leave a blank state. Transparent conductive film 6
Spunter films and vapor deposited films such as TO and 5n02, (j
A VD film is used. Light irradiation from the back side of the substrate 1 requires several hundred to several thousand times the appropriate irradiation time from the front side. The dimensions of the gate electrode 12 and the source and drain electrodes 15 and 16 are determined according to the amount of dimming, and are, for example, about 05 to 3 μm.

In FIG. 1(e), after removing the resist 8, the unnecessary portions of the transparent conductive film 24 are selectively etched and further exposed.
The i film 5 is removed to form a high resistance a which becomes the channel region 14.
A state is shown in which a source region 15 and a drain region 16 are formed by the na-8i film 5 which are in contact with both ends of the -8i film 4 and are separated from each other, and a source electrode 25 and a drain electrode 26i are formed by the transparent conductive film 6.

To remove the Na-8i film 5, plasma etching using an AT-based gas, reactive ion etching, and photo etching are used to remove high-resistance a
This is desirable from the viewpoint of selectivity with the -8i film 4.

Contact openings above the gate electrode layout can be formed after this or after FIG. 1(c) if necessary.

(b) Example Z Manufacturing of unit pixel (Figs. 3 and 4)
Figure) An example in which the present invention is applied to a TPT substrate for a liquid crystal display device will be explained for each unit pixel with reference to Figures 5 and 4. FIG. 3 shows a complete plan view of an example of the structure of the mask, in which A is the gate electrode wiring, B is the drain electrode and the pixel electrode Kanakura's source! Pole, C is drain 'ton excision.

It is an auxiliary mask for lines. The following manufacturing process will be explained with reference to FIG. FIG. 4 shows a cross section taken along line a-a' in FIG. 5, and FIG. 12, gate insulating film 13, high resistance a-8i@4, na
After depositing the -8i film 5, a positive resist 18 is applied and patterned by backside exposure. The positive resist 18 remains in substantially the same shape as the mask A. After that, the two-layer semiconductor film 10f is selectively etched, the absolute R film 7 is deposited, and the negative resist 28 is patterned again by back exposure, as shown in FIG. 4(b). Si□x or the like is deposited on the insulating film 7 and is used to reinforce the gate insulating film 15. FIG. 4C shows a state in which after an opening is formed in the insulating film 7 on the 2# semiconductor film 10, the transparent 4-electrode film 6 is completely deposited and the negative resist 8 is completely patterned by exposing the back side again. In this case, the backside exposure is performed in an excessive manner so that resist patterning forms on the inner side of the opening end of the insulating film 7. Since the resist on the gate electrode wiring 12 (29 semiconductor film 10) is not exposed to light by backside exposure, the future intersection of the gate electric wiring 12 and the drain electrode wiring 26 is exposed from the front side using mask C. do. Mask C is.

In this way, the portion where the gate electrode wiring 12 and the transparent conductive film 6 overlap can also be used for forming a capacitor, for example.

FIG. 4(d) shows that after the transparent conductive film is selectively etched in the state shown in FIG. 4(c), the entire unnecessary portion of the transparent groove m film is selectively etched again using mask B, and then the resist is removed and exposed. The completed na-8i film 5f is selectively etched using a transparent conductive mask. As a result, the separated source and drain regions (n+a-81 film) 1
5.16 and source and drain electrodes (transparent conductive film) 25
．． 26 is formed. Mask B [, channel region 14
Since the upper part is masked, the interlayer positioning accuracy may be rough as in the conventional example shown in FIG.

In addition, high-resistance traces 4 remain on the gate electrode wiring 12 other than the TPT portion, but the distance is sufficiently long so that crosstalk between FTs can be seen. 1f of insulation in this part
Q If the 7 and na-8i films 5 overlap at the ends, use the transparent conductive film 6 as a mask to remove the IRPA7'f:
The na-8i film 5 may be removed after being partially removed.

If the selective etching of the insulating film 7 shown in FIG. 4(b) is over-etched, the S-side exposure shown in FIG. 4(c) does not necessarily require overexposure.

In this example, gates 1i1. Although the external lead-out portion of the 'm wiring 12 is not shown,
4, by masking the na-8i film 5 so as not to deposit it on the external extraction portion during deposition, it can be easily formed without additional masking steps. Further, the mask C, which is an auxiliary mask, can also be made unnecessary by making the intersection of the gate electrode wiring 12 with the drain/electrode 26 thinner and by over-exposing the back surface. Furthermore, before making the entire island-like region of the %22-layer semiconductor film 10, an additional transparent 4-layer film is deposited on the NA-81 film 5, and the additional transparent conductive film and the 2-layer semiconductor film are made into an island-like region, and the source
It is also possible to reinforce the drain electrodes 25,26.

〔Effect of the invention〕

As described above, according to the present invention, a large area Tl'T device or a short channel TU can be produced by a simple process of 6 to 4 masks.
T device can be manufactured.

Although we have mainly described an example in which an a-8i film is used as a semiconductor thin film, the present invention can be similarly applied to a polycrystalline silicon film and other semiconductor thin films. Also, nchi'r-/nel TF
This applies not only to TPT but also to p-channel TPT.

[Brief explanation of drawings]

Figures 1(e) to (e) are cross-sectional views along the manufacturing process of TFT according to the present invention, *Figure 2 is TPP according to the conventional manufacturing method.
The T cross-sectional view, FIG. 3, and FIGS. 4(a) to (d) are diagrams of other embodiments of the present invention, and FIG. 3 is a plane mask diagram, and FIGS. 4(a) to (d). 3 is a step-by-step sectional view taken along line a-a' in FIG. 3. 1...Substrate 2...First conductive film\IL film 4...High resistance semiconductor thin film 5...
...Low resistance semiconductor layer 6...Transparent conductive film
Film 7...Insulating film 8.18.2
8...Resist 10...2# Semiconductor film
G12...Gate'electrode wiring 1
3...Gate insulating film 14...Channel region 15...Source region 16...Drain region 25...Source electrode 26...・・・
・・Dray/electrode The above is a cross-sectional view of the TFT rough fabrication process according to the present invention (2).
Diagram 2 of concave cross section

Claims (4)

[Claims] (1) (a) A first step of selectively forming a gate electrode and wiring made of an opaque first conductive film on a transparent insulating substrate. (b) A second step of sequentially and continuously depositing a multilayer semiconductor film consisting of at least a gate insulating film, a high-resistance semiconductor thin film, and a low-resistance semiconductor thin film. (c) A third step of selectively etching the multilayer semiconductor film on the gate electrode to form an island-like region. (d) Fourth step of depositing a transparent conductive film. (e) After applying a negative resist, the resist is selectively left on areas other than the gate electrode and wiring by light irradiation from the back surface of the substrate and overexposure, and the resist is used as a mask to contact a part of the surface of the multilayer semiconductor film. A fifth step of selectively forming a transparent conductive film. (f) A sixth step of selectively etching unnecessary parts of the transparent conductive film to form small co-source and drain electrodes. (g) A seventh step of selectively etching the low-resistance semiconductor thin film exposed in the sixth step to form source and drain regions made of a low-resistance semiconductor that are in contact with the source and drain electrodes and the high-resistance semiconductor thin film. A method of manufacturing a thin film transistor device with fewer components. (2) In the fifth step, after the light irradiation and exposure from the back side of the substrate, exposure is further performed from the front side of the substrate through a mask, and after the selective etching, a part of the multilayer semiconductor film is exposed on the gate electrode and wiring. 2. The method of manufacturing a thin film transistor device according to claim 1, further comprising the step of also providing a transparent conductive film that crosses the area. (3) The third step is to apply a positive resist on the multilayer semiconductor film, leave a resist with almost the same shape on the gate electrode and wiring by irradiation and exposure from the back side of the substrate, and mask the resist. 3. The method of manufacturing a thin film transistor device according to claim 1, wherein the island-like region is formed in a semiconductor device. (4) After the third step, a step of depositing an insulating film, a step of applying a negative resist, irradiating light from the back surface of the substrate, and removing the insulating film on the island-shaped region using light exposure, 4. The method of manufacturing a thin film transistor device according to claim 3, wherein the fourth step is performed.