JPH1188120A - Filter circuit - Google Patents

Abstract

(57) [Summary] [Purpose] To reduce the size and power consumption of filter circuits. A direct type configuration of an IIR filter is realized by an analog architecture.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a direct configuration IIR filter circuit.

[0002]

2. Description of the Related Art Digital technology in computer science has been remarkably developed with the advance of microfabrication technology, but the amount of capital investment is increasing at an accelerating rate, and at present analog technology and analog / digital mixed technology are being developed. Is attracting attention. Therefore, the applicant has proposed a filter circuit that uses an analog voltage as an input signal and filters the analog voltage as it is (Japanese Patent Laid-Open No. 06-1643).
No. 21, etc.), and good results were obtained with respect to the circuit scale and power consumption.

FIG. 6 shows such an analog type filter circuit, which converts an input signal X (n) input in the form of an analog input voltage into a plurality of analog type sample-and-hold circuits S.
The signals held in chronological order by Ha0 to ShaM, and the multipliers a0 to aM are applied to the signals held by these sample and hold circuits by analog multipliers Ma1 to MaM.
Multiply. The outputs of these multiplying circuits are summed by an adding circuit ADD7, and the sum is held in time series by a plurality of sample and hold circuits SHb1 to SHbN. The output of these sample-and-hold circuits is a multiplication circuit M
The multipliers -b1 to -bN are multiplied by b1 to MbN, respectively, and input to the adder ADD7. That is, the adder ADD7 sums the outputs of all the multipliers, and further multiplies the outputs Y (n) of the adders by the multipliers Mb1-Mb.
Multiplication by bN is performed. This filter circuit is IIR
This is called a filter, and is applied to an extremely large number of applications. There is a high demand for further miniaturization and power saving of the analog configuration of such a filter circuit.

[0004]

SUMMARY OF THE INVENTION The present invention has been made under such a background, and has as its object to provide a direct type IIR filter circuit having a smaller circuit size and lower power consumption than conventional ones. I do.

[0005]

The filter circuit according to the present invention has a simplified IIR filter configuration by reducing the number of sample-and-hold circuits, thereby simplifying the circuit configuration.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The direct form II according to the present invention will now be described.
An embodiment of the R filter circuit will be described with reference to the drawings.

[0007]

FIG. 1 is a circuit diagram showing an embodiment of a filter circuit according to the present invention, wherein a plurality of first multiplying circuits Mb1 to Mb are shown.
N and a plurality of second multiplication circuits Ma0 to MaN,
One set of sample and hold circuits SH0 to SHN is provided. The outputs of the multiplication circuits Mb1 to MbN are added to the addition circuit AD.
D1 and the outputs of the multiplication circuits Ma0 to MaN are input to the addition circuit ADD2. Further, an addition circuit ADD
1 receives the input signal Ai once held by the sample hold circuit SH0, and ADD1 calculates the sum of this input signal and the outputs of the multiplication circuits Mb1 to MbN. (I
The output of the (+1) -th sample-hold circuit SHi is input to the multiplication circuits Mai and Mbi, and the output of the addition circuit ADD1 is input to the multiplication circuit Ma0.

The above configuration is called a direct configuration IIR filter (Reference: Miki Takebe, “Design of Digital Technology Series Digital Filter”, Tokai University Press, February 20, 1994, 4th print), 1 One set of sample-and-hold circuits can be used as an input to two sets of multiplication circuits, and the number of sample-and-hold circuits can be reduced to about half of the conventional case. Here, the transfer function of the above filter circuit is as shown in equations (1) to (3). Note that multiplying circuits Ma1 to MaN are provided in all of the sample and hold circuits SH1 to SHN.
It is not necessary to connect Mb1 to MbN, and only one of the multiplication circuits may be connected. Therefore, the multiplication circuit Mb
The number of multiplication circuits Mb1 to MbM is M
Is present, the transfer function of the filter circuit becomes
As shown in (3).

(Equation 1)

In FIG. 3, the sample and hold circuit SH1 includes a switch S31 connected to an input voltage Vi3.
, The sample hold timing is set, and the output timing of the voltage held in the subsequent switch S32 is set. The switch 31 is connected to a first input capacitance C31. The switch C31 is connected to an inverter circuit INV31 shown in detail in FIG.
1 are connected by a feedback capacitance Co31. C31 and Co31 are set to the same capacity, and when S31 is closed, INV31 produces the output Vo3 'of equation (4). As shown in the equation, the output is V
equal to the inverse of i3. These Vo3 ′ and Vi3 are V
The voltage is based on dd / 2.

(Equation 2) The output of INV31 is input to a second input capacitance C32 via a switch S32, and the output of C32 is INV31.
31 is connected to the same inverter circuit INV32 as
The input and output of the NV32 are connected by a feedback capacitance Co32. If C32 = Co32, then S
In the closed state of No. 32, the output of INV32, that is, the output of the sample-and-hold circuit SH0, is as shown in Expression (5).

(Equation 3)

The sample-and-hold circuit SH1 is configured so that S31 is closed for a sufficient time and the charge corresponding to Vi3 is C3.
1. When S31 is held at Co31, S31 is opened, then S32 is closed, and the charge corresponding to Vo3 'is transferred to C32,
It is held by Co32. By transferring the charge in this manner, a change in Vi3 is prevented from affecting Vo3, and Vi3 can be held and output with good accuracy. Note that the other sample and hold circuits are configured in the same manner as the SH1, and therefore description thereof is omitted.

FIG. 2 shows inverter circuits INV31 and INV.
32 (indicated by the reference numeral INV). The inverter circuit INV includes a three-stage CMOS inverter I2
1, I22 and I23 are connected in series, and a phase compensation circuit composed of a series circuit of a resistance RP and a capacitance CP is connected to the input and output of I22. The inverter circuit outputs the inverted input with good linear characteristics due to the effect of the high gain by the product of the gain of each CMOS inverter and the feedback capacitance. Further, the phase compensation circuit prevents oscillation in a high-gain feedback system.

In FIG. 4, a multiplier Ma0 receives an input voltage V
i4 (corresponding to the output of the adder ADD1) has a plurality of switches S41 to S48 that can be connected, and the outputs of S41 to S48 are connected to the first input capacitances C41 to C48 for multiplication, respectively. The input sides of the switches S41 to S48 can be connected to Vi4 or the reference voltage Vref, and the input voltage or the reference voltage is applied to C41 to C48. C41 to C48 have a capacity corresponding to a power of 2, and each of the switches S41 to S48 is controlled by a control signal corresponding to the multiplier a0. C41
To the output of the inverter circuit INV4 while being integrated.
And the output of INV4 is connected to its input via a first feedback capacitance Co4 for multiplication. Here, each bit of the binary number corresponding to the multiplier a0 is represented by bm0 to bm.
7 (bm7 is the MSB) and the capacity of C41 to C48 is

[Outside 1] And Co4

[Outside 2] , The output Vo4 of the multiplication circuit Ma0 is as shown in Expression (6).

(Equation 4)

In FIG. 5, the adder ADD1 has first input capacitances C5b1 to C5bN for multiplication corresponding to the multipliers Mb1 to MbN. The outputs of the multipliers Mb1 to MbN are input to these input capacitances. ing. Each input capacitance is connected to a switch (not shown) that is switched by a sign bit of a multiplier.

The capacitances C5b1 to C5bN are the same as those of the inverter circuit INV51 while the outputs are integrated.
And the output of INV51 is the feedback capacitance C
It is connected to its input by o51. Here C5
b1 = C5b2 =. . . = C5bN = CC / (N / 2−
1) = Co51, Co52 = 2CC, and the adding circuit A
The output Vo5 of DD1 is as shown in equation (7).

(Equation 5) Here, when the input capacitance such as C5b1 is simply represented by C, Equation (7) is simplified as Equation (8).

(Equation 6)

The reference voltage Vref is set to Vdd / 2 when the power supply voltage of the CMOS inverter is Vdd, and the maximum dynamic range is secured in both the positive and negative directions around this reference voltage.

As described above, since all of the sample-and-hold circuit, the multiplication circuit, the addition circuit, and the scaler circuit are configured by voltage-driven analog circuits, the overall circuit configuration is simple and small, and the power consumption is small. . And
By reducing the number of sample and hold circuits, further miniaturization and power saving are achieved.

[0015]

As described above, in the filter circuit according to the present invention, the configuration of the IIR filter is a direct type configuration, and the number of sample-and-hold circuits is reduced to simplify the circuit configuration. And has an excellent effect of low power consumption.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an embodiment of a filter circuit according to the present invention.

FIG. 2 is a circuit diagram showing an inverter circuit in the embodiment.

FIG. 3 is a circuit diagram showing a sample and hold circuit in the embodiment.

FIG. 4 is a circuit diagram showing a multiplication circuit in the embodiment.

FIG. 5 is a circuit diagram showing an adding circuit of the embodiment.

FIG. 6 is a circuit diagram showing a conventional IIR filter circuit.

[Explanation of symbols]

SH0 to SHN. . . Sample hold circuit M0 to MN / 2-1. . . Multiplication circuit II. . . Adder circuit SC. . . Scaler circuit INV, INV31, INV32, INV5, INV
6, INV71, INV72, INV81 to INV8
4, INV9. . . Inverter circuit RP. . . Resistance CC, CP. . . Capacitance C31, C32, C61-C68, C7p1-C7pN /
2-1, C7m1 to C7 mN / 2-1, C8p1 to C8pn, C8m1 to C8m
n. . . Input capacitance Co31, Co32, Co5, Co6, Co71, Co
72, C81-C84, C911-C91n, C921
~ C92n. . . Feedback capacitance ADD. . . Adder MUL. . . Multiplication unit S31, S32, S61 to S68, S911 to S91
n, S921 to S92n. . . switch. 1 Reference number = YZ1977032A

Claims (1)

[Claims] 1. A plurality of first signals for holding a plurality of signals in time series.
A sample and hold circuit; a plurality of first multiplication circuits for multiplying all or a part of the input signals held by the first sample and hold circuits by a predetermined first multiplier; a second sample and hold circuit for holding the input signal; A first adder for calculating the sum of the output of the second sample and hold circuit and the output of the first multiplying circuit; all or part of the output of the first adder and the signal held by the sample and hold circuit And a second adder circuit for calculating the sum of the outputs of the second multiplier circuit. The number of first sample-and-hold circuits is equal to the number of first samples. A direct-configuration IIR filter circuit set equal to a greater number of the first and second multiplication circuits connected to the hold circuit;
Each of the second multiplying circuits includes a plurality of multiplication input capacitances having a capacity corresponding to the weight of each bit of the binary number; and an odd-stage serial CMOS inverter in which the outputs of the multiplication input capacitances are connected while being integrated. A multiplication inverter circuit; a multiplication feedback capacitance connecting the output of the multiplication inverter circuit to its input;
A plurality of switches for connecting an input of the input capacitance for multiplication to an output of the adder or a reference voltage;
The first adder circuit includes an odd-numbered-stage series CMOS in which the outputs of the first multiplying circuit are input and the equal-capacity adding first input capacitances are connected; A first inverter circuit for addition comprising an inverter; and a first feedback capacitance for addition for connecting an output of the inverter circuit to an input thereof; the second addition circuit receives an output of a second multiplication circuit. A second input capacitance for addition having an equal capacity; a second inverter circuit for adding an odd-numbered series of CMOS inverters connected in an integrated manner to the outputs of the second input capacitance for addition; and the second inverter for addition. A second feedback capacitance for addition that connects the output of the circuit to its input.