JPH1198004A - Semiconductor circuit - Google Patents

Abstract

(57) [Summary] [PROBLEMS] To facilitate circuit design, increase circuit manufacturing margin, relax required area processing accuracy of elements, and reduce power consumption by miniaturization as a design suitable for miniaturization. An enabled semiconductor circuit is provided. SOLUTION: Transistors 3 and 4 are connected in parallel to two negative differential resistance elements 1 and 2, and complementary signals S and
As a configuration for inputting S ~, peak current values on the driver side and the load side can be modulated. In this circuit, the current flowing through the parallel circuit of the negative differential resistance element and the transistor changes greatly depending on the on / off of the transistor, so that the area of the negative differential resistance element can be precisely designed and processed as in the past. Therefore, it is not necessary to realize the current condition. Therefore, the circuit manufacturing margin can be increased and the area processing accuracy can be relaxed. As a result, miniaturization can be achieved, so that low power consumption and high speed can be achieved.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The technical field to which the present invention pertains is:
The present invention relates to a semiconductor circuit which has a high operation speed, is multifunctional, and has a large degree of freedom in design.

[0002]

2. Description of the Related Art Two examples are given as examples of the prior art close to the present invention. (First Prior Art Example) As a first prior art example, there is known a logic gate of a system in which two negative differential resistance elements are connected in series and a potential at the connection point is taken out as an output (Reference KJ. Chenet a1. Ext, Abs, “1994 Solid State Devi
ces and Materia 1s, "Yokohama, 1994, p979." Fig. 11 is a circuit diagram of the above-mentioned prior art. In Fig. 11, reference numeral 1 denotes a first negative differential resistance element, and 2 denotes a second negative differential resistance. The element 3 is a first field-effect transistor, and 5 is a driver-side composite element (a composite element of 1 and 3) The negative differential resistance element is, for example, a resonant tunneling diode.

The current-voltage characteristics of one negative differential resistance element are as shown in FIG. When two negative differential resistance elements are connected in series, the stable point of the system is the power supply voltage Vbi
It changes as shown in FIG. 13 according to as. First, FIG.
As shown in (a), when Vbias is smaller than twice the peak voltage Vp, the point A (voltage _VA ) is a stable point, and the output voltage is Vbias / 2. Vbias is increased and 2Vp
Is exceeded, the stability point of the system becomes B as shown in FIG.
And C, and the output voltage is V _B or V _C depending on the stable point.
Becomes Here, which of the stable points B and C is settled depends on the difference between the peak currents of the two negative differential resistance elements. For example, the larger the negative peak current differential resistance element 1 on the driver side, the state of the system point B, and the output voltage becomes V _B. The opposite, that is, the negative differential resistance element 2 on the load side
If the peak current is large, _VC is output. In order to form a logic circuit using this element, 2bias as Vbias
A drive voltage that changes periodically above and below is used. This acts as a clock and switching will occur when the voltage rises.

In order to operate this as a logic gate, it is necessary to modulate the peak current according to the input voltage. One method for that is to connect a field effect transistor in parallel with the negative differential resistance element. At this time, as shown in FIG. 14, the current flowing through the composite element is the sum of the current flowing through the negative differential resistance element and the current flowing through the field-effect transistor. become.

(Second prior art example) As a second prior art example, two negative differential resistance elements are connected in series, a transistor is connected in parallel with each negative differential resistance element, and a negative differential resistance element is connected. There is known a logic gate of a method of taking out the potential at the connection point as an output.
No.). FIG. 15 is a circuit diagram of the related art. In FIG. 15, reference numeral 4 denotes a second field-effect transistor;
Denotes a load-side composite element (composite element of 2 and 4), and the same reference numerals as in FIG. 11 denote the same elements.

The current-voltage characteristics of one negative differential resistance element are as shown in FIG. When the two negative differential resistance elements 1 and 2 are connected in series, the stable point of the system changes as shown in FIG. 16 according to the input voltages R and S to the two field effect transistors 3 and 4, respectively. I do. First, the current-voltage characteristic curve of the driver-side composite element 5 shows the input voltage R
Is "Low", it becomes D _L and the input voltage R
Is "High", it becomes like _DH . In addition, the current-voltage characteristic curve of the load-side composite element 6 becomes L _L when the input voltage S is “Low”, and L _H when the input voltage S is “High”. Therefore, the system has six stable points, L1, L2, LA, H1, H2, and HA, depending on the combination of the input voltages R and S.

When both the input voltages S and R are "Low",
The system can be in either the L1 or H1 state, but the R, S
Becomes "High", the stable point of the system is determined to be L2 or H2. After that, even if the input to the other one changes to “High”, the stable point changes like L2 → LA or H2 → HA and the output as a logic level (“High” or “Low”) ) Does not change. Also, the input that was “High” is “Low”.
, The stable point only changes like L2 → L1 or H2 → H1, and the output as a logic level (“Hi
gh ”or“ Low ”) does not change.

In order to form a logic gate using the above-described principle, a system bistable state (stable points: L1 and H1) obtained when a negative differential resistance element is connected in series is converted to a negative state. It is necessary to change to a monostable state (stable point: L2 or H2) by changing the current-voltage characteristic curve of the differential resistor. Therefore, by connecting a transistor to the negative differential resistance element in parallel, it is possible to change the effective current-voltage characteristics of the negative differential resistance element as shown in FIG.

[0009]

In order to form a logic gate by combining a negative differential resistance element and a field effect transistor as described above, there are the following problems. In the case of the first prior art, at the time of circuit design, a difference is made between the peak current values of two negative differential resistance elements connected in series, that is, when the input voltage is “Low” (〜0).
V), the sum of the current of the first field-effect transistor 3 and the peak current of the first negative differential resistance element 1 on the driver side is equal to the sum of the current of the second negative differential resistance element 2 on the load side. The input current is set to “High” so that the current is smaller than the peak current.
In such a case, the sum of the current of the first field-effect transistor 3 and the peak current of the first negative differential resistance element 1 is larger than the peak current of the second negative differential resistance element 2,
It is necessary to design the area of both negative differential resistance elements 1 and 2. Here, the peak current of the second negative differential resistance element 2 must be larger than the peak current of the first negative differential resistance element 1, and how large it is is an important parameter in design.

In the second prior art, when the input voltage R or S is "High", the negative differential resistance element is sufficiently large so that the state of the system transitions from the bistable state to the monostable state. Connecting transistors with high driving capability,
That is, for example, when the input voltage S is “High”,
The sum of the valley current of the second negative differential resistance element 2 on the load side and the current of the second field effect transistor 4 becomes larger than the peak current value of the first negative differential resistance element 1 on the driver side ( As shown in FIG. 16, the relationship between D _L and L _H ) requires that the gate width of the transistor be designed in consideration of the peak current value of the negative differential resistance element. Simply, the gate width should be wide, but the output of the preceding circuit is the input R and S to the circuit of the prior art. Therefore, in consideration of the driving ability of the preceding circuit, for high-speed operation, It is necessary to reduce the gate width of the transistor. Therefore, the gate width of the transistor is an important parameter in design.

Under the above-mentioned problems, there is no problem if the transistors always show the same current-voltage characteristics. However, in practice, the threshold voltage and the mutual conductance vary, and the circuit is manufactured as designed. It is very difficult to do.

Further, in the high-speed operation, the effect of the current flowing into the next stage must be considered. Specifically, the current flowing into the next stage is weighed by the current flowing through the driver-side composite element 5, and increases the effective driver-side peak current value. Therefore, in the case of the first prior art, even if the effective peak current on the driver side increases, the input voltage becomes “Lo”.
In the case of “w”, the input voltage is set to “H” while taking the area difference of the negative differential resistance element as large as possible so that the peak current of the load-side composite element 6 exceeds that of the effective driver side.
In the case of "high", a precise design of the element area, that is, a design with a small degree of freedom, that the peak current of the driver-side composite element 5 is limited to an area difference within a range in which the peak current can exceed that of the load side must be performed. No.

In the case of the second prior art example, when the input voltage S is "High" within the range of the gate width of the transistor which is limited by the driving capability of the preceding circuit, the driver-side composite element 5 than the effective peak current
In order to increase the valley current on the load side, a careful design must be made to increase the gate width of the transistor.

As a result, precision is required for both design and circuit fabrication. In addition, miniaturization of the element is restricted in order to secure the area processing accuracy of the element. When the above conditions are no longer satisfied due to variations in the electrical characteristics of the transistor and the negative differential resistance element caused by problems in the epitaxial structure and process, the circuit becomes inoperable immediately. Therefore, in order to make the above-mentioned conventional technology practical, it is important to increase the degree of freedom in circuit design and to provide a circuit with a function of compensating for variations in elements to increase the margin in circuit fabrication. The method was unknown.

SUMMARY OF THE INVENTION The present invention has been made to solve the problems of the prior art as described above. The present invention provides a circuit with a function of facilitating circuit design and a function of compensating for variations in electrical characteristics of elements. The purpose is to increase the circuit manufacturing margin and to reduce the required area processing accuracy of the element by this compensation function, and to enable low power consumption by miniaturization as a design suitable for miniaturization. I do.

[0016]

In order to achieve the above object, the present invention is structured as described in the appended claims. That is, in the present invention, a peak current modulation transistor is connected in parallel to two negative differential resistance elements, and a complementary signal is input to each of them, so that the peak current value on the driver side and the load side can be modulated. Things. With the configuration as described above, the current value flowing through the parallel circuit of the negative differential resistance element and the peak current modulation transistor greatly changes according to the on / off of the peak current modulation transistor.
By precisely designing and processing the area of the negative differential resistance element, it is not necessary to realize a desired current condition.
Therefore, the circuit manufacturing margin can be increased, and the required area processing accuracy of the element can be eased. Further, as a result of the reduction in the area processing accuracy, the negative differential resistance element can be miniaturized, so that the power consumption and the circuit operation can be speeded up by the miniaturization.

The contents of each claim are as follows. First, the invention according to claim 1 relates to a basic circuit configuration method, and this configuration corresponds to, for example, a logic gate in the embodiment shown in FIGS. 1 and 5.

The invention according to claims 2 and 3 relates to a circuit configuration method for generating an inversion signal of an input signal required for the circuit in claim 1 in the circuit. 3 and the logic gate in the embodiment shown in FIG.

Further, claims 4 and 5 show specific examples of the negative differential resistance element according to claims 1 to 3, and claim 4 uses a resonance tunnel diode. Item 5 uses an Esaki diode.

A sixth aspect of the present invention is directed to a configuration using a bipolar transistor instead of the field effect transistor according to the first to fifth aspects.

The invention described in claim 7 is the same as the invention described in claim 2.
A １ ／ frequency divider is configured using the configuration described in claim 3. This configuration corresponds to, for example, the embodiment shown in FIG.

[0022]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention relates to a dual negative differential resistor by connecting a field effect transistor to each of two serially connected negative differential resistance elements and inputting a complementary signal to both transistors. This is a circuit that enables control of a peak current value of a resistance element and obtains an output corresponding to an input signal in synchronization with a clock signal.

(First Embodiment) FIG. 1 is a circuit diagram showing a first embodiment, and FIG. 2 is a signal waveform diagram in FIG. This circuit is a circuit that outputs an inverted signal of an input signal in synchronization with a clock.

The circuit shown in FIG. 1 has two signal input terminals (S, S ~) and one clock input terminal (CLK),
Output terminals (Q). Here, the circuit connects the emitter electrode of the first negative differential resistance element 1 to ground, connects the collector electrode of the second negative differential resistance element 2 to the clock input terminal, The collector electrode and the emitter electrode of the second negative differential resistance element 2 are connected, and the drain electrode and the source electrode of the first field-effect transistor 3 are connected to the collector electrode of the first negative differential resistance element 1, respectively.
The second field effect transistor 4 connected to the emitter electrode
Are connected to the collector electrode and the emitter electrode of the second negative differential resistance element 2, respectively.
Output Q is the potential at the connection point of the first and second negative differential resistance elements.
Circuit. The input signal S is applied to the gate electrode of the first field-effect transistor 3, and the inverted signal S to the input signal is applied to the gate electrode of the second field-effect transistor 4.
Enter The parallel circuit of the first negative differential resistance element 1 and the first field effect transistor 3 is connected to the driver-side composite element 5 and the second negative differential resistance element 2 and the second field effect transistor 4 are connected in parallel. The circuit is named the load-side composite element 6.

As the negative differential resistance elements 1 and 2, a resonance tunnel diode or an Esaki diode can be used. Further, the field-effect transistor 3,
Instead of 4, a bipolar transistor can be used. In that case, the gate electrode, the source electrode, and the drain electrode of the field effect transistor may be replaced with the base electrode, the emitter electrode, and the collector electrode of the bipolar transistor, respectively.

The operation will be described below. In the circuit of FIG. 1, the voltage applied to the clock input terminal CLK is “Lo”
w ", the potential at the output terminal Q is always" Lo "
w ”and the voltage applied to CLK is“ Lo ”.
The value corresponding to the magnitude relationship between the effective peak current values of the load-side composite element 6 and the driver-side composite element 5 when changing from “w” to “High” is the clock input terminal C.
It is output while the voltage applied to LK is “High”. Further, even if the input signal changes while CLK is “High”, the output does not change.

A specific output determination process will be described. When “High” is applied as the input signal S to the gate electrode of the first field-effect transistor 3, the inverted signal S ~ of the input signal is input to the gate electrode of the second field-effect transistor 4. From “Low”. Therefore, the first field-effect transistor 3 is on and the second field-effect transistor 4 is off. Then, among the load-side composite element 6 and the driver-side composite element 5, the one having the larger peak current value is on the driver-side composite element 5, so that the output Q becomes “Low”. Conversely, “Lo” is input to the first field-effect transistor 3 as the input signal S.
w "is applied and" High "is applied to the second field-effect transistor 4 as the inverted signal S ~.
The first field-effect transistor 3 is turned off and the second field-effect transistor 4 is turned on, and the magnitude relation of the peak current densities is reversed, so that the output Q becomes “High”. Therefore, as shown in the timing diagram of FIG. 2, an inverted signal synchronized with the clock CLK of the input signal S is obtained as the output Q.

(Second Embodiment) FIG. 3 is a circuit diagram showing a second embodiment, and FIG. 4 is a signal waveform diagram in FIG. This circuit is also a circuit that outputs an inverted signal of an input signal in synchronization with a clock, similarly to FIG. In this circuit, the inverting element circuit 7 is constituted by a series circuit of a resistor and a field effect transistor, and outputs an inverted signal S ~ obtained by inverting the input signal S. The output of the inversion element circuit 7 is connected to be input to the gate electrode of the second field effect transistor 4. Other parts are the same as those of the circuit of FIG. As described above, by internally generating the inverted signal S１ of the input signal, the number of signal input terminals can be reduced to one.

The operation of the circuit with respect to the input signal S is the same as that in FIG. 1, and an inverted signal synchronized with the clock CLK of the input signal S is obtained as the output Q as shown in the timing diagram of FIG.

(Third Embodiment) FIG. 5 is a circuit diagram showing a third embodiment, and FIG. 6 is a signal waveform diagram in FIG. This circuit is a circuit that outputs an input signal in synchronization with a clock. The basic configuration of this circuit is shown in FIG.
Except that the input points of the input signal S and the inverted signal S ~ are opposite. That is, in the circuit of FIG. 5, the inverted signal SＳ of the input signal is input to the gate electrode of the first field-effect transistor 3, and the input signal S is input to the gate electrode of the second field-effect transistor 4.

The operation will be described below. In the circuit of FIG. 5, the voltage applied to the clock input terminal CLK is “Lo”
w ", the potential at the output terminal Q is always" Lo "
The value corresponding to the magnitude relationship between the effective peak current values of the load-side composite element 6 and the driver-side composite element 5 when the voltage applied to CLK changes from “Low” to “High”. However, when the voltage applied to CLK is "H"
The signal is output during “high”, and the CLK is “High”.
Even if the input signal changes during the period, the output does not change.

The specific output determination process will be described. When “High” is applied as an input signal S to the gate electrode of the second field-effect transistor 4, an inverted signal S ~ of the input signal is input to the gate electrode of the first field-effect transistor 3. From “Low”. Therefore, the first field-effect transistor 3 is off and the second field-effect transistor 4 is on. Then, since the peak current value of the load-side composite element 6 and the driver-side composite element 5 is larger on the load-side composite element 6 side, the output Q becomes “High”. vice versa,
"L" is input to the second field-effect transistor 4 as the input signal S.
ow "is applied, and" High "is applied to the first field-effect transistor 3 as the inverted signal S ~, the first field-effect transistor 3 is on and the second field-effect transistor 4 is off. And the magnitude relationship between the peak current densities is reversed, so that the output Q becomes “Low”.
That is, as shown in the timing diagram of FIG. 6, a signal synchronized with the clock of the input signal S is obtained as the output Q.

(Fourth Embodiment) FIG. 7 is a circuit diagram showing a fourth embodiment, and FIG. 8 is a signal waveform diagram in FIG. This circuit also outputs a signal synchronized with the clock of the input signal, as in FIG. In this circuit, the inverting element circuit 7 is constituted by a series circuit of a resistor and a field effect transistor, and outputs an inverted signal S ~ obtained by inverting the input signal S. The output of the inversion element circuit 7 is connected to be input to the gate electrode of the first field effect transistor 3. The other parts are the same as the circuit of FIG. As described above, by internally generating the inverted signal S１ of the input signal, the number of signal input terminals can be reduced to one.

The operation of the circuit with respect to the input signal S is the same as that shown in FIG. 5, and a signal synchronized with the clock CLK of the input signal S is obtained as the output Q as shown in the timing diagram of FIG.

(Fifth Embodiment) FIG. 9 is a circuit diagram showing a fifth embodiment of the present invention, and FIG. 10 is a signal waveform diagram in FIG. This circuit is an example in which the basic circuit of the present invention is combined to form a 1/2 static frequency divider that outputs a signal having a frequency half the frequency of the clock signal. The circuit shown in FIG. 9 connects the output of the circuit 8 shown in FIG. 3 as the input of the circuit 9 shown in FIG. 7, connects the output of the circuit 9 as the input of the circuit 8, and connects the output of the circuit 8 The configuration is such that the entire output R is input, CLK is input to the clock input terminal of the circuit 8, and the inverted signal CLK ~ of the CLK is input to the clock input terminal of the circuit 9.

The operation will be described below. In the circuit shown in FIG. 9, it is assumed that X is “Low” or “High” and the input to the circuit 8 is X. When CLK becomes "High", the output of the circuit 8, that is, the input of the circuit 9, becomes the inverted signal X of X. Next, when CLK ~ becomes "High", the output of the circuit 9, that is, the input of the circuit 8, becomes X ~.
Thus, the input to the circuit 8 is inverted in one cycle of the clock. Therefore, the input to the circuit 8 returns to the original state in two cycles of the clock. That is, if the output terminal Q is provided at the connection point between the circuit 8 and the circuit 9, the circuit shown in FIG. 9 operates as a frequency divider as shown in the timing diagram of FIG. The configuration of the inverting element circuit 7 is not limited to the illustrated one. For example, instead of a resistor as a load, an ingate FET or a depletion type FE is used.
T can be used.

[0037]

As described above, according to the present invention, a transistor for peak current modulation is connected in parallel to two negative differential resistance elements, and a complementary signal is input to each transistor. Since the peak current values on the driver and load sides can be modulated,
Unlike the conventional case, it is not necessary to realize a desired current condition by precisely designing and processing the area of the negative differential resistance element. Therefore, the circuit manufacturing margin can be increased, and the required area processing accuracy of the element can be eased. In addition, as the area processing accuracy is reduced, the negative differential resistance element can be miniaturized.
Effects such as low power consumption and high-speed circuit operation due to miniaturization are obtained.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a signal waveform diagram in the circuit of FIG.

FIG. 3 is a circuit diagram showing a second embodiment of the present invention.

FIG. 4 is a signal waveform diagram in the circuit of FIG. 3;

FIG. 5 is a circuit diagram showing a third embodiment of the present invention.

FIG. 6 is a signal waveform diagram in the circuit of FIG. 5;

FIG. 7 is a circuit diagram showing a fourth embodiment of the present invention.

FIG. 8 is a signal waveform diagram in the circuit of FIG. 7;

FIG. 9 is a circuit diagram showing a fifth embodiment of the present invention.

FIG. 10 is a signal waveform diagram in the circuit of FIG. 9;

FIG. 11 is a circuit diagram showing a first conventional example.

FIG. 12 is a current-voltage characteristic diagram of a negative differential resistance element.

FIG. 13 is a characteristic diagram showing a stable point of a system in which two negative differential resistance elements are connected in series.

FIG. 14 is a current-voltage characteristic diagram of a composite element including a negative differential resistance element and a field-effect transistor.

FIG. 15 is a circuit diagram showing a second conventional example.

FIG. 16 is a characteristic diagram showing a stable point of the system in the circuit of FIG. 15;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... 1st negative differential resistance element 2 ... 2nd negative differential resistance element 3 ... 1st field effect type transistor 4 ... 2nd field effect type transistor 5 ... Driver side composite element 6 ... Load side composite element 7 ... inverting element circuit 8 ... 1-input circuit for inverting the input signal in synchronization with the clock 9 ... 1-input circuit for outputting the input signal in synchronization with the clock S ... input signal S ~ ... input signal Inverted signal CLK ... Clock signal CLK ~ ... Inverted clock signal Vdd ... Power supply voltage

Claims (7)

[Claims] An emitter electrode of a first negative differential resistance element is grounded, and a collector electrode of a second negative differential resistance element is connected to a power supply terminal to which an oscillating voltage is applied. Connecting the collector electrode of the negative differential resistance element and the emitter electrode of the second negative differential resistance element, and connecting the drain electrode and the source electrode of the first field effect transistor to the collector of the first negative differential resistance element, respectively. An electrode, an emitter electrode, a drain electrode and a source electrode of a second field-effect transistor are connected to a collector electrode and an emitter electrode of the second negative differential resistance element, respectively, and the first and second field-effect transistors are connected. An input signal is applied to one of the gate electrodes of the transistor,
A semiconductor circuit, wherein an inverted signal of the input signal is input to the other one, and a potential at a connection point between the first and second negative differential resistance elements is output. 2. An input signal is input to a gate electrode of the first field-effect transistor, and a signal obtained by inverting the input signal via an inversion element circuit is input to a gate electrode of the second field-effect transistor. 2. The method according to claim 1, wherein
3. The semiconductor circuit according to claim 1. 3. An input signal is input to a gate electrode of the second field effect transistor, and a signal obtained by inverting the input signal via an inversion element circuit is input to a gate electrode of the first field effect transistor. 2. The method according to claim 1, wherein
3. The semiconductor circuit according to claim 1. 4. The semiconductor circuit according to claim 1, wherein a resonance tunnel diode is used as said negative differential resistance element. 5. An element according to claim 1, wherein an Esaki diode is used as said negative differential resistance element.
The semiconductor circuit according to any one of the above. 6. The field effect transistor according to claim 1, wherein the field effect transistor is replaced with a bipolar transistor, and the gate electrode, source electrode and drain electrode of the field effect transistor are replaced with a base electrode, an emitter electrode and a collector electrode of the bipolar transistor, respectively. 1 to Claim 5
The semiconductor circuit according to any one of the above. 7. An output of the semiconductor circuit A according to claim 2 is connected as an input of the semiconductor circuit B according to claim 3, and an output of the semiconductor circuit B is connected as an input of the semiconductor circuit A; The output of the semiconductor circuit A is used as the entire output, and a clock signal is applied to the collector electrode of the second negative differential resistance element of the semiconductor circuit A, and the collector electrode of the second negative differential resistance element of the semiconductor circuit B is used. Wherein the inverted clock signal is connected to each other so as to be input, and a signal obtained by dividing the clock signal by 出力 is output.